Intel + Parallelism Everywhere. James Reinders Intel Corporation

Transcription

1 Intel + Parallelism Everywhere James Reinders Intel Corporation

2 How to win at parallel programming 2

3 My Talk Hardware Parallelism and some insights INNOVATION: vectorization INNOVATION: tasking 3

4 Helping to Drive the Petascale Explosion Source: Top500.org 4 Years to go from 1 to 10 Petaflop/s systems <1 Year to grow from 10 to 20 Petaflop/s systems Intel Petaflop Systems Overall Petaflop Systems 4

5 Intel Xeon Processor E5 Family: Foundation of HPC Intel Xeon processor remains #1 architecture 78% of new Top500 systems (June 2012 listings) 100% 90% 80% 70% Architecture Presence in Top 500 Rapid Adoption of Intel Xeon Processor E5 Family 45 systems in Top500 just 3 months post-launch 60% 50% 40% 30% 20% Genci LRZ LLNL LANL University of Frankfurt 10% 0% Jun '06 Nov '06 Jun '07 Nov '07 Jun '08 Nov '08 Jun '09 Nov '09 Jun '10 Nov '10 Jun '11 Nov '11 Jun '12 Intel IBM Power AMD Other Source: Top500.org 5

6 140,000, ,000, ,000,000 80,000,000 60,000,000 40,000,000 20,000,000 Top500: Rapid Expansion in Total FLOPs Top500 FLOPs Growth 2.9 TFLOPs #4 on the Top Largest all Intel Xeon Processor Cluster Ever Source: Top500.org 6

7 Intel Xeon Phi coprocessor 1. Designed for Highly Parallel workloads 2. and Power efficiency 3. and Highly programmable 4. and Highly compatible to preserve software and expertise investments In Production In 2012, enabled by 22nm 3-D TriGate Transistors 7

8 Breakthrough Performance We re just getting started Preproduction hardware Pre-beta software Power Efficient Most power efficient supercomputer on list except Bluegene based systems 118 TFLOPs #150 on the Top500 8 Source: top500.org

9 Performance, Parallelism, Power Efficiency Intel Xeon Brand Industrial strength processing Enterprise, cloud, mission critical, & technical compute Intel Xeon Phi Brand Part of the Intel Xeon brand family Parallel performance to power breakthrough innovation Evokes many concepts in science & nature 9

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11 Source Multicore CPU Compilers Libraries, Parallel Models Multicore CPU Intel MIC architecture coprocessor 11

12 Game Changer Source Multicore CPU Compilers Libraries, Parallel Models Multicore CPU Intel MIC architecture coprocessor Unparalleled productivity most of this software does not run on a GPU - Robert Harrison, NICS, ORNL R. Harrison, Opportunities and Challenges Posed by Exascale Computing - ORNL's Plans and Perspectives, National Institute of Computational Sciences, Nov

13 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Amplifier XE, Intel Advisor 13

14 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Amplifier XE, Intel Advisor Intel Parallel Studio XE 14

15 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Amplifier XE, Intel Advisor Intel MPI Library Intel Trace Analyzer and Collector Intel Parallel Studio XE 15

16 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Amplifier XE, Intel Advisor Intel MPI Library Intel Trace Analyzer and Collector Intel Parallel Studio XE 16

17 Software Development Ecosystem 1 for Intel MIC Compilers, Run environs Open Source gcc (kernel build only, not for applications), Python Commercial Intel C++ Compiler, Intel Fortran Compiler, MYO, CAPS * HMPP * compiler, ScaleMP * Debugger gdb Intel Debugger, Rogue Wave * TotalView *, Allinea * DDT Libraries TBB 1, MPICH2, FFTW, NetCDF Profiling & Analysis Tools Workload Scheduler NAG *, Intel MKL, Intel MPI, OpenMP * (in Intel compilers), Cilk Plus (in Intel compilers), Coarrray Fortran (Intel), Rogue Wave * IMSL, Intel IPP Intel VTune Amplifier XE, Intel Trace Analyzer & Collector, Intel Inspector XE Altair * PBS Professional, Adaptive * Computing Moab 1 These are all announced. Intel has said there are more actively being developed but are not yet announced. Those in BOLD are available as of June Commercial support of TBB available from Intel. 17

18 Software Development Ecosystem 1 for Intel MIC Compilers, Run environs Open Source gcc (kernel build only, not for applications), Python Commercial Intel C++ Compiler, Intel Fortran Compiler, MYO, CAPS * HMPP * compiler, ScaleMP * Debugger gdb Intel Debugger, Rogue Wave * TotalView *, Allinea * DDT Libraries TBB 1, MPICH2, FFTW, NetCDF Profiling & Analysis Tools Workload Scheduler NAG *, Intel MKL, Intel MPI, OpenMP * (in Intel compilers), Cilk Plus (in Intel compilers), Coarrray Fortran (Intel), Rogue Wave * IMSL, Intel IPP Intel VTune Amplifier XE, Intel Trace Analyzer & Collector, Intel Inspector XE Altair * PBS Professional, Adaptive * Computing Moab 1 These are all announced. Intel has said there are more actively being developed but are not yet announced. Those in BOLD are available as of June Commercial support of TBB available from Intel. 18

19 My talk INNOVATION: tasking 19

20 Intel Threading Building Blocks threadingbuildingblocks.org C++ library Parallel tasks Outfits C++ for Parallelism. Introduced The most widely used abstraction for parallelism. Parallel algorithms Concurrent containers Synchronization primitives Scalable memory allocator 20

21 Intel Threading Building Blocks Generic Parallel Algorithms Efficient scalable way to exploit the power of multi-core without having to start from scratch Concurrent Containers Common idioms for concurrent access - a scalable alternative serial container with a lock around it Thread Local Storage Scalable implementation of thread-local data that supports infinite number of TLS Task scheduler The engine that empowers parallel Synchronization Primitives algorithms that employs task-stealing User-level and OS wrappers for to maximize concurrency mutual exclusion, ranging from atomic Miscellaneous Thread-safe timers OS API wrappers operations to several flavors of Threads mutexes and condition variables Memory Allocation Per-thread scalable memory manager and false-sharing free allocators 21

22 Intel Cilk Plus cilkplus.org Easy C / C++ syntax. Compiler knows that parallelism is goal, and helps. Like, TBB, inspired by proven Cilk research at M.I.T. 3 keywords Parallel tasks Hyper-objects Array notations Elemental functions Pragma SIMD 22

23 Intel Cilk Plus cilkplus.org Easy C / C++ syntax. Compiler knows that parallelism is goal, and helps. Like, TBB, inspired by proven Cilk research at M.I.T. 3 keywords Parallel tasks Hyper-objects Array notations Elemental functions Pragma SIMD 23

24 Intel Cilk Plus Est Parallel spawn in a recursive Fibonacci computation, in C, using Cilk Plus: Parallel function invocation, in C, using Cilk Plus: int fib (int n) { if (n < 2) return 1; else { int x, y; x = cilk_spawn fib(n-1); y = fib(n-2); cilk_sync; return x + y; } } Three keywords cilk_for (int i=0; i<n; ++i){ Foo(a[i]); } 24

25 My talk INNOVATION: vectorization 25

26 Intel Cilk Plus cilkplus.org Easy C / C++ syntax. Compiler knows that parallelism is goal, and helps. Like, TBB, inspired by proven Cilk research at M.I.T. 3 keywords Parallel tasks Hyper-objects Array notations Elemental functions Pragma SIMD 26

27 Auto Vectorization: Useful, but limited by language void v_add (float *c, float *a, float *b) { } for (int i=0; i<= MAX; i++) c[i]=a[i]+b[i]; C/C++ language implies that vectorizing this loop is illegal Some code can be re-written in a way that the compiler can vectorize Hard to learn Impossible to completely automate 27

28 Auto Vectorization: Useful, but limited by language Consider a Solution: Allow the programmer to express operations without unintended serial execution, using a new syntax. 28

29 What went wrong? Arrays not really in the language Pointers are evil pointers! 29

30 Fortran is the answer? a.k.a. Fortran got this right how could C and C++ be so wrong for vectorization? How can we patch things up? 30

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41 Intel Cilk Plus Powerful solution? Conversation starter? Ready for use, and ready for conversation. Both. Intel Compiler: Windows*, Linux*, Mac OS* X gcc: experimental branch Open Specification 41

42 Other inspiration ISPC: research compiler exploring SPMD on SIMD 42

43 TBB and Cilk Plus make a great combination Vector parallelism Cilk Plus has two syntaxes for vector parallelism Array Notation #pragma simd TBB relies on things outside TBB for vector parallelism. TBB + #pragma simd is an attractive combination Thread parallelism Cilk Plus is a strict fork-join language Straitjacket enables strong guarantees about space. TBB permits arbitrary task graphs Flexibility provides hanging rope

44 Vector Width 44

45 Vector Width Bottom line: Hardware vector capabilities are growing. Knights Corner makes them pretty interesting. Standard languages need help, C/C++ especially. TODAY: Pragmas + auto-vectorization offer most effective answer. We look to engage everyone in finding better ways. 45

46 My talk INNOVATION: tasking 46

47 Structured Parallel Programming using TBB and Cilk Plus Teaching structured parallel programming Designed for programmers not computer architects Teach best methods (known as patterns) Coming: next week 47

48 Intel Threading Building Blocks threadingbuildingblocks.org C++ library Parallel tasks Outfits C++ for Parallelism. Introduced The most widely used abstraction for parallelism. Parallel algorithms Concurrent containers Synchronization primitives Scalable memory allocator 48

49 Intel Threading Building Blocks threadingbuildingblocks.org + NEW FEATURE FLOW GRAPH Outfits C++ for Parallelism. Introduced The most widely used abstraction for parallelism. C++ library Parallel tasks Parallel algorithms Concurrent containers Synchronization primitives Scalable memory allocator 49

50 Intel TBB Class Graph: Components New Feature of TBB 4.0 Release Graph object Contains a pointer to the root task Owns tasks created on behalf of the graph Users can wait for the completion of all tasks of the graph Graph nodes Implement sender and/or receiver interfaces Nodes manage messages and/or execute function objects Edges Connect predecessors to successors Graph object == graph handle Edge Graph node 50

51 The flow graph has several node types: source_node continue_node function_node multioutput_function_node* Functional f() f() f(x) f(x) buffer_node queue_node priority_queue_node sequencer_node Buffering queueing join reserving join tag matching join split_node* or_node* Split / Join broadcast_node write_once_node overwrite_node limiter_node Other 51

52 "Using Intel TBB's new flow graph feature, we accomplished what was previously not possible, parallelize a very sizable task graph with thousands of interrelationships - all in about a week. Robert Link, GCAM Project Scientist, Pacific Northwest National Laboratory 52

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54 in early stages of investigation now no guarantees it will ever be available outside Intel A sneak peek at 54

55 in early stages of investigation now no guarantees it will ever be available outside Intel A sneak peek at 55

56 Motivation draw dependencies already created with TBB Some developers have created very complex graphs Sought help to visualize what they had created Performance analysis Challenging using traditional (ignorant) profilers Scaling estimation Create a dependency graph See what kind of scalability there is Create new graphs GUI drawing tool Can produce TBB code Will be able to edit output, or enter in GUI, either way the output is GraphML 56

57 TBB Flow Graph Designer Research prototype Able to: create dependency graphs visually perform basic rule-checks on the visual graph draw the graphs using various layout algorithms save graphs in an open format (GraphML) generate C/C++ code stubs capture and playback runtime traces of the graph 57

58 TBB Flow Graph Designer GUI Display themes Algorithms File options Edit Mode Layout algorithms Edit options TBB node types Diagnostics Graph Canvas Timeline of trace data 58

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60 TBB Flow Graph Designer Wish List Current wish list includes ability to: simulate a graph and generate the scalability plots set different weights for the nodes to indicate the computation complexity add lambda functions for each node and preserve this code in the graph state have more analyses algorithms available 60

61 Two modes of operation envisioned 1. As an analysis tool for existing flow graph apps 2. As a code development tool from creating and analyzing new flow graph apps Can go back and forth. Correctness and performance (critical path, subscription levels) assistance. 61

62 Learn more TBB flow graph designer (requests for beta ~ Q3) james. r. intel. com Intel Parallel Studio XE, Intel Cluster Studio XE intel.com / software / product Structure Parallel Programming (book ~ next week) parallelbook.com MIC Architecture / Xeon Phi intel.com / software / mic 62

63 Knights Corner Where to learn more 63

64 Knights Corner: Open Source Software Stack Open Source Software Stack for Knights Corner Consists of the following: Embedded Linux Minimally Modified GCC and Driver Software GDB Linux Kernel Tested with Red Hat * Enterprise 6.0, 6.1, and 6.2 and SuSE * Linux Enterprise Server (SLES) 11 SP1. 64 *Other names and brands may be claimed as the property of others.

65 Knights Corner Specifications 65

66 Winner Best HPC software product Unequaled Support for Parallelism 66 Mac OS* X Windows* MPI C Fortran TSX C++ MMX SSE AVX IMCI GraphML Cilk Plus

67 Learn more TBB flow graph designer (requests for beta ~ Q3) james. r. intel. com Intel Parallel Studio XE, Intel Cluster Studio XE intel.com / software / product Structure Parallel Programming (book ~ next week) parallelbook.com MIC Architecture / Xeon Phi intel.com / software / mic 67

68 Legal Disclaimer & Optimization Notice INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO THIS INFORMATION INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, reference Copyright 2012, Intel Corporation. All rights reserved. Intel, the Intel logo, Xeon, Core, Phi, VTune and Cilk are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Optimization Notice Intel s compilers may or may not optimize to the same degree for non-intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessordependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #