UNIVERSITY OF OSLO. Faculty of Mathematics and Natural Sciences

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1 Page 1 UNIVERSITY OF OSLO Faculty of Mathematics and Natural Sciences Exam in : FYS4220/ FYS9220 Day of exam : 16. December 2010 Exam hours : This examination paper consists of 6 page(s). Appendices: Permitted materials: Lectures with notes, lab exercises with solutions, and the book "Digital System Design with VHDL, Second Edition, by Mark Zwolinski. Make sure that your copy of this examination paper is complete before answering. Problem 1: a) What kind of hardware elements can the following VHDL code be synthesized to: signal m : std_logic; b) Given the following concurrent statement: y <= a when choice = '1' else b; What is the name of this type of logic circuit element? c) Implement in VHDL the combinational logic described in b) using a process d) Write the VHDL signal assignment(s) for the signal X shown in Figure 1, in order to produce this waveform for use in a test bench: Figure 1: Waveform of the signal X

2 e) Given that you are to implement the waveform shown in Figure 1 into a synthesizable VHDL code (for use in an FPGA), describe shortly (with a few sentences) how this could be implemented. f) Write the VHDL code (both entity and architecture) for the 3-8 decoder (combinational logic) described by the truth table in Table 1. Inputs Outputs x y z D0 D1 D2 D3 D4 D5 D6 D Table 1: Truth table for the 3-8 decoder g) Given that you are to implement an embedded system on a programmable chip (SOPC) that includes the following characteristics: 1. A time critical part that requires high performance and parallel processing 2. A complex data processing algorithms (including floating point calculations) 3. An RS-232 connection for communication What kind of programmable logic (circuit technology) and implementation strategy would you use? Justify your answer. Problem 2: In this problem you are to implement the Finite State Machine (FSM) of an alarm system. The system clock available for the FSM is a 1 Hz clock. The alarm system has three sensors, and their signals are combined in the input vector called Sensors. The FSM has six states, named Init, AlarmOff, DelayAlarm, ConfirmOn, AlarmOn and Burglary.

3 The entity of the FSM, describing the input and output signals, is as follows: entity AlarmSystem is port ( sclk in : std_logic; -- system clock, 1 Hz areset in : std_logic; -- asynchronous reset On in : std_logic; -- alarm on Off in : std_logic; -- alarm off Sensors in : std_logic_vector (2 downto 0); -- [S1 S2 S3] codeok in : std_logic; -- Alarm code status StatusLED out : std_logic; -- light indicator for system status BreachLED out : std_logic; -- light indicator for a breach Sound out : std_logic -- sound signal when burglary ); end AlarmSystem The relationship between the output signals and the states are given in Table 2. Outputs State StatusLED BreachLED Sound Init AlarmOff DelayAlarm ConfirmOn AlarmOn Burglary Table 2: State-output table for the FSM a) Write the VHDL code for the security alarm systems Finite State Machine (FSM), as described in the ASM chart in Figure 2 and in the state-output table in Table 2. Use the state and signal names as defined in this text. The FSM should also satisfy the following requirements: The FSM should use the rising edge of the system clock (sclk) The FSM should have an asynchronous reset (using the areset signal) The FSM s VHDL code should include fault tolerance (i.e. the FSM should be able to get out of illegal/undefined states) b) What is the approximate time delay in seconds from the alarm system is turned on by the user (On signal goes logic high) to the alarm system is activated (the state machine gets into the AlarmOn state)?

4 Figure 2: ASM chart for the security alarm FSM. YES = 1, NO = 0 ;

5 Problem 3: 3.1 How can signals be used in Real-Time/embedded systems? 3.2 The code below (header files not shown) causes one compilation error. Why? What other faults are there in SignalHandler()? /* global scope */ SEM_ID semsignal; int volatile signalnumber; void SignalHandler (int sig, struct siginfo *info, void *pcontext) { semtake (semsignal, WAIT_FOREVER); signalnumber = sig; semgive (semsignal); printf("signal received %d\n", signalnumber); goto entryfromsignalhandler; } STATUS main() { int signalvalue; if ((semsignal = semmcreate (SEM_Q_FIFO)) == (SEM_ID) NULL) exit (ERROR); /* semmcreate initializes the semaphore to FULL. Since option SEM_INTERRUPTIBLE is not set, a signal sent to a blocked task will not wakeup the task */ /*--- install SignalHandler etc ---*/ entryfromsignalhandler: semtake (semsignal, WAIT_FOREVER); signalvalue = signalnumber; /*--- do something ---*/ semgive (semsignal); /*--- and continue until you want to go home ---*/ semdelete (semsignal); return (OK); } 3.3 Propose a logical specification of a Real-Time system for measuring on and monitoring of three physical variables Temperature (T), Pressure (P) and Speed (S). The specification shall include 1) block schematics over the activities and the communication between these, and 2) flow charts or pseudo code for the respective activities. The proposed design shall be qualified (justified). Neither computer hardware nor instrumentation shall be specified, and no code shall be written. Reading of input data is shown with statements of type readtemp(), readpressure() and readspeed(). The values shall be tested against low and high boundary values, denoted lowtemp/hightemp, lowpressure/highpressure, lowspeed/highspeed. The data shall be stored in a common data structure in shared memory. The organization of the data structure shall not be specified. I/O calls are shown with expressions of the type write/read Tdata. Why must access of the data structure be controlled through mutual exclusion? How can that be done?

6 For data outside boundary values a process taskalarm shall be triggered with information about the type of alarm. Specify the choice of the inter-process communication method for sending the alarm type to taskalarm. Also alarms shall be logged in DataBase. The system, data and alarms are monitored by a process taskmonitor. How taskmonitor shall present the information is outside the scope of this exercise. The system is started, initialized and controlled by a process taskcontrol. Activity taskcontrol : Temp : Pressure : Speed : taskmonitor : taskalarm: Period interactive 5 sek 5 sek 2 sek 1 sek sporadic 3.4 What relative process priorities shall be assigned to these activities? Justify. 3.5 What system calls in VxWorks shall be used for periodic execution? Problem 4: 4.1 What is the role of the component of the operating system called scheduler, and what problems and challenges are there regarding resource allocation in Real Time systems? 4.2 Give a short explanation of VxWorks Wind preemptive priority-based - and round-robin scheduling, and their relevance for Real Time systems. 4.3 What does the relation below (ref. Liu og Leyland) expresses? For N = 3 and 4 the values on the right hand side are approximately 0.78 and 0.75, respectively Three processes have periods = [80, 40, 16] and WCE (Worst Case Execution time) = [16,5,2]. Can these periodic processes meet their deadlines? How is deadline defined? 4.5 What are their relative process priorities based on Rate Monotonic Priority Assignment? 4.6 The system is extended with a fourth process of type sporadic. If WCE 4 = 1, what is the shortest inter-arrival time in order that U shall not exceed 0.70? 4.7 Under what circumstances can a process with lower priority block a higher priority process? How can the effect of blocking be reduced by the operating system?