VHDL Essentials Simulation & Synthesis

Transcription

1 VHDL Essentials Simulation & Synthesis Course Description This course provides all necessary theoretical and practical know-how to design programmable logic devices using VHDL standard language. The course goes into great depth, and touches upon every aspect of the standard with directly connected to the topics needed in the industry today. The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory and also include practical digital design. The course begins with an overview of the current programmable logic devices and their capabilities, continues with an in-depth study of VHDL language with all of its structures, involves writing test-bench programs and employ a simulation tool. The course ends with a synthesis overview and emphasizes the difference between testing code and synthesizable code. Course Duration 5 days Goals 1. Become familiar with FPGA and CPLD families and their capabilities 2. Understand the design process from specification up to programming and final verification on board 3. Implement combinational and sequential processes 4. Build a hierarchy (bottom-up and top-down) 5. Write test-benches 6. Write generic code for design reuse 7. Understand coding style considerations for synthesis Intended Users Hardware engineers who would like start developing FPGA or CPLD System engineers who would like to upgrade their professional skills

2 Previous Knowledge A basic background in digital logic Course Material 1. Simulator: Modelsim or ActiveHDL 2. Synthesizer and Place & Route: Quartus II (ALTERA) or Precision (Mentor Graphics) 3. Demonstration on ALTERA Evaluation board Table of Contents Day #1 Introduction to Programmable Logic Devices o CPLD architecture and design consideration o FPGA architecture LUT FF PLL DSP Block Embedded RAM Embedded Processor FPGA Programming process Introduction to VHDL Language o VHDL history o Digital design o FPGA design Simulation Synthesis Place & Route Programming Verification o Advantages of VHDL o Simulation & Synthesis o Demonstration of whole process on board

3 VHDL Basic Structures Overview o Entity o Component o Architecture o Process o Functions & Procedures o Package & Package Body o Library o Configuration o Top down design VHDL Design Units Building a Hierarchy o Building MUX from its primitives o Port Map o Test bench and simulation More on Entities o Ports name o Direction In Out InOut Buffer o Data types o Generic o Generic map Architecture Bodies o Architecture Declarative Part o Behavioral Description o Data Flow Description o Structural Description Concurrent Statements o Simple signal assignment o Concurrent signal assignment o Implementation of signals o Conditional signal assignments Day #2

4 When-Else With-Select o Examples of mux and encoder VHDL Timing Model o Inertial delay o Transport delay o Delta delay o Reject reserved word o Demonstration Grammar and Declarations o Data Types & Data Objects o Enumeration Types o Attributes, Subtype o Numeric Data Types (Integer & Real) o Physical Data Types o Composite Data Types Array Array attributes Record Aggregate Multi-Dimensional Array Day #3 Sequential Processing o Process definition o Sensitivity list o Declaration area o Statement area o Sequential execution o Demonstration o Concurrent signal assignment versus process Sequential Control Statements o If-Elsif-Else statement o Case Statement o Loop statement

5 o Next & Exit Loop control statements o Null o Assert statement o Wait statement Day #4 Process Behavior o Signal assignment inside and outside a process o Signal and variable assignment differences o Process communication o Understanding the simulator algorithm o Passive process Modeling Finite State Machines o FSM concept o Mealy & Moore Models o HDL coding style One process Two processes Three processes Mealy & Moore o State encoding Sequential Johnson One Hot Two Hot Defined by user Defined by synthesis o Handling the unused states o Reset & Fail Safe Behavior o Interactive State Machines Unidirectional Bi-Directional

6 Day #5 Package & Package Body o Package declaration o Package Body declaration o Information hiding o Deferred constant o Reuse methodology o IEEE packages Sub Programs: Functions & Procedures o Where to declare subprogram o Functions Name Input parameters Return type Declaration part Statement part o Variables in functions o Impure functions o Resolution functions o Conversion functions o Standard functions o Procedures Name Input & Output parameter Declaration part Statement part Side effects o Matching Object Classes of Formals & Actuals in Subprograms o Function versus Procedure Introduction to Synthesis o What is Synthesis o Synthesis tools o VHDL programs for synthesis versus for simulation o Coding style and pitfalls o Demonstration