Department of Electronics & Communication Engineering Lab Manual E-CAD Lab

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1 Department of Electronics & Communication Engineering Lab Manual E-CAD Lab Prasad V. Potluri Siddhartha Institute of Technology (Sponsored by: Siddhartha Academy of General & Technical Education) Affiliated to JNTU- Kakinada Approved by AICTE- New Delhi Kanuru, Vijayawada-7

2 List of Experiments. LOGIC GATES 2. IC7474 A POSITIVE EDGE TRIGGERING D FLIP FLOP 3. IC 74x9 DECADE COUNTER 4. IC 74x93 4 -BIT BINARY COUNTER 5. IC 74x95 SHIFT REGISTER 6. IC 74x94 UNIVERSAL SHIFT REGISTER 7. 3x8 DECODER 8. IC 74x85 4-BIT COMPARATOR 9. 8x MULTIPLEXER. 6X MULTIPLEXER. IC 74X89 READ AND WRITE OPERATIONS OF RAM

3 .LOGIC GATES AIM: Write a VHDL code for all the logic gates. #-TITLE: AND gate LOGIC GATE SYMBOL: TRUTH TABLE: 748N x y z VHDL CODE: Library IEEE; use IEEE.std_logic_64.all; entity AND2 is port( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC end AND2; Dept. of ECE, PVPSIT.

4 --Dataflow model architecture behav of AND2 is Z<= x and y; --Signal Assignment Statement end behav; -- Behavioral model architecture behav2 of AND2 is process (x, y) if (x='' and y='') then -- Compare with truth table Z <= ''; else Z <= ''; end if; end process; end behav2; OUT PUT WAVE FORM: Dept. of ECE, PVPSIT. 2

5 #2-TITLE: OR gate LOGIC GATE SYMBOL: TRUTH TABLE: 7432 x y z VHDL CODE: Library IEEE; use IEEE.std_logic_64.all; entity OR2 is port( end OR2; x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC --Dataflow model architecture behav of OR2 is Z <= x or y; --Signal Assignment Statement end behav; Dept. of ECE, PVPSIT. 3

6 -- Behavioral model architecture behav2 of OR2 is process (x, y) if (x='' and y='') then -- Compare with truth table Z <= ''; else Z<= ''; end if; end process; end behav2; OUTPUT WAVEFORM: #3-TITLE: NOT gate LOGIC GATE SYMBOL: 744 Dept. of ECE, PVPSIT. 4

7 TRUTH TABLE: x z VHDL CODE: Library IEEE; use IEEE.std_logic_64.all; entity not is port( X: in STD_LOGIC; Z: out STD_LOGIC end not; --Dataflow model architecture behav of not is Z<= not X; --Signal Assignment Statement end behav; -- Behavioral model architecture behav2 of not is process (X) if (x='') then -- Compare with truth table Z <= ''; else Z<= ''; Dept. of ECE, PVPSIT. 5

8 end if; end process; end behav2; OUTPUT WAVEFORM: #4-TITLE: NAND gate LOGIC GATE SYMBOL: TRUTH TABLE: 74 x y z Dept. of ECE, PVPSIT. 6

9 VHDL CODE: Library IEEE; use IEEE.std_logic_64.all; entity nand2 is port( end nand2; --Dataflow model x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC architecture behav of nand2 is z<= x nand y; --Signal Assignment Statement end behav; -- Behavioral model architecture behav2 of nand2 is Process (x, y) Begin If (x='' and y='') then -- Compare with truth table Z <= ''; else Z <= ''; end if; end process; end behav2; Dept. of ECE, PVPSIT. 7

10 OUTPUT WAVEFORM: #5- TITLE: NOR gate LOGIC GATE SYMBOL: TRUTH TABLE: 742 x y z VHDL CODE: Library IEEE; use IEEE.std_logic_64.all; entity nor2 is Port ( end nor2; X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC Dept. of ECE, PVPSIT. 8

11 --Dataflow model architecture behav of nor2 is end behav; -- Behavioral model architecture behav2 of nor2 is Z<= x nor y; --Signal Assignment Statement process (x, y) If (x='' and y='') then -- Compare with truth table Z <= ''; else Z <= ''; end if; end process; end behav2; OUTPUT WAVEFORM: Dept. of ECE, PVPSIT. 9

12 #6-TITLE: EX-OR gate LOGIC GATE SYMBOL: TRUTH TABLE: 7486 x y z VHDL CODE: Library IEEE; use IEEE.std_logic_64.all; entity xor2 is Port ( X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC end xor2; --Dataflow model architecture behav of xor2 is end behav; Z<= x xor y; --Signal Assignment Statement Dept. of ECE, PVPSIT.

13 -- Behavioral model architecture behav2 of xor2 is process (x, y) If (x/=y) then Z <= ''; else Z<= ''; end if; -- Compare with truth table end process; end behav2; OUTPUT WAVEFORM: #7-TITLE: EX-NOR gate LOGIC GATE SYMBOL: 7435 Dept. of ECE, PVPSIT.

14 TRUTH TABLE: x y z VHDL CODE: Library IEEE; use IEEE.std_logic_64.all; entity xnor2 is Port ( end xnor2; --Dataflow model X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC architecture behav of xnor2 is end behav; Z<= x xnor y; --Signal Assignment Statement -- Behavioral model architecture behav2 of xnor2 is process (x, y) Dept. of ECE, PVPSIT. 2

If (x=y) then Z <= ''; else Z<= ''; end if; -- Compare with truth table end process; end behav2; OUTPUT WAVEFORM: VIVA QUESTIONS:. Implement the following function using VHDL coding.

15 If (x=y) then Z <= ''; else Z<= ''; end if; -- Compare with truth table end process; end behav2; OUTPUT WAVEFORM: VIVA QUESTIONS:. Implement the following function using VHDL coding. (Try to minimize if you can). F(A,B,C,D)=(A +B+C). (A+B +D ). (B+C +D ). (A+B+C+D) 2. What will be the no. of rows in the truth table of N variables? 3. What are the advantages of VHDL? 4. Design Ex-OR gate using behavioral model? 5. Implement the following function using VHDL code f=ab+cd. 6. What are the differences between half adder and full adder? 7. What are the advantages of minimizing the logical expressions? 8. What does a combinational circuit mean? 9. Implement the half adder using VHDL code?. Implement the full adder using two half adders and write VHDL program in structural model? Dept. of ECE, PVPSIT. 3

16 2.IC7474 A POSITIVE EDGE TRIGGERING D FLIP FLOP AIM: Write a VHDL code for IC7474 a positive edge triggering D flip flop. TITLE: IC7474 a positive edge triggering D flip flop. CIRCUIT DIAGRAM: TRUTH TABLE: clr_l pr_l Clk d q qn X X X X X X Dept. of ECE, PVPSIT. 4

17 VHDL CODE: --VHDL code for the circuit library IEEE; use ieee.std_logic_64.all; entity dff is port ( pr_l: in STD_LOGIC; -- active low preset input clr_l:in STD_LOGIC; -- active low clear input clk :in STD_LOGIC; -- clock input d :in STD_LOGIC; -- D input q :inout STD_LOGIC; -- output of D flip flop end dff; architecture dff of dff is signal e,f,g,h:std_logic; component nand3 port ( qn :inout STD_LOGIC -- inverted output a,b,c: in STD_LOGIC; d : out STD_LOGIC end component; g:nand3 port map(pr_l,h,f,e -- creates g gate g2:nand3 port map(clr_l,e,clk,f -- creates g2 gate g3:nand3 port map(f,clk,h,g -- creates g3 gate g4:nand3 port map(g,clr_l,d,h -- creates g4 gate g5:nand3 port map(pr_l,f,qn,q -- creates g5 gate g6:nand3 port map(q,g,clr_l,qn -- creates g6 gate end dff; --VHDL code for 3 i/p nand gate library IEEE; use IEEE.std_logic_64.all; entity nand3 is port ( a,b,c: in STD_LOGIC; d : out STD_LOGIC end nand3; Dept. of ECE, PVPSIT. 5

$architecture \nand\ of nand3 is d<=$ $nand gate end \nand\; WAVEFORMS: D$

18 architecture \nand\ of nand3 is d<= not (a and b and c -- creates a 3 i/p nand gate end \nand\; WAVEFORMS: D FLIPFLOP NAND GATE Dept. of ECE, PVPSIT. 6

19 VIVA QUESTIONS:. Write the behavioral code for the IC 74x Write the dataflow code for the IC 74x What is the difference between sequential and combinational circuit? 4. What is a flip-flop? 5. Explain the functions of preset and clear inputs in flip-flop? 6. What is meant by a clocked flip-flop? 7. What is meant by excitation table? 8. What is the difference between flip-flop and latch? 9. What are the various methods used for triggering flip-flops?. Explain level triggered flip-flop?. Write the behavioral code for IC 74X Write the syntax of IF statement? Dept. of ECE, PVPSIT. 7

20 Dept. of ECE, PVPSIT. 8 3.IC 74x9 DECADE COUNTER AIM:To write the VHDL code for IC 74x9 decade counter. CIRCUIT DIAGRAM OF IC 74x9: TRUTH TABLE: OUTPUT Q() Q(3) Q(2) Q()

21 VHDL CODE: --To work as a decade counter library IEEE; Use IEEE.std_logic_64.all; entity count is port ( S, s, r, r: in STD_LOGIC; --set and reset i/ps for mod2 and -- Mod5 counters Clk: in STD_LOGIC; --Clock signal for mod2 counter Clk: inout STD_LOGIC; --Clock signal for mod5 counter end count; q : inout STD_LOGIC_VECTOR(3 downto ) --o/p of -- mod2 X mod5= mod architecture count of count is component jk_ff -- jk flip flop instantiation port ( jk : in STD_LOGIC_VECTOR( downto clk,pr_l,clr_l : in STD_LOGIC; q,nq : inout STD_LOGIC end component; signal preset,clear,s, q3bar:std_logic; preset <= s nand s; clear <=r nand r; S<=q(2) and q( q3bar <= not q(3 clk<=q( -- common preset inputs for mod2 and mod5 counters -- common reset inputs for mod2 and mod5 counters -- to set the last flip flop -- complemented output of q(3) --to work as asynchronous mod counter jk:jk_ff port map("",clk,preset,clear,q(),open jk2:jk_ff port map(jk()=> q3bar, jk()=>'', clk=>clk, pr_l=>preset, Dept. of ECE, PVPSIT. 9

22 clr_l=>clear, q=>q(), nq=>open -- jk.jk2,jk3,jk4 create four JK flip flops jk3:jk_ff port map("",q(),preset,clear,q(2),open jk4:jk_ff port map(jk()=>q(3), jk()=>s, clk=>clk, pr_l=>preset, clr_l=>clear, q=>q(3), nq=> q3bar end count; WAVEFORMS: Dept. of ECE, PVPSIT. 2

23 --Program for JK flip-flop library IEEE; use IEEE.std_logic_64.all; entity jk_ff is port ( jk : in STD_LOGIC_VECTOR( downto --jk()=j;jk()=k; clk,pr_l,clr_l : in STD_LOGIC; q,nq end jk_ff; : inout STD_LOGIC architecture jk of jk_ff is process(clk,pr_l,clr_l,jk) variable temp:std_logic:=''; q<='';nq<=''; if (pr_l='' and clr_l='') then q<='';nq<=''; elsif (pr_l='' and clr_l ='') then q<='';nq<=''; elsif (pr_l='' and clr_l='') then if (clk 'event and clk='') then --performs during the falling edge of clock end jk; case jk is when ""=>temp:=temp; when ""=>temp:=''; when ""=>temp:=''; when ""=>temp:=not temp; when others=>null; end case; end if; q<=temp; nq<= not temp; end if; end process; Dept. of ECE, PVPSIT. 2

WAVEFORMS: VIVA QUESTIONS:.Write the behavioral code for IC 74x9..What is a sequential circuit? 2.Differentiate between synchronous and asynchronous counter? 3.How many no.

24 WAVEFORMS: VIVA QUESTIONS:.Write the behavioral code for IC 74x9..What is a sequential circuit? 2.Differentiate between synchronous and asynchronous counter? 3.How many no.of flip-flops are required for decade counter? 4.What is meant by excitation table? 5.What are the meanings of different types of values in std_ulogic? 6.What are the objects in VHDL? 7.Write the syntax for a signal? 8.Write the difference between signal and variable? 9.Explain about enumeration types?.if the modulus of a counter is 2 how many flip-flops are required? Dept. of ECE, PVPSIT. 22

25 Dept. of ECE, PVPSIT IC 74x93 4 -BIT BINARY COUNTER AIM:To write the VHDL code for IC 74x93 4 -bit binary counter. TRUTH TABLE: OUTPUT Q(3) Q(2) Q() Q() CIRCUIT DIAGRAM OF IC74X93:

26 VHDL CODE: --Program for 4-bit counter library IEEE; use IEEE.std_logic_64.all; entity cnt is port ( clk: in STD_LOGIC; mr: in STD_LOGIC; mr: in STD_LOGIC; clk: inout STD_LOGIC; Q:inout STD_LOGIC_VECTOR(3 downto ) end cnt; architecture cnt of cnt is Component tff -- T- flip flop instantiation port ( t : in STD_LOGIC; clk : in STD_LOGIC; clr_l : in STD_LOGIC; q,nq : out STD_LOGIC end component; signal clear : std_logic; clear<= mr nand mr; -- common reset inputs for mod2 and mod8 --counters CLK<=q( --to work as asynchronous mod6 counter t:tff port map('',clk,clear,q(),open--t,t2,t3,t4 create four T-flip flops t2:tff port map('',clk,clear,q(), open t3:tff port map('',q(),clear,q(2), open t4:tff port map('',q(2),clear,q(3), open end cnt; Dept. of ECE, PVPSIT. 24

27 WAVEFORMS: --Program for T flip-flop library IEEE; use IEEE.std_logic_64.all; entity tff is port ( t : in STD_LOGIC;--input to the T-flip flop clk : in STD_LOGIC;--Clock signal for T-flip flop clr_l : in STD_LOGIC;--active low clear input q,nq : out STD_LOGIC--actual and complemented outputs of T-flip flop end tff; architecture tff of tff is process(t,clk,clr_l) variable temp:std_logic:=''; if (clr_l='') then temp:=''; Dept. of ECE, PVPSIT. 25

elsif ((clr_l='') and (clk'event and clk='')) then--perfoms during falling edge if ( t='') then temp:=temp; else temp:= not temp; end if; end if; q<= temp; nq<= not temp; end process; end tff;

28 elsif ((clr_l='') and (clk'event and clk='')) then--perfoms during falling edge if ( t='') then temp:=temp; else temp:= not temp; end if; end if; q<= temp; nq<= not temp; end process; end tff; WAVEFORMS: VIVA QUESTIONS:. Write the behavioral code for IC 74x What is the difference between decade counter and 4 bit counter? 3. What is meant by a modulus of a counter? 4. Write the behavioral code for IC74X93? 5. Explain the operation of IC74X93? 6. Write the syntax for component instantiation? 7. What is netlist? 8. Briefly explain about generics? 9. Write the difference between sequential statement and concurrent statement?. Write the syntax for loop statements?. Write the syntax for generate statements? 2. Write the differences between loop and generate? Dept. of ECE, PVPSIT. 26

29 5.IC 74x95 SHIFT REGISTER AIM:To write the structural program for IC 74x95 SHIFT REGISTER. TRUTH TABLE: mode control clock clk function Serial operation q(2) to q(3), q() to q(2), q() to q(), si to q() clk Parallel operation A to q() B to q() C to q(2) D to q(3) CIRCUIT DIAGRAM OF IC 74X95: Dept. of ECE, PVPSIT. 27

30 VHDL CODE: --Structural model --Program for shift register library IEEE; use IEEE.std_logic_64.all; entity shift_reg is port ( a,b,c,d: in STD_LOGIC; --four parallel inputs si : in STD_LOGIC; --one serial input m : in STD_LOGIC; --mode control clk :in STD_LOGIC; --clock for serial input clk :in STD_LOGIC; --clock for parallel input end shift_reg; q architecture shift_reg of shift_reg is component mux -- multiplexer instantiation port ( :inout STD_LOGIC_VECTOR (3 downto )--4-bit output a,b,c,d: in STD_LOGIC; z : out STD_LOGIC end component ; component dff -- D- flip flop instantiation port ( d,clk: in STD_LOGIC; q : out STD_LOGIC end component; signal nm,c,do,d,d2,d3:std_logic; nm<= not m; g:mux port map(clk,nm,clk,m,c --to select the clock based on mode -- control g2:mux port map(si,nm,a,m,do --g2,g3,g4,g5 are used to select g3:mux port map(q(),nm,b,m,d --either serial input or parallel input g4:mux port map(q(),nm,c,m,d2 --based on mode control g5:mux port map(q(2),nm,d,m,d3 d:dff port map(do,c,q() --d,d2,d3,d4 creates four D flip flops d2:dff port map(d,c,q() --to perform either serial or parallel shift d3:dff port map(d2,c,q(2) -- operations d4:dff port map(d3,c,q(3) end shift_reg; Dept. of ECE, PVPSIT. 28

31 WAVEFORMS: --program for D-flip-flop library IEEE; use IEEE.std_logic_64.all; IC 74x94 UNIVERSAL SHIFT REGISTER entity dff is port ( end dff; d,clk: in STD_LOGIC; q : out STD_LOGIC architecture dff of dff is process(clk) if( clk'event and clk='') then q<=d; else null; end if; end process; end dff; --performs during falling edge Dept. of ECE, PVPSIT. 29

32 WAVEFORMS: --Program for multiplexer library ieee; use ieee.std_logic_64.all; entity mux is port ( end mux; a,b,c,d: in STD_LOGIC; z : out STD_LOGIC architecture mux of mux is z<=((a and b) or (c and d) end mux; WAVEFORMS: Dept. of ECE, PVPSIT. 3

33 VIVA QUESTIONS:. Write the behavioral code for IC 74x What is a shift register? 3. Write some applications of shift register? 4. Explain briefly about BLOCK? 5. Write the syntax for function? 6. Write the syntax for procedure? 7. How to define variable in VHDL? 8. Write the syntax for CASE statement? 9. What is the advantage of case statement over if-else statement?. Write the difference between with-select and when-else statement? Dept. of ECE, PVPSIT. 3

34 6.IC 74x94 UNIVERSAL SHIFT REGISTER AIM: To write the VHDL code for IC 74x94 universal shift register. BLOCK DIAGRAM: TRUTH TABLE: Clr_l S() S() Clk Output function X X X no change shift right ( dsr to q()) shift left ( dsl to q(3)) load data (parallel shifting) Dept. of ECE, PVPSIT. 32

35 VHDL code: library IEEE; use IEEE.std_logic_64.all; entity shift94 is port ( clk : in STD_LOGIC;--Clock signal dsr,dsl : in STD_LOGIC;--serial input for right shift and left shift --operation clr_l : in STD_LOGIC;--active low clear input S:in STD_LOGIC_VECTOR( downto --mode control bits d: in STD_LOGIC_VECTOR (3 downto --four parallel input bits q: inout STD_LOGIC_VECTOR (3 downto ) --4-bit output end shift94; architecture shift94 of shift94 is process(clk,s,clr_l) if clr_l='' then q<=(others=>'' elsif clr_l='' then if(clk'event and clk='') then case s is when"" =>q<=q;--no change when""=>q<=q(2 downto ) & dsr;--shift right(dsr to q()) when"" =>q<=dsl & q(3 downto --shift left(dsl to q(3)) when"" =>q<=d(3) & d(2) & d() & d(--parallel operation --d(3) to q(3),d(2) to q(2),d() to q(),d() to q() when others=>null; end case; end if; end if; end process; end shift94; Dept. of ECE, PVPSIT. 33

36 WAVEFORMS: Dept. of ECE, PVPSIT. 34

37 7.3x8 DECODER AIM: Write a VHDL code for IC7438-3X8 Decoder TITLE: IC7438 3x8 Decoder. BLOCK DIAGRAM: TRUTH TABLE: S.No Enable inputs g g2a_l g2b_l Encoded inputs A B C Decoded output X X X X X 2 X X X X 3 X X X X Dept. of ECE, PVPSIT. 35

38 VHDL CODE: library IEEE; use IEEE.std_logic_64.all; entity decoder3x8 is port ( g : in STD_LOGIC;--g, g2a_l, g2b_l cascade i/ps g2a_l : in STD_LOGIC; g2b_l : in STD_LOGIC; a : in STD_LOGIC_VECTOR (2 downto y_l : out STD_LOGIC_VECTOR ( to 7) end decoder3x8; architecture deco38 of decoder3x8 is process (a,g,g2a_l,g2b_l) if (g and not g2a_l and not g2b_l)=''then if a <= ""then y_l<= ""; elsif a <= ""then y_l <= ""; elsif a <= ""then y_l<= ""; elsif a <= ""then y_l <= ""; elsif a <= ""then y_l <= ""; elsif a <= ""then y_l <= ""; elsif a <= ""then y_l <= ""; elsif a <= ""then y_l <= ""; else y_ l<= ""; end if; else y_l <= ""; end if; end process; end deco38; Dept. of ECE, PVPSIT. 36

WAVEFORMS: VIVA QUESTIONS :. Write the behavioral code for the IC 74x38. 2. Write the VHDL code for the IC 74x38 using CASE statement. 3. Write the VHDL code for the IC 74x38 using WITH statement. 4.

39 WAVEFORMS: VIVA QUESTIONS :. Write the behavioral code for the IC 74x Write the VHDL code for the IC 74x38 using CASE statement. 3. Write the VHDL code for the IC 74x38 using WITH statement. 4. Write the VHDL code for the IC 74x38 using WHEN--ELSE statement. 5. Write the structural program for IC 74x What does priority encoder mean? 7. How many decoders are needed to construct 4X6 decoder? 8. What is the difference between decoder and encoder? 9. Write the syntax for exit statement?. Explain briefly about next statement?. How to specify the delay in VHDL program? 2. Write the syntax for component declaration. Dept. of ECE, PVPSIT. 37

40 8.IC 74x85 4-BIT COMPARATOR AIM: Write a VHDL code for IC 74x85 4-bit comparator. BLOCK DIAGRAM: TRUTH TABLE: S.No. Cascade inputs Present input condition A>B A=B A<B AGTBOUT AEQBOUT ALTBOUT AGTBIN= X X X 2 AEQBIN= 5 ALTBIN= X X X VHDL CODE: library IEEE; use IEEE.std_logic_64.all; entity comp is port ( altbin: in STD_LOGIC; aeqbin: in STD_LOGIC; agtbin: in STD_LOGIC; a: in STD_LOGIC_VECTOR (3 downto b: in STD_LOGIC_VECTOR (3 downto agtbout: out STD_LOGIC; aeqbout: out STD_LOGIC; altbout: out STD_LOGIC Dept. of ECE, PVPSIT. 38

end comp; architecture comp of comp is process(a,b,agtbin,aeqbin,altbin) agtbout<=''; --initializes the outputs to aeqbout<=''; altbout<=''; if aeqbin='' then if a=b then aeqbout<='';

41 end comp; architecture comp of comp is process(a,b,agtbin,aeqbin,altbin) agtbout<=''; --initializes the outputs to aeqbout<=''; altbout<=''; if aeqbin='' then if a=b then aeqbout<=''; elsif a>b then agtbout<=''; elsif (a<b) then altbout<=''; end if; elsif (altbin/=agtbin)then agtbout<=agtbin; altbout<=altbin; end if; end process ; end Comp; WAVEFORMS: Dept. of ECE, PVPSIT. 39

42 VIVA QUESTIONS:. Write the dataflow model for the IC 74x Write the VHDL code for the IC 74x85 using CASE statement. 3. Write the VHDL code for the IC 74x85 using WITH statement. 4. Write the VHDL code for the IC 74x85 using WHEN--ELSE statement. 5. Write the structural program for IC 74x How many 4-bit comparators are needed to construct 2-bit comparator? 7. What does a digital comparator mean? 8. Design a 2-bit comparator using gates? 9. Explain the phases of a simulation?. Explain briefly about wait statement? Dept. of ECE, PVPSIT. 4

43 9.8x MULTIPLEXER AIM: Write a VHDL code for IC745 8x multiplexer. TITLE: IC745 8x multiplexer. BLOCK DIAGRAM: TRUTH TABLE: S.No en_l Data select lines Output A B C Y I() 2 I() 3 I(2) 4 I(3) 5 I(4) 6 I(5) 7 I(6) 8 I(7) 9 X X X Dept. of ECE, PVPSIT. 4

44 VHDL CODE: library IEEE; use IEEE.std_logic_64.all; entity mux5 is port ( I :in STD_LOGIC_VECTOR (7 downto --8 i/p lines S :in STD_LOGIC_VECTOR (2 downto --3 data select lines en_l:in STD_LOGIC; --active low enable i/p end mux5; y :out STD_LOGIC architecture mux5 of mux5 is process (I,s,en_l) if en_l='' then case s is when "" => y <= I( when "" => y <= I( when "" => y <= I(2 when "" => y <= I(3 when "" => y <= I(4 when "" => y <= I(5 when "" => y <= I(6 when "" => y <= I(7 when others=>null; end case; end if; end process; end mux5; else y <= ''; --y= when en_l= --output line Dept. of ECE, PVPSIT. 42

WAVEFORMS: VIVA QUESTIONS :. Write the behavioral code for the IC 74x5. 2. Write the VHDL code for the IC 74x5 using IF statement. 3. Write the VHDL code for the IC 74x5 using WITH statement. 4.

45 WAVEFORMS: VIVA QUESTIONS :. Write the behavioral code for the IC 74x5. 2. Write the VHDL code for the IC 74x5 using IF statement. 3. Write the VHDL code for the IC 74x5 using WITH statement. 4. Write the VHDL code for the IC 74x5 using WHEN--ELSE statement. 5. Write the structural program for IC 74x5. 6. What is meant by multiplexer? 7. What does demultiplexer mean? 8. How many 8X multiplexers are needed to construct 6X multiplexer? 9. Compare decoder with demultiplexer?. Design a full adder using 8X multiplexer?. What are the two kinds of subprograms? 2. What are the difference between function and procedure? 3. Explain briefly about subprogram overloading? Dept. of ECE, PVPSIT. 43

46 .6X MULTIPLEXER AIM: Write a VHDL code for IC745 6x multiplexer. TITLE: IC745 6x multiplexer. BLOCK DIAGRAM: TRUTH TABLE: S.No. Data select lines output strobe A B C D Y d () 2 d () 3 d (2) 4 d (3) 5 d (4) 6 d (5) 7 d (6) 8 d (7) 9 d (8) d (9) d () 2 d () 3 d (2) 4 d (3) 5 d (4) 6 d (5) 7 X X X X Dept. of ECE, PVPSIT. 44

47 VHDL CODE: library IEEE; use IEEE.std_logic_64.all; entity mux6 is port( end mux6; strobe : in STD_LOGIC; --active low enable i/p D : in STD_LOGIC_VECTOR(5 downto --6 i/p lines Sel : in STD_LOGIC_VECTOR(3 downto --4 data select lines Y : out STD_LOGIC --output line architecture mux6 of mux6 is signal Y_L:std_logic; with Sel select Y_L <= D() when "", D() when "", D(2) when "", D(3) when "", D(4) when "", D(5) when "", D(6) when "", D(7) when "", D(8) when "", D(9) when "", D() when "", D() when "", D(2) when "", D(3) when "", D(4) when "", D(5) when "", unaffected when others; Y<= not Y_L when (strobe='') else ''; end mux6; Dept. of ECE, PVPSIT. 45

48 WAVEFORMS: Dept. of ECE, PVPSIT. 46

49 VIVA QUESTIONS:. Write the behavioral code for the IC 74x5. 2. Write the VHDL code for the IC 74x5 using IF statement. 3. Write the VHDL code for the IC 74x5 using CASE statement. 4. Write the VHDL code for the IC 74x5 using WHEN--ELSE statement. 5. Write the structural program for IC 74x5. 6. Implement 6X multiplexer using structural model? 7. Write the applications of multiplexer and demultiplexer? 8. Design 32X multiplexer using 6X multiplexer? 9. Explain briefly about operator overloading?. Explain the execution steps of subprogram?. Write the syntax of package declaration? 2. Write the syntax of package body? Dept. of ECE, PVPSIT. 47

50 .IC 74X89 READ AND WRITE OPERATIONS OF RAM AIM: To write the VHDL code for IC 74X89 read and write operations of RAM. BLOCK DIAGRAM: TRUTH TABLE: en_l rw operation Write X Read the complemented data Inhibit VHDL code: library IEEE; use IEEE.std_logic_64.all; entity ram is port ( rw : in STD_LOGIC;--read or write enable pin en_l: in STD_LOGIC; --active low enable pin datain: in STD_LOGIC_VECTOR (3 downto --4-bit input data line addr: in STD_LOGIC_VECTOR (3 downto --4-bit address line dataout: out STD_LOGIC_VECTOR (3 downto ) --4-bit input data line end ram; Dept. of ECE, PVPSIT. 48

51 architecture ram of ram is subtype wtype is STD_LOGIC_VECTOR (3 downto type mem_type is array (5 downto ) of wtype; signal memory:mem_type; ;--creates 6 memory locations.each location can store --4-bits function conv_integer(x:std_logic_vector) return integer is --function to convert variable result:integer; --binary to integer result:=; for i in x'range loop if x(i)= then result:= result+2**i; else null; end if; end loop; return result; end conv_integer; process(en_l,rw,addr) if(en_l='') then if (rw ='') then --performs write operation memory(conv_integer(addr))<= datain;--stores the data in the dataout<="zzzz"; -- corresponding memory elsif (rw ='') then -- the output performs read operation dataout<=not memory(conv_integer(addr)--places the data on end if; -- the given address line else dataout<=(others=>'z' --output is in inhibit state when en_l= (i.e.hi- -- impedence) end if; end process; end ram; Dept. of ECE, PVPSIT. 49

52 WAVEFORMS: Dept. of ECE, PVPSIT. 5

53 VIVA QUESTIONS:. Write the behavioral code for IC 74x89 without declaring the function. 2. Explain about different types of RAMs? 3. How to specify the memory size? 4. Explain read and write operations? 5. What are the differences between RAM and RAM? 6. Explain the steps of a compilation process of a VHDL program? 7. Explain the types of design units? 8. Why configurations are needed? 9. What is binding?. What is subprogram in vhdl Dept. of ECE, PVPSIT. 5

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