DEVELOPING A SIMPLE CUSTOM PCORE THAT READS AND

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1 DEVELOPING A SIMPLE CUSTOM PCORE THAT READS AND WRITES TO DDR AND USE ITS SLAVE REGISTERS TO COMMUNICATE WITH MICROBLAZE YUKA KYUSHIMA SOLANO University of Toronto April 10, 2014 This document has a practical example of how build a custom pcore that reads and writes to DDR. First of all, I recommend you to read and try to create a simple IPCore following the "Creating AXI-connected User-Designed Peripheral Cores" from the labs before starting this tutorial. It contains more information about what is a pcore and how it is structure. CREATION THROUGH THE CUSTOM PERIPHERAL WIZARD First, load a project that has the DDR pcore or create a new XPS project and add it. 1. After loading the project, start the wizard through the menu: Hardware->Create/Import Peripheral Wizard. 2. Select "create templates for a new peripheral". 3. Select "to the local project directory". It will put the newly created pcore in the the pcore subdirectory of the project directory. 4. Name the peripheral "read_write_ddr" 5. Select "AXI4: Burst Capable". 6. Select "User logic master support", "Software reset" and "User logic software register". 7. Number of software accessible registers: Let the default configuration for the next screens.

2 9.Next, the pcore template will be created and you will be returned to the main screen. Add the newly created IP into your design. Select and add it to your design from the IP Catalog with the default options and remember to assign it a base address and range. SOFTWARE APPLICATION With the new pcore created and added we can Generate Bitstream and Export it to SDK. We will first use the software application to read or write to DDR. In other words, we will set the address, the number of bytes to transfer and the command to request read or write using the master register of our pcore directly in the C code. For the next session we will set these parameters in the user_logic.vhd. 1. After export to SDK, create a new Xilinx C Project: File->New->Xilinx C Project. 2. Select Empty Application and name it "rw_ddr". 3. Create a C file and copy the code below and add it to the workspace/rw_ddr/src/ that you have just created. 4. Refresh it (F5) and rebuild your project. 5. Connect the Serial with the terminal and Program to the FPGA. If you have trouble to download the program to the FPGA try change mcb_ddr2_s0_axi_baseaddr to microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl in the Section to Memory Region Mapping in the lscript.ld file. 6. The output on the terminal should be: Before read or write: AAAABBBB CCCCDDDD After read command: AAAABBBB CCCCDDDD After write command: AAAABBBB AAAABBBB C code to request read and write to DDR #include <stdlib.h> #include <stdio.h> #include "xparameters.h" #define printf xil_printf #define DDR1 0xA //define a base address of your DDR #define DDR2 0xA //define another base address of your DDR #define OFFSET 0x100 //offset for the master registers #define PCORE_BASEADDR 0x77A00000 //change to your pcore base address User program

3 int main() { //base address that we will read from volatile unsigned int *ddr1_addr = (volatile unsigned int *) DDR1; //base address the we will write to volatile unsigned int *ddr2_addr = (volatile unsigned int *) DDR2; //base address of our pcore (slave registers) volatile unsigned int *pcore_addr = (volatile unsigned int *) PCORE_BASEADDR; //base address of our pcore (master registers) volatile unsigned char *pcore_mst_addr = (volatile unsigned char *) (PCORE_BASEADDR + OFFSET); ddr1_addr[0] = 0xAAAABBBB; //write a random value in the DDR1 base address //this value will copy to DDR2 ddr2_addr[0] = 0xCCCCDDDD; //write a random value in the DDR2 base address //this value will be overwrited printf("before read or write: %8x %8x \n\r", ddr1_addr[0], ddr2_addr[0]); Read command Control Register (C_BASEADDR + OFFSET + 0x0): -- bit 0 - Rd (Read Request Control) -- bit 1 - Wr (Write Request Control) -- bit 2 - BL (Bus Lock Control) -- bit 3 - Brst (Burst Assertion Control) pcore_mst_addr[0] = 0x01; -- Addrress Register (C_BASEADDR + OFFSET + 0x4): -- bit Target Address (This 32-bit value is used to populate the -- IP2Bus_Mst_Addr(0:31) address bus during a Read or Write -- user logic master operation) //Address to read from: 0xA pcore_mst_addr[4] = 0x00; pcore_mst_addr[5] = 0x00; pcore_mst_addr[6] = 0x00; pcore_mst_addr[7] = 0xA0; -- Byte Enable Register (C_BASEADDR + OFFSET + 0x8): -- bit Master BE (This 16-bit value is used to populate the -- IP2Bus_Mst_BE byte enable bus during a Read or Write user -- logic master operation for single data beat transfer) pcore_mst_addr[8] = 0xFF; pcore_mst_addr[9] = 0xFF; -- Length Register (C_BASEADDR + OFFSET + 0xC): -- bit Reserved -- bit Transfer Length (This 12-bit value is used to populate the -- IP2Bus_Mst_Length(0:11) transfer length bus which specifies -- the number of bytes (1 to 4096) to transfer during user logic -- master Read or Write fixed length burst operations) //We will transfer only 4 bytes pcore_mst_addr[12] = 0x04; pcore_mst_addr[13] = 0x00; pcore_mst_addr[14] = 0x00; -- Go Register (C_BASEADDR + OFFSET + 0xF): -- bit Go Port (Write to this byte address initiates the user -- logic master transfer, data key value of 0x0A must be used) -- //Go command pcore_mst_addr[15] = 0x0A; printf("after read command: %8x %8x\n\r", ddr1_addr[0], ddr2_addr[0]); Write command

4 pcore_mst_addr[0] = 0x02; //Set the address to write to: 0xA pcore_mst_addr[4] = 0x00; pcore_mst_addr[5] = 0x00; pcore_mst_addr[6] = 0x10; pcore_mst_addr[7] = 0xA0; //Go command pcore_mst_addr[15] = 0x0A; printf("after write command: %8x %8x\n\r", ddr1_addr[0], ddr2_addr[0]); } return 0; To transfer more than 4 bytes, enable the burst bit and put the number of bytes we want to transfer in the Length Register. Try to change other parameters to see what happens. CHANGING THE USER_LOGIC.VHD In this section you will change your user_logic generated when you created your pcore. You can find the user_logic.vhd in the folder \pcores\read_write_ddr_v1_00_a\hdl\vhdl. It is in this file that you will put your own VHDL processes and customize your pcore. For now, only do the following changes: --ADDED after line: --USER signal declarations added here, as needed for user logic Signals for read and write to DDR Explanation of the added signals rd_addr address of read from DDR -- wr_addr address of write to DDR -- rd_en read from DDR is enabled signal rd_addr, wr_addr : std_logic_vector(c_mst_awidth-1 downto 0); signal rd_en : std_logic; type SEARCH_RW_SM_TYPE is (SEARCH_RW_IDLE, SEARCH_READ_INIT, SEARCH_READ_GO, SEARCH_WRITE_INIT, SEARCH_WRITE_GO); signal search_rw_sm_state : SEARCH_RW_SM_TYPE; --END_ADDED --EDITED -- rip control bits from master model registers --mst_cntl_rd_req <= mst_reg(0)(0);

5 --mst_cntl_wr_req <= mst_reg(0)(1); mst_cntl_bus_lock <= '0'; --mst_reg(0)(2); mst_cntl_burst <= '1'; --mst_reg(0)(3); --mst_ip2bus_addr <= mst_reg(7) & mst_reg(6) & mst_reg(5) & mst_reg(4); mst_ip2bus_be <= x"ffff"; --mst_reg(9) & mst_reg(8); mst_xfer_reg_len <= x"00040"; --mst_reg(14)(3 downto 0) & mst_reg(13) & mst_reg(12); mst_xfer_length <= mst_xfer_reg_len(c_length_width-1 downto 0 ); --END_EDITED --EDITED if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then if ( Bus2IP_Resetn = '0' or mst_cmd_sm_clr_go = '1' ) then mst_go <= '0'; elsif ( mst_cmd_sm_busy = '0' and mst_cntl_rd_req = '1') then --mst_byte_we(go_byte_lane) = '1' and --Bus2IP_Data((GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)* (GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8)= GO_DATA_KEY ) then mst_go <= '1'; elsif ( mst_cmd_sm_busy = '0' and mst_cntl_wr_req = '1') then mst_go <= '1'; null; --END_EDITED downto --ADDED after line: IP2Bus_Error <= '0'; --Process to read from the bus and store in the fifo --and read from the fifo and write to the bus --slv_reg0 is rd_addr and slv_reg1 is wr_addr SEARCH_SM_RW_PROC: process(bus2ip_clk) is constant IMAGE_WIDTH : integer := 640; constant IMAGE_HEIGHT : integer := 480; constant PACKET_SIZE : integer := 64; //it will transfer 64 bytes each time begin if Rising_Edge(Bus2IP_Clk) then --Initial values if ( Bus2IP_Resetn = '0' ) then search_rw_sm_state <= SEARCH_RW_IDLE; mst_cntl_wr_req <= '0'; mst_cntl_rd_req <= '0'; rd_en <= '0'; rd_addr <= slv_reg0; wr_addr <= slv_reg1;

6 case search_rw_sm_state is when SEARCH_RW_IDLE => Go to read states if (rd_en = '0') then if (f_full = '0') then search_rw_sm_state <= SEARCH_READ_INIT; mst_cntl_rd_req <= '1'; rd_en <= '1'; Go to write states search_rw_sm_state <= SEARCH_WRITE_INIT; mst_cntl_wr_req <= '1'; rd_en <= '0'; when SEARCH_READ_INIT => if(bus2ip_mst_cmdack = '1') then search_rw_sm_state <= SEARCH_READ_GO; mst_cntl_rd_req <= '0'; when SEARCH_READ_GO => if(bus2ip_mst_cmplt = '1') then search_rw_sm_state <= SEARCH_RW_IDLE; if (rd_addr = slv_reg0 + (IMAGE_WIDTH*IMAGE_HEIGHT*2 - PACKET_SIZE)) then rd_addr <= slv_reg0; rd_addr <= rd_addr + PACKET_SIZE; when SEARCH_WRITE_INIT => if(bus2ip_mst_cmdack = '1') then search_rw_sm_state <= SEARCH_WRITE_GO; mst_cntl_wr_req <= '0'; when SEARCH_WRITE_GO =>

7 if(bus2ip_mst_cmplt = '1') then search_rw_sm_state <= SEARCH_RW_IDLE; if (wr_addr = slv_reg1 + (IMAGE_WIDTH*IMAGE_HEIGHT*2 - PACKET_SIZE)) then wr_addr <= slv_reg1; wr_addr <= wr_addr + PACKET_SIZE; when others => search_rw_sm_state <= SEARCH_RW_IDLE; end case; end process SEARCH_SM_RW_PROC; --use the read address when read is enabled, otherwise use write address mst_ip2bus_addr <= rd_addr when rd_en = '1' wr_addr; --END_ADDED This code basically read 64 bytes each time from DDR write to it 64 bytes each time. The base address for read is saved at slv_reg0 and the base address for write is saved at slv_reg1. We can set these address in the software, which make easier in case you want to change them. The number of bytes that is actually transfer is 680*480*2 (, you can change it, only make sure that it is multiple of 64). Actually, when you read from DDR the data is stored at the FIFO and when you write to DDR the data is read from FIFO and put on the Bus to be transferred to DDR. After make all this changes, you can save it and Generate Netlist, Bitstream and Export to SDK. You can create a new workspace to not overwrite your software application. Then, create a new Xilinx C Project as above, copy the following C code in your src folder, connect the Serial and Program to FPGA. C code to request read and write to DDR #include <stdlib.h> #include <stdio.h> #include "xparameters.h" #define printf xil_printf #define DDR1 0xA //define a base address of your DDR #define DDR2 0xA //define another base address of your DDR #define OFFSET 0x100 //offset for the master registers #define PCORE_BASEADDR 0x77A00000 //change to your pcore base address User program int main() {

8 //base address that we will read from volatile unsigned int *ddr1_addr = (volatile unsigned int *) DDR1; //base address the we will write to volatile unsigned int *ddr2_addr = (volatile unsigned int *) DDR2; //base address of our pcore (slave registers) volatile unsigned int *pcore_addr = (volatile unsigned int *) PCORE_BASEADDR; //base address of our pcore (master registers) volatile unsigned char *pcore_mst_addr = (volatile unsigned char *) (PCORE_BASEADDR + OFFSET); ddr1_addr[0] = 0xAAAABBBB; ddr2_addr[0] = 0xCCCCDDDD; //write a random value in the DDR1 base address //this value will copy to DDR2 //write a random value in the DDR2 base address //this value will be overwrited //write to slave registers pcore_addr[0] = DDR1; //address to read pcore_addr[1] = DDR2; //address to write int i = 0; while(1){ //for(i = 0; i < 640*480*2, i++){ printf("%8x %8x\n\r", ddr1_addr[i], ddr2_addr[i]); //} } } return 0; If you want to write any value to the slave registers in your pcore and read this value in the software application you should write the code in the SLAVE_REG_WRITE_PROC in the user_logic. An example is given below. SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin ( ) when others => --null; //write to slave register 2 slv_reg2 <= x"eeeeffff"; end case; end process SLAVE_REG_WRITE_PROC; Then to read this value in the software application only add the line below. //read from slave register 2 printf("slv_reg2: %8x", pcore_addr[2]); Now you already know how to create a simple pcore that reads and writes to the DDR and how to use its slave registers to communicate with MicroBlaze. I hope this tutorial has helped. For more information or bug reports contact me at yuka.kyushimasolano@mail.utoronto.edu.