POWERLINK Slave Xilinx Getting Started User's Manual

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POWERLINK Slave Xilinx Getting Started Version 0.01 (April 2012) Model No: PLALTGETST-ENG We reserve the right to change the content of this manual without prior notice.

1 POWERLINK Slave Xilinx Getting Started Version 0.01 (April 2012) Model No: PLALTGETST-ENG We reserve the right to change the content of this manual without prior notice. The information contained herein is believed to be accurate as of the date of publication, however, B&R makes no warranty, expressed or implied, with regards to the products or the documentation contained within this document. B&R shall not be liable in the event if incidental or consequential damages in connection with or arising from the furnishing, performance or use of these products. The software names, hardware names and trademarks used in this document are registered by the respective companies. Copyright B&R Subject to change without notice 1/23

2 I History Vers. Date Comment Edited by 0.1 Apr 19, 2012 Creation of document mairt Table 1: History 2/23

3 II Table of contents 1 Reference Design Software Tools & Licensing Xilinx Tools B&R Tools Other Tools POWERLINK slave hardware setup Set up the Reference Board Hardware Setup of the LX16 Powerlink Evaluation Board (s6plkeb) Hardware Setup of the LX150T Industrial Ethernet Kit (IEK) Hardware Setup of the LX9 Reference Board POWERLINK slave FPGA configuration POWERLINK slave software compilation Software import for the pcp_directio example Software import for the dual processor example (pcp_pdi, ap_pdi and the libcnapi) Download the FPGA configuration and the MicroBlaze software POWERLINK Master Startup X20 POWERLINK I/O Node Startup (optional) Definitions and Abbreviations Other literature /23

4 Reference Design 1 Reference Design The POWERLINK Slave Design - Xilinx Version - uses the LX16 Powerlink Evaluation Board (s6plkeb) as a hardware reference and evaluation environment (refer to Figure 2). Example designs are also available for the Avnet Spartan-6 lx150t - Industrial Ethernet Kit (IEK) and the Avnet Spartan-6 lx9 MicroBoard 2 Software Tools & Licensing Figure 1: Software Tools and Licensing for POWERLINK Slave Development The above seen tools are necessary for developing an FPGA based POWERLINK Slave. For a quick test of the reference design on the s6plkeb board, a 30 day evaluation license can be acquired from Xilinx. 2.1 Xilinx Tools The following tools are necessary for using this manual and developing on the Xilinx FPGA based slave: Xilinx ISE Embedded Edition which is called ISE Design Suite 13.2 Full Product Installation or ISE Design Suite 13.2 Embedded Edition and can be downloaded from: The license can be acquired from the Xilinx Licensing Site and is free for an evaluation product. (30 days) For network traffic verification it is useful to install a network analyzer tool which can capture and filter POWERLINK frames on the network. For this, the Open Source tool Wireshark or the proprietary software Omni Peak are well suited. In addition a terminal program like TeraTerm can be used to see prints from the Microblaze processor. (This can also be done by using the included SDK terminal window) 2.2 B&R Tools Automation Studio (Download at: This is the B&R tool for all automation tasks and products. A setup version including a single-user license is bundled in the POWERLINK Slave Development Kit. Automation Studio is used to setup and configure the POWERLINK Master (MN), the POWERLINK network, and the B&R I/Os. 4/23

5 2.3 Other Tools For Network verification purposes it is very useful to install Network-Sniffer tools which can capture and filter Ethernet and in this case also POWERLINK frames. There are two recommended tools: WireShark (Open Source, Download at: Omni Peak (Commercial license required, Download at: In order to see the processor prints it is possible to use an external terminal program for reading the on board UART. An integrated program in the SDK is also available. TeraTerm (Open Source, Download at: TeraTerm is a program to print out text which is transmitted over a serial interface. (USB UART) 3 This chapter guides you through the steps in bringing up your first POWERLINK Slave FPGA design. It refers to the demo examples provided with the POWERLINK Slave Development Kit (CNDK). Mainly there are two different applications available in this kit: 1. The first one is a single processor solution and called DirectIO. 2. The second application is a dual processor design where both processors are interconnected by an interface which is called Process Data Interface (PDI). The processor where the use is able to interact with is called Application Processor (AP) and can access the PDI by using different protocols: a. Internal connection via PLB or AXI bus. (intplb, intaxi) b. Access of the PDI with a parallel interface. (8 or 16bit wide) c. SPI interface A more detailed description of the different POWERLINK designs is available in the API Reference Manual [1] or the POWERLINK IP-Core (Generic documentation) [2]. 3.1 POWERLINK slave hardware setup In order to get an POWERLINK slave up and running one of the reference boards need to be chosen. This chapter explains how these three boards need be configured and connected to the network Set up the Reference Board This chapter guides you through the steps in bringing up and running a POWERLINK slave based on a Xilinx FPGA. Requirements: 1. One of the Spartan -6 Development Boards from Avnet a. Avnet Spartan-6 lx16 - POWERLINK Evaluation Board (s6plkeb) b. Avnet Spartan-6 lx150t - Industrial Ethernet Kit (IEK) c. Avnet Spartan-6 lx9 - MicroBoard 2. Xilinx Platform Cable USB II for JTAG programming 3. Xilinx ISE 13.2 Embedded Edition Software tools Hardware Setup of the LX16 POWERLINK Evaluation Board (s6plkeb) The following jumpers and cables need to be connected according to the following picture and listing. 5/23

1. Connect the Power supply as given in Figure 2. 2. Connect one of the Ethernet jacks to the POWERLINK network. 3. Connect the Xilinx Platform Cable USB II to the JTAG-Programmer port. 4.

6 1. Connect the Power supply as given in Figure Connect one of the Ethernet jacks to the POWERLINK network. 3. Connect the Xilinx Platform Cable USB II to the JTAG-Programmer port. 4. Connect the USB-Uart to your host PC USB port. 5. Set the jumpers J502 and J500 as given in Figure If a PDI interface to the AP processor is used please interconnect a ribbon cable with the other board. 7. Finally set the Node Switches to your desired node number. Figure 2 The Powerlink Evaluation Board (s6plkeb) Hardware Setup of the LX150T Industrial Ethernet Kit (IEK) The jumpers need to be set according to the following figures and description below: 1. Install jumper on JP4 pins Install jumper on JP8 pins Connect the JTAG cable (Xilinx Platform Cable USB II) to J9 and to the USB port of your PC. 4. Connect the USB cable to JR1 and to the USB port of your PC. 5. Connect the power supply to J Connect the ISMNET module to FMC slot JX1. 6/23

Figure 3 The LX150T development board (IEK) On the ISMNET FMC module set the jumpers as following: 1. Install jumper on JP1 pins 2-3. 2. Install jumper on JP2 pins 1-2. 3. Install jumper on JP5 & JP10 pins 7-8.

7 Figure 3 The LX150T development board (IEK) On the ISMNET FMC module set the jumpers as following: 1. Install jumper on JP1 pins Install jumper on JP2 pins Install jumper on JP5 & JP10 pins Install jumper on JP4 & JP9. 5. Slide the SW11 Power switch on the S6LX150T board to the ON position. 6. Finally connect one of the two Ethernet ports with your host PC. Figure 4 ISMNET FMC module 7/23

3.1.4 Hardware Setup of the LX9 Reference Board When using this board no additional jumper settings are needed. The connection to the PC is done as listed below and shown in the following figure: 1.

8 3.1.4 Hardware Setup of the LX9 Reference Board When using this board no additional jumper settings are needed. The connection to the PC is done as listed below and shown in the following figure: 1. Connect the JTAG cable (Xilinx Platform Cable USB II) to J6 and to the USB port of your PC. Note: Instead, also the integrated USB JTAG can be used by directly plugging the board into the USB port of your PC. The Digilent USB drivers are included in the Xilinx IDE of version 13.2 or higher. 2. Connect the USB cable to J3 and to the USB port of your PC. 3. Connect the Ethernet jack in J1 to the Ethernet port of your PC. Figure 5 The lx9 Microboard 8/23

9 3.2 POWERLINK slave FPGA configuration After the hardware is set up, the FPGA bitsteam needs to be created and downloaded to the target. The demo software for the POWERLINK evaluation boards is located in the fpga/xilinx directory of your CNDK release. This directory consists of the hardware configuration for the three supported boards and the different supported applications. In order to compile the configuration the following steps need to be carried out: 1. Open Xilinx Platform Studio (Start -> Xilinx ISE Design Suite > EDK ->Xilinx Platform Studio ) 2. Set the Global Repository Search Path by clicking on Edit -> Preferences in XPS. 3. In the following window select the Application category and insert the path to the xilinx/ip-core folder to the Repository Search Path. Figure 6 Set the Global Repository Search Path 4. Open <install>\br_powerlink- SLAVE_XILINX_VX.X.X\02_Reference_Sources\fpga\xilinx\Avnet_<XX>\<design_name>\syste m.xmp according to your hardware platform. 5. Generate Bit Stream (Hardware -> Generate Bit Stream) like it is shown in the following figure. NOTE: The compilation takes several minutes depending on the complexity of the selected design. 9/23

$Tick on Include Bit Stream & BMM File and click Export Only Figure 8 Export to SDK with bitstream and BMM file This creates the FPGA configuration bitstream in the SDK\SDK_Export folder of your$ project. The downloading of the bitstream and the MicroBlaze software is covered in chapter 3.

project. The downloading of the bitstream and the MicroBlaze software is covered in chapter 3.

10 Figure 7 Generate Bitstream 6. After the compilation is done you can export the hardware design to the Xilinx SDK (Project -> Export Hardware Design to SDK) 7. Tick on Include Bit Stream & BMM File and click Export Only Figure 8 Export to SDK with bitstream and BMM file This creates the FPGA configuration bitstream in the SDK\SDK_Export folder of your project. The downloading of the bitstream and the MicroBlaze software is covered in chapter 3.5. The download of the software will be done via the Xilinx SDK, therefore the XPS can be closed. 3.3 POWERLINK slave software compilation After the FPGA configuration is successfully exported, it is time to create the software example which will run on the MicroBlaze processor. 1. Open the Xilinx Software Development Kit (SDK): (Start -> Xilinx ISE Design Suite > EDK -> Xilinx Software Development Kit) 2. Switch Work Directory (File -> Switch Workspace -> Other) 3. Choose a new workspace in the root directory of your CNDK. (e.g: <install>\br_powerlink- SLAVE_XILINX_VX.X.X\02_Reference_Sources\) 10/23

$CNDK installation which is located in the fpga\xilinx\ip-core folder. (e.g. <install>\br_powerlink-slave_xilinx_vx.$

11 Figure 9 Switch the workspace in the Xilinx SDK to the CNDK root folder 4. Add the SDK repository search path. By clicking on Xilinx Tools -> Repositories This path always needs to be set to the IP-Cores directory in your CNDK installation which is located in the fpga\xilinx\ip-core folder. (e.g. <install>\br_powerlink-slave_xilinx_vx.x.x\02_reference_sources\fpga\xilinx\ip- Core) Figure 10 Add the path to the POWERLINK IP-Core repository 11/23

Create a new hardware platform by clicking on File -> New -> Xilinx Hardware Platform Specification Figure 11 Open the new hardware platform specification window 2.

12 3.3.1 Software import for the pcp_directio example This section deals with the compilation of the single processor (pcp_directio) software. Therefore only one program needs to be compiled and downloaded to the processor. This can be achieved as following: 1. Create a new hardware platform by clicking on File -> New -> Xilinx Hardware Platform Specification Figure 11 Open the new hardware platform specification window 2. Enter a name for the new hardware project (e.g. hw_platform_lx150t_directio-plb) and select the target specification file. This specification is an xml file system.xml which can be found in the path where the hardware got exported (e.g. <install>\br_powerlink- SLAVE_XILINX_VX.X.X\02_Reference_Sources\fpga\xilinx\Avnet_<XX>\pcp_DirectIO- [plb,axi]\sdk\sdk_export\hw). Then click the Finish button Figure 12 Create a new hardware platform 3. In addition also a new board support package is needed which will be generated by using the following dialog. There you simply need to enter the new project name (e.g. standalone_bsp_lx9_directio-plb) and hit Finish. 12/23

13 Figure 13 Create a new board support package 4. In the following Board Support Package Settings window select the drivers tab and choose the right driver for the POWERLINK IP-Core. (e.g: plb_powerlink for plb bus or axi_powerlink for AXI bus) Figure 14 Select the driver fort the POWERLINK IP-Core 5. In the standalone tab it is also possible to change the stdin/stdout peripheral. This option enables to redirect the prints of the processor to the desired output device. 13/23

This can be done by clicking on: Import -> C/C++ -> Existing Code as Makefile Project Figure 16 Import pcp_directio C-Project 7.

14 Note: If you are using the MicroBlaze debug module for stdin/stdout the prints get very slow and can therefore decrease the system speed. Figure 15 Redirect stdout/stdin of the MicroBlaze processor 6. Now the Software for the pcp_directio example needs to be imported to the SDK. This can be done by clicking on: Import -> C/C++ -> Existing Code as Makefile Project Figure 16 Import pcp_directio C-Project 7. In the following import dialog give the project a name and select the pcp_directio as existing code location. (e.g: <install>\br_powerlink- SLAVE_XILINX_VX.X.X\02_Reference_Sources\powerlink\pcp_DirectIO) 14/23

15 In addition you need to select C as programming language and the Xilinx MicroBlaze GNU Toolchain as the used toolchain. Figure 17 Software project import window Note: After the software import is finished the program will automatically build itself and will throw a lot of compile errors. In order to fix this the following step needs to be executed! 8. The pcp_directio program consists of a file makefile.settings. Inside this file there are several options to configure the build of the software project. The options BSP_PATH and HW_PLATFORM_PATH need to be adjusted in order fix the compile issues. In addition the correct bus system needs to be set inside this file. (plb or axi bus) 9. In addition you need to select the previously created board support package as the referenced bsp by right clicking on the pcp_directio project and selecting Change Referenced BSP. (see Figure 18) 10. After this it is possible to download the FPGA configuration with the already compiled Micro- Blaze program. This is explained in detail in chapter /23

16 Figure 18 Change the Referenced BSP Software import for the dual processor example (pcp_pdi, ap_pdi and the libcnapi) This section deals with the compilation of the dual processor (pcp_pdi and ap_pdi) software. Therefore this example needs the software for the POWERLINK controlled processor (PCP), the software for the Application processor (AP) and the library for the AP (libcnapi). Note: This chapter just contains of additional information to chapter and therefore users without SDK knowledge should read through this chapter first. 1. Open the Xilinx Software Development Kit (SDK) 2. Create a new hardware platform for your selected dual processor design. (e.g. hw_platform_lx150t_intaxi-axi) 3. Create a board support package for both processors (PCP and AP). (e.g: standalone_bsp_lx150t_intaxi-pcp-axi, standalone_bsp_lx150t_intaxi-ap-axi) 4. Import the software for the PCP processor by using Import -> C/C++ -> Existing Code as Makefile Project. Select the the program pcp_pdi as the existing code location. (e.g: <install>\br_powerlink-slave_xilinx_vx.x.x\02_reference_sources\powerlink\pcp_pdi) 5. Change the Referenced BSP for pcp_pdi to standalone_bsp_lx150t_intaxi-pcp-axi. 6. Adjust the makefile.settings file inside the pcp_pdi project. 7. Import the library libcnapi into the SDK by using the Existing Code as Makefile method. 8. Adjust the makefile.settings file inside the libcnapi project. 9. Also import the ap_pdi program by using the same method as given in point In addition also adjust the makefile.settings file in the ap_pdi project. 11. Change the Referenced BSP for ap_pdi to standalone_bsp_lx150t_intaxi-ap-axi. 12. Finally it is possible to compile all three projects by firstly compiling the pcp_pdi then the libcnapi and finally the ap_pdi program. Note: If you see this compile error: error: #error "cnapicfg.h has not been generated correctly! Please clean and rebuild the pcp_pdi software. Note: It is very important to compile the pcp_pdi first in order to configure the libcnapi with the right parameters. 16/23

3.4 Know Issues 3.4.1 Dual Processor Reset Behaviour In case of a dual processor design the SDK always resets the whole system instead

This behavior is indicated by the following window: Figure 19 Reset status of the dual processor design This problem can be solved by

17 3.4 Know Issues Dual Processor Reset Behaviour In case of a dual processor design the SDK always resets the whole system instead of only the processor. This behavior is indicated by the following window: Figure 19 Reset status of the dual processor design This problem can be solved by changed the reset behavior of your pcp_pdi and ap_pdi program. For this click on Run -> Run configuration and change to the Device Initialization tab. There you can change the reset behavior of your design. Figure 20 Reset behavior of the program 17/23

3.5 Download the FPGA configuration and the MicroBlaze software In order to download the FPGA configuration just click on Xilinx Tools in the SDK and select Program FPGA.

By doing this the board needs to be powered up by turning the run switch on the LX150T (SW11) to on. Finally the generated bitstream is downloaded onto the hardware.

18 3.5 Download the FPGA configuration and the MicroBlaze software In order to download the FPGA configuration just click on Xilinx Tools in the SDK and select Program FPGA. In the following window the path to the bitstream, which needs to be downloaded, is already provided and the Program button can be pushed. By doing this the board needs to be powered up by turning the run switch on the LX150T (SW11) to on. Finally the generated bitstream is downloaded onto the hardware. Figure 21 Program FPGA window Figure 22 Download the FPGA configuration To download the MicroBlaze software just right click on the pcp_directio, pcp_pdi or ap_pdi project and select Run As -> Launch on Hardware. 18/23

19 Figure 23 Download the MicroBlaze software Finally, the software example is booting up and waits for a master node to go operational. One or two USB-Uart or MicroBlaze debug modules are included in every design which allows you to see the debug output of the software on each processor. Therefore, the USB cable or JTAG programming cable needs to be connected. The debug output via the serial console can be read directly in the Xilinx SDK or by using an external program like tera term. Therefore, a terminal log window is connected to the according serial port. In this window, click on the Settings icon and choose Connection type: Serial and the according COM port of the USB serial cable. The other settings are: Baud rate: 9600 Data Bits: 8 Stop Bits: 1 Parity: none Flow control: none 19/23

20 Figure 24 SDK terminal window Note: Debug outputs via the MicroBlaze debug module are very slow and can therefore decrease bootup speed of your CN. Please always prefer to use the USB-Uart if available. (On the dual processor design of the s6plkeb board there is only one UART available which is connected to the AP processor.) 20/23

$The POWERLINK interface is marked with IF3/EPL. A sample project for the B&R PLC is found in the Examples\AS_Projects directory of the DVD.$

21 3.6 POWERLINK Master Startup In order to test run the POWERLINK Slave, connect the POWERLINK cable from your board to the POWERLINK interface of your PLC (e.g: X20CP1485-1, X20CP1486, ). The POWERLINK interface is marked with IF3/EPL. A sample project for the B&R PLC is found in the Examples\AS_Projects directory of the DVD. In order to run the example, carry out the following steps: 1. Start Automation Studio and open the project X20_POWERLINK_Master.zip (found in before mentioned folder). 2. Enter a local path where to import the project to (e.g. <My Documents>\X20_POWERLINK_Master ) Figure 25: Sample project in AutomationStudio 3. Choose Project Rebuild Configuration in order to compile the project. 4. If asked to, download the project to the target. Alternatively, choose Tools Create Compact Flash. 5. Boot the PLC with the new program. As soon as the CPU has started, the POWERLINK network is running. An operational CN is indicated by a bright POWERLINK status led. 21/23

22 Definitions and Abbreviations 3.7 X20 POWERLINK I/O Node Startup (optional) The package also contains a B&R POWERLINK I/O node (X20BC0083) that can be operated with node number 2. 4 Definitions and Abbreviations AP CN CPU DSP EDS FPGA MCU PCP PDI PDO RAM SBT SPI Application Processor POWERLINK Controlled Node Central Processing Unit Digital Signal Processor Embedded Development Suit Field Programmable Gate Array Microcontroller Unit POWERLINK Communication Processor Process Data Interface Process Data Object Random Access Memory Software Build Tools Serial Peripheral Interface 22/23

23 Other literature 5 Other literature [1] Bernecker+Rainer Industrie-Elektronik GmbH: API Reference Manual, 2012, V0.4.5 [2] Bernecker+Rainer Industrie-Elektronik GmbH: POWERLINK IP-Core Generic Documentation, 2012, V1.2 [3] Ethernet POWERLINK Standardization Group: Ethernet POWERLINK Communication Profile Specification DS301 V1.1.0, 2009, [4] Ethernet POWERLINK Standardization Group: Ethernet POWERLINK XML Device Description DS311 V1.0.0, 2009, [5] Bernecker+Rainer Industrie-Elektronik GmbH: POWERLINK Bus Controllers User s Manual, [6] Bernecker+Rainer Industrie-Elektronik GmbH: X20 System Register Description, [7] Bernecker+Rainer Industrie-Elektronik GmbH: X67 System User s Manual, [8] openconfigurator The Open Source POWERLINK Configuration Tool, [9] openpowerlink An Open Source POWERLINK Stack, 23/23

Spartan -6 LX9 MicroBoard Web Connectivity On Ramp Tutorial

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