NIOS Character. Last updated 7/16/18

Size: px
Start display at page:

Download "NIOS Character. Last updated 7/16/18"

Transcription

1 NIOS Character Last updated 7/16/18

2 Character Buffer Block Diagram CLK RST Clock Reset_bar CLK RST PLL 25MHz* CPU Onchip Memory JTAG UART Timer System ID S M S S S S S M S Character Buffer DMA Dual Port FIFO Character System VGA Controller VGA Connector 25MHz** - VGA clk 2 tj

3 Character Buffer Block 80 char x 60 lines ASCII Character 8 x 8 matrix / char Automatically scans through memory 3 tj

4 Dual Clock FIFO Allows different incoming and outgoing data rates 4 tj

5 VGA Controller Block Creates and drives the required VGA signals 5 tj

6 Create a new Quartus project Do not select a Simulation Tool in EDA Tool Settings Open Tools Platform Designer 6 tj

7 Add NIOS Processors and Peripherals Embedded Processors NIOS II Processor NIOS II/f Add On-chip Memory Basic Functions On Chip Memory On Chip Memory (RAM or ROM) RAM Size = 12,000 bytes 7 tj

8 Add JTAG Interface Protocols Serial JTAG Uart Intel FPGA IP Add Timer Processors and Peripherals Peripherals Interval Timer Intel FPGA IP Add System ID Basic Functions Simulation; Debug and Verification Debug and Performance System ID Peripheral Intel FPGA IP 8 tj

9 Connect up basic NIOS system NIOS Inputs 9 tj

10 Connect up basic NIOS system On-chip Memory Connect to data and instruction masters 10 tj

11 Connect up basic NIOS system JTAG, Timer, SysID Connect to data master Assign Priorities 11 tj

12 Connect up basic NIOS system Assign the NIOS II Reset and Exception vectors 12 tj

13 Create Character System Add a PLL Basic Functions Clocks; PLLs and Resets PLL ALTPLL Intel FPGA IP 50MHz input clock no areset or locked c0 25MHz 13 tj

14 Create Character System Connect PLL Connect to data master 14 tj

15 Create Character System Character Buffer University Program Audio and Video Video Character Buffer for VGA Display Connect to data master 15 tj

16 Create Character System Dual Clock FIFO University Program Audio and Video Video Dual Clock FIFO Color Bits 10 Color Planes - 3 Connect to video character buffer streaming source Connect to c0 16 tj

17 Create Character System VGA Controller University Program Audio and Video Video VGA Controller DE10-Lite VGA Connector VGA 640x480 Connect to dual_clock_buffer streaming source Connect to c0 Export and rename 17 tj

18 Create Character System Assign Base Addresses 18 tj

19 Create Character System Check for errors 19 tj

20 Create Character System Save the Platform Designer system Generate the Platform Designer system The first time you generate you must delete the last directory in the path don t use the 20 tj

21 Create Character System Add the.qip file to the project 21 tj

22 Create DE10 Design Instantiate into a VHDL file Open a new VHDL design In Platform Designer: Generate Show Instantiation Template Copy and Paste into the new design where appropriate component nios_character is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n vga_out_clk : out std_logic; -- CLK vga_out_hs : out std_logic; -- HS vga_out_vs : out std_logic; -- VS vga_out_blank : out std_logic; -- BLANK vga_out_sync : out std_logic; -- SYNC vga_out_r : out std_logic_vector(3 downto 0); -- R vga_out_g : out std_logic_vector(3 downto 0); -- G vga_out_b : out std_logic_vector(3 downto 0) -- B ); end component nios_character; u0 : component nios_character port map ( clk_clk => CONNECTED_TO_clk_clk, -- clk.clk reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n vga_out_clk => CONNECTED_TO_vga_out_CLK, -- vga_out.clk vga_out_hs => CONNECTED_TO_vga_out_HS, --.HS vga_out_vs => CONNECTED_TO_vga_out_VS, --.VS vga_out_blank => CONNECTED_TO_vga_out_BLANK, --.BLANK vga_out_sync => CONNECTED_TO_vga_out_SYNC, --.SYNC vga_out_r => CONNECTED_TO_vga_out_R, --.R vga_out_g => CONNECTED_TO_vga_out_G, --.G vga_out_b => CONNECTED_TO_vga_out_B --.B ); 22 tj

23 Create DE10 Design Instantiate into a VHDL file Instantiation template component library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nios_character_de10 is port( CLOCK_50 : in std_logic; VGA_HS: out std_logic; VGA_VS: out std_logic; ); end entity; VGA_R: out std_logic_vector(3 downto 0); VGA_G: out std_logic_vector(3 downto 0); VGA_B: out std_logic_vector(3 downto 0) architecture behavioral of nios_character_de10 is no signals component nios_character is port ( clk_clk : in std_logic := 'X ; -- clk reset_reset_n : in std_logic := 'X ; -- reset_n vga_out_clk : out std_logic; -- CLK vga_out_hs : out std_logic; -- HS vga_out_vs : out std_logic; -- VS vga_out_blank : out std_logic; -- BLANK vga_out_sync : out std_logic; -- SYNC vga_out_r : out std_logic_vector(3 downto 0); -- R vga_out_g : out std_logic_vector(3 downto 0); -- G vga_out_b : out std_logic_vector(3 downto 0) -- B ); end component nios_character; DE10 pin aliases from.qsf file 23 tj

24 Create DE10 Design Instantiate into a VHDL file Instantiation template instance mapped to DE10 qsf pin aliases begin u0 : component nios_character port map ( clk_clk => CLOCK_50, -- clk.clk reset_reset_n => '1, -- reset.reset_n --vga_out_clk => CONNECTED_TO_vga_out_CLK, -- vga_out.clk vga_out_hs => VGA_HS, --.HS vga_out_vs => VGA_VS, --.VS --vga_out_blank => CONNECTED_TO_vga_out_BLANK, --.BLANK --vga_out_sync => CONNECTED_TO_vga_out_SYNC, --.SYNC vga_out_r => VGA_R, --.R vga_out_g => VGA_G, --.G vga_out_b => VGA_B --.B ); end architecture; Note: these 3 signals are not used - comment out or remove 24 tj

25 Create DE10 Design Prepare to synthesize If you did not do these when you created the project be sure to do them now assignments device device and Pin options Single Uncompressed with memory initialization Import the pin aliases (qsf file) Setup the SDF file Be sure to set your top level entity Start Compilation 25 tj

26 Create DE10 Design Complete the HW setup Download the HW project onto the board DO NOT CLOSE either of these windows 26 tj

27 Create Eclipse System Open NIOSII software Tools NIOSII Software Build Tools for Eclipse Create the BSP File New NIOSII Application and BSP from template Blank Template Edit the BSP Right click on the BSP, NIOS II BSP Editor Change the properties for small systems Small C library Reduced device drivers Re-Generate the BSP 27 tj

28 Create Eclipse System In the BSP under drivers/inc Open altera_up_avalon_video_character_buffer_with_dma.h Find the video character buffer structure name Create a pointer of this type // define a pointer of type char buffer type // to use as a reference in the dma functions // alt_up_char_buffer_dev * char_buf_dev; 28 tj

29 Create Eclipse System In the BSP under drivers/inc Open altera_up_avalon_video_character_buffer_with_dma.h Find the function to open the character buffer dma device 29 tj

30 Create Eclipse System In the BSP under drivers/inc Open the device and assign it to the previously defined pointer // open the Character Buffer control port // name reference is in system.h // "/dev/video_character_buffer_with_dma_0_avalon_char_buffer_slave" // char_buf_dev = alt_up_char_buffer_open_dev("/dev/video_character_buffer_with_dma_0"); 30 tj

31 Create Eclipse System In the BSP under drivers/inc Open altera_up_avalon_video_character_buffer_with_dma.h The remainder of the character buffer dma commands are in this file This actually writes to the buffer /** Draw a character at the location specified by <em>(x, y)</em> on the * VGA monitor with white color and transparent background * ch -- the character to draw x-- the \em x coordinate y-- the \em y coordinate * 0 for success, -1 for error (such as out of bounds) **/ int alt_up_char_buffer_draw(alt_up_char_buffer_dev *char_buffer, unsigned char ch, unsigned int x, unsigned int y); tj

32 Create Eclipse System /** Draw a NULL-terminated text string at the location specified by <em>(x, y)</em> * ch -- the character to draw x-- the \em x coordinate y-- the \em y coordinate Strings do not wrap around the display * 0 for success, -1 for error (such as out of bounds) **/ int alt_up_char_buffer_string(alt_up_char_buffer_dev *char_buffer, const char *ptr, unsigned int x, unsigned int y); /** Clears the character buffer's memory * 0 for success **/ int alt_up_char_buffer_clear(alt_up_char_buffer_dev *char_buffer); This actually writes to the buffer 32 tj

33 Create Eclipse System Write a program to print some characters to the screen ///////////////// // Include files ///////////////// #include "altera_up_avalon_video_character_buffer_with_dma.h" #include "system.h" #include <stdio.h> 33 tj

34 Create Eclipse System Write a program to print some characters to the screen int main(void){ // define a pointer of type char buffer type // to use as a reference in the dma functions // alt_up_char_buffer_dev * char_buf_dev; // open the Character Buffer port // name reference is in system.h // "/dev/video_character_buffer_with_dma_0_avalon_char_buffer_slave" // char_buf_dev = alt_up_char_buffer_open_dev("/dev/video_character_buffer_with_dma_0"); // Check for error and output to the console // if ( char_buf_dev == NULL) printf ("Error: could not open character buffer device \n"); else printf ("Opened character buffer device \n"); 34 tj

35 Create Eclipse System Write a program to print some characters to the screen // Print some text to the screen // char text = 'X'; char text_top_row[40] = "Altera DE10_lite\0"; char text_bottom_row[40] = "Character Buffer\0"; /* output text message near the middle of the VGA monitor */ alt_up_char_buffer_clear(char_buf_dev); alt_up_char_buffer_draw(char_buf_dev, text, 0, 0); alt_up_char_buffer_draw(char_buf_dev, text, 0, 59); alt_up_char_buffer_draw(char_buf_dev, text, 79, 0); alt_up_char_buffer_draw(char_buf_dev, text, 79, 59); alt_up_char_buffer_string(char_buf_dev, text_top_row, 20,20); alt_up_char_buffer_string(char_buf_dev, text_bottom_row, 40,40); // end program message printf ("Program complete \n"); } return 0; 35 tj

36 Create Eclipse System Compile the software Select the code file (char.c) Project Build Project Right Click on the project run as Nios II Hardware 36 tj

NIOS II Pixel Display

NIOS II Pixel Display NIOS Pixel Display SDRAM 512Mb Clock Reset_bar CPU Onchip Memory External Memory Controller JTAG UART Pixel DMA Resampler Scaler Dual Port FIFO VGA Controller Timer System ID VGA Connector PLL 2 tj SDRAM

More information

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus Prime 15.1

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus Prime 15.1 Introduction to the Altera Qsys System Integration Tool For Quartus Prime 15.1 1 Introduction This tutorial presents an introduction to Altera s Qsys system integration tool, which is used to design digital

More information

University of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual

University of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual University of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual Lab 1: Using NIOS II processor for code execution on FPGA Objectives: 1. Understand the typical design flow in

More information

Creating projects with Nios II for Altera De2i-150. By Trace Stewart CPE 409

Creating projects with Nios II for Altera De2i-150. By Trace Stewart CPE 409 Creating projects with Nios II for Altera De2i-150 By Trace Stewart CPE 409 CONTENTS Chapter 1 Hardware Design... 1 1.1 Required Features... 1 1.2 Creation of Hardware Design... 1 Chapter 2 Programming

More information

MAX 10 - ADC. Last updated 8/12/18

MAX 10 - ADC. Last updated 8/12/18 MAX 10 - Last updated 8/12/18 A/D Analog to Digital Conversion Most of the real world is analog temperature, pressure, voltage, current, To work with these values in a computer we must convert them into

More information

DKAN0011A Setting Up a Nios II System with SDRAM on the DE2

DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 04 November 2009 Introduction This tutorial details how to set up and instantiate a Nios II system on Terasic Technologies, Inc. s DE2 Altera

More information

Embedded Systems. "System On Programmable Chip" Design Methodology using QuartusII and SOPC Builder tools. René Beuchat LAP - EPFL

Embedded Systems. System On Programmable Chip Design Methodology using QuartusII and SOPC Builder tools. René Beuchat LAP - EPFL Embedded Systems "System On Programmable Chip" Design Methodology using QuartusII and SOPC Builder tools René Beuchat LAP - EPFL rene.beuchat@epfl.ch 3 Tools suite Goals: to be able to design a programmable

More information

Making Qsys Components. 1 Introduction. For Quartus II 13.0

Making Qsys Components. 1 Introduction. For Quartus II 13.0 Making Qsys Components For Quartus II 13.0 1 Introduction The Altera Qsys tool allows a digital system to be designed by interconnecting selected Qsys components, such as processors, memory controllers,

More information

CSEE W4840 Embedded System Design Lab 1

CSEE W4840 Embedded System Design Lab 1 CSEE W4840 Embedded System Design Lab 1 Stephen A. Edwards Due January 31, 2008 Abstract Learn to use the Altera Quartus development envrionment and the DE2 boards by implementing a small hardware design

More information

Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication

Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication Introduction All processors offer some form of instructions to add, subtract, and manipulate data.

More information

University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring Lab 1: Using Nios 2 processor for code execution on FPGA

University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring Lab 1: Using Nios 2 processor for code execution on FPGA University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring 2007 Lab 1: Using Nios 2 processor for code execution on FPGA Objectives: After the completion of this lab: 1. You will understand

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip 1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based

More information

Embedded Systems. "System On Programmable Chip" Design Methodology using QuartusII and SOPC Builder tools. René Beuchat LAP - EPFL

Embedded Systems. System On Programmable Chip Design Methodology using QuartusII and SOPC Builder tools. René Beuchat LAP - EPFL Embedded Systems "System On Programmable Chip" Design Methodology using QuartusII and SOPC Builder tools René Beuchat LAP - EPFL rene.beuchat@epfl.ch 3 Tools suite Goals: to be able to design a programmable

More information

Tutorial of Interfacing with RS232 UART

Tutorial of Interfacing with RS232 UART Tutorial of Interfacing with RS232 UART Kwan Yin Lau (group 3) Feb 7, 2014 Introduction This tutorial will demonstrate how to interface the RS232 UART port on the Altera DE2 board in order to send and

More information

Quartus Counter Example. Last updated 9/6/18

Quartus Counter Example. Last updated 9/6/18 Quartus Counter Example Last updated 9/6/18 Create a logic design from start to a DE10 implementation This example uses best design practices This example is not about creating HDL The HDL code will be

More information

Generic Serial Flash Interface Intel FPGA IP Core User Guide

Generic Serial Flash Interface Intel FPGA IP Core User Guide Generic Serial Flash Interface Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Generic

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems NIOS-II SoPC: PART-II 1 Introduction This lab has been constructed to introduce the development of dedicated

More information

Designing with Nios II Processor for Hardware Engineers

Designing with Nios II Processor for Hardware Engineers Designing with Nios II Processor for Hardware Engineers Course Description This course provides all theoretical and practical know-how to design ALTERA SoC FPGAs based on the Nios II soft processor under

More information

CSEE W4840 Embedded System Design Lab 3

CSEE W4840 Embedded System Design Lab 3 CSEE W4840 Embedded System Design Lab 3 Stephen A. Edwards Due February 24, 2010 Abstract Use Quartus and SOPC builder to create one of two mixed hardware/software designs: an FM sound synthesizer or a

More information

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language) Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable

More information

DE2 Board & Quartus II Software

DE2 Board & Quartus II Software January 23, 2015 Contact and Office Hours Teaching Assistant (TA) Sergio Contreras Office Office Hours Email SEB 3259 Tuesday & Thursday 12:30-2:00 PM Wednesday 1:30-3:30 PM contre47@nevada.unlv.edu Syllabus

More information

CSEE W4840 Embedded System Design Lab 1

CSEE W4840 Embedded System Design Lab 1 CSEE W4840 Embedded System Design Lab 1 Stephen A. Edwards Due February 2, 2009 Abstract Learn to use the Altera Quartus development envrionment and the DE2 boards by implementing a small hardware design

More information

Designing with ALTERA SoC Hardware

Designing with ALTERA SoC Hardware Designing with ALTERA SoC Hardware Course Description This course provides all theoretical and practical know-how to design ALTERA SoC devices under Quartus II software. The course combines 60% theory

More information

CSEE W4840 Embedded System Design Lab 1

CSEE W4840 Embedded System Design Lab 1 CSEE W4840 Embedded System Design Lab 1 Stephen A. Edwards Due February 3, 2011 Abstract Learn to use the Altera Quartus development envrionment and the DE2 boards by implementing a small hardware design

More information

9. Building Memory Subsystems Using SOPC Builder

9. Building Memory Subsystems Using SOPC Builder 9. Building Memory Subsystems Using SOPC Builder QII54006-6.0.0 Introduction Most systems generated with SOPC Builder require memory. For example, embedded processor systems require memory for software

More information

SerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices

SerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices IP Core Design Example User Guide for Intel Arria 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start

More information

Introduction to VHDL Design on Quartus II and DE2 Board

Introduction to VHDL Design on Quartus II and DE2 Board ECP3116 Digital Computer Design Lab Experiment Duration: 3 hours Introduction to VHDL Design on Quartus II and DE2 Board Objective To learn how to create projects using Quartus II, design circuits and

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip NIOS CPU Based Embedded Computer System on Programmable Chip 1 Lab Objectives EE8205: Embedded Computer Systems NIOS-II SoPC: PART-I This lab has been constructed to introduce the development of dedicated

More information

Sign here to give permission for your test to be returned in class, where others might see your score:

Sign here to give permission for your test to be returned in class, where others might see your score: EEL 4712 Midterm 2 Spring 216 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)

More information

Altera s Avalon Communication Fabric

Altera s Avalon Communication Fabric Altera s Avalon Communication Fabric Stephen A. Edwards Columbia University Spring 2012 Altera s Avalon Bus Something like PCI on a chip Described in Altera s Avalon Memory-Mapped Interface Specification

More information

Introduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction

Introduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction Introduction to the Altera SOPC Builder Using Verilog Designs 1 Introduction This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the

More information

Getting Started with the CPU Design

Getting Started with the CPU Design Getting Started with the CPU Design In this tutorial we will create a skeleton of your top-level computer and CPU. You may want to create a new library for these designs, but you may feel free to use your

More information

A. FPGA Basics Manuals

A. FPGA Basics Manuals A. FPGA Basics Manuals In this practical course, Field-Programmable Gate Array (FPGA) is used as the experimental platform, which means to creation of a hardware description for the FPGA and writing software

More information

Using the SDRAM on Altera s DE1 Board with Verilog Designs. 1 Introduction. For Quartus II 13.0

Using the SDRAM on Altera s DE1 Board with Verilog Designs. 1 Introduction. For Quartus II 13.0 Using the SDRAM on Altera s DE1 Board with Verilog Designs For Quartus II 13.0 1 Introduction This tutorial explains how the SDRAM chip on Altera s DE1 Development and Education board can be used with

More information

QUARTUS II Altera Corporation

QUARTUS II Altera Corporation QUARTUS II Quartus II Design Flow Design Entry Timing Constraints Synthesis Placement and Routing Timing, Area, Power Optimization Timing and Power Analyzer Optimized Design 2 Can I still use a Processor?

More information

ECE-6170 Embedded Systems Laboratory Exercise 3

ECE-6170 Embedded Systems Laboratory Exercise 3 ECE-6170 Embedded Systems Laboratory Exercise 3 The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and use the Nios II processor to interface with parallel

More information

CSCE 313: Embedded System Design. Introduction. Instructor: Jason D. Bakos

CSCE 313: Embedded System Design. Introduction. Instructor: Jason D. Bakos CSCE 313: Embedded System Design Introduction Instructor: Jason D. Bakos Introduction to CSCE 313 Teaching assistants (Storey, room 2236): Charles Daniels (cad3@email.sc.edu) Office hours: M 10:40 to 11:30,

More information

4. SOPC Builder Components

4. SOPC Builder Components 4. SOPC Builder Components VGA Core for Altera DE2/DE1 Boards QII544-6.. Introduction 1 Core Overview This chapter describes in detail what an SOPC Builder component is. SOPC Builder components are individual

More information

HyperBus Memory Controller (HBMC) Tutorial

HyperBus Memory Controller (HBMC) Tutorial Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T005C: A Qsys based Nios II Reference design with a simple HyperFlash test device using S/Labs' HBMC IP and S/Labs' Memory Region Mapper IP This

More information

EEC180B DIGITAL SYSTEMS Spring University of California, Davis. Department of Electrical and Computer Engineering

EEC180B DIGITAL SYSTEMS Spring University of California, Davis. Department of Electrical and Computer Engineering University of California, Davis Department of Electrical and Computer Engineering Tutorial: Instantiating and Using a PLL on the DE10 LITE Objective: This tutorial explains how to configure and instantiate

More information

HyperBus Memory Controller (HBMC) Tutorial

HyperBus Memory Controller (HBMC) Tutorial Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T001: A Qsys based Nios II Reference design with HelloWorld test running in HyperRAM device using S/Labs' HBMC IP This tutorial describes a simple

More information

CSCE 313: Embedded Systems. Video Out and Image Transformation. Instructor: Jason D. Bakos

CSCE 313: Embedded Systems. Video Out and Image Transformation. Instructor: Jason D. Bakos CSCE 313: Embedded Systems Video Out and Image Transformation Instructor: Jason D. Bakos Annoucements Demo your Lab 1 to instructor/ta on Monday Save your Lab 1 in a separate directory Ex. cp a ~/lights

More information

SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices

SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Stratix 10 ES Editions Subscribe Send Feedback Latest document

More information

In our case Dr. Johnson is setting the best practices

In our case Dr. Johnson is setting the best practices VHDL Best Practices Best Practices??? Best practices are often defined by company, toolset or device In our case Dr. Johnson is setting the best practices These rules are for Class/Lab purposes. Industry

More information

Design of Embedded Hardware and Firmware

Design of Embedded Hardware and Firmware Design of Embedded Hardware and Firmware Introduction on "System On Programmable Chip" NIOS II Avalon Bus - DMA Andres Upegui Laboratoire de Systèmes Numériques hepia/hes-so Geneva, Switzerland Embedded

More information

Introduction to the Altera SOPC Builder Using Verilog Design

Introduction to the Altera SOPC Builder Using Verilog Design Introduction to the Altera SOPC Builder Using Verilog Design This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the Nios II processor

More information

Introduction to the Qsys System Integration Tool

Introduction to the Qsys System Integration Tool Introduction to the Qsys System Integration Tool Course Description This course will teach you how to quickly build designs for Altera FPGAs using Altera s Qsys system-level integration tool. You will

More information

Digital Systems Design

Digital Systems Design Digital Systems Design Memory Implementation on Altera CYCLONE V Devices Electrical & Computer Engineering Dr. D. J. Jackson Lecture 6-1 Embedded Memory 10 Kb M10K blocks blocks of dedicated memory resources

More information

NIOS II Instantiating the Off-chip Trace Logic

NIOS II Instantiating the Off-chip Trace Logic NIOS II Instantiating the Off-chip Trace Logic TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICD In-Circuit Debugger... Processor Architecture Manuals... NIOS... NIOS II Application

More information

FPGAs in a Nutshell - Introduction to Embedded Systems-

FPGAs in a Nutshell - Introduction to Embedded Systems- FPGAs in a Nutshell - Introduction to Embedded Systems- Dipl.- Ing. Falk Salewski Lehrstuhl Informatik RWTH Aachen salewski@informatik.rwth-aachen.de Winter term 6/7 Contents History FPGA architecture

More information

CSC / EE Digital Systems Design. Summer Sample Project Proposal 01

CSC / EE Digital Systems Design. Summer Sample Project Proposal 01 THE CATHOLIC UNIVERSITY OF AMERICA SCHOOL OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE CSC / EE 519-01 Digital Systems Design Summer 2013 Sample Project Proposal 01 Thursday

More information

Sega Genesis Controller Interfacing

Sega Genesis Controller Interfacing Sega Genesis Controller Interfacing Mason Strong, Stephen Just 2016-04-02 1 Introduction The Sega Genesis was an old 16-bit game console that was released in North America in 1989. [1] This console features

More information

FPGA design with National Instuments

FPGA design with National Instuments FPGA design with National Instuments Rémi DA SILVA Systems Engineer - Embedded and Data Acquisition Systems - MED Region ni.com The NI Approach to Flexible Hardware Processor Real-time OS Application software

More information

Nios II Custom Instruction User Guide Preliminary Information

Nios II Custom Instruction User Guide Preliminary Information Nios II Custom Instruction User Guide Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Copyright 2008 Altera Corporation. All rights reserved. Altera,

More information

System Cache (CMS-T002/CMS-T003) Tutorial

System Cache (CMS-T002/CMS-T003) Tutorial Synaptic Labs' System Cache (CMS-T002/CMS-T003) Tutorial T006A: Arduino Style Nios II/e embedded system: A Qsys Nios II Reference design based on S/Labs' HBMC IP and S/Labs' System Cache for accelerating

More information

Penrose World. Group member. CSEE4840 Embedded System Design 03/26/2014 Project Design. Yuanhui Luo(yl3026) Yao Luo(yl3028) Cong Zhu(cz2311)

Penrose World. Group member. CSEE4840 Embedded System Design 03/26/2014 Project Design. Yuanhui Luo(yl3026) Yao Luo(yl3028) Cong Zhu(cz2311) Penrose World CSEE4840 Embedded System Design 03/26/2014 Project Design Group member Yuanhui Luo(yl3026) Yao Luo(yl3028) Cong Zhu(cz2311) Implement details: Algorithm Induction We consider use Ray- Casting

More information

HyperBus Memory Controller (HBMC) Tutorial

HyperBus Memory Controller (HBMC) Tutorial Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T005B: A Qsys based Nios II Reference design with a simple application running from HyperFlash and HyperRAM device using S/Labs' HBMC IP. The HyperRAM

More information

Objective: Create an interface to the LCD display, internal timer functions, and interface with the SDRAM memory as well as on chip memory.

Objective: Create an interface to the LCD display, internal timer functions, and interface with the SDRAM memory as well as on chip memory. Lab 2 LCD display and external memory interfacing Objective: Create an interface to the LCD display, internal timer functions, and interface with the SDRAM memory as well as on chip memory. Topics Covered:

More information

FPGA briefing Part II FPGA development DMW: FPGA development DMW:

FPGA briefing Part II FPGA development DMW: FPGA development DMW: FPGA briefing Part II FPGA development FPGA development 1 FPGA development FPGA development : Domain level analysis (Level 3). System level design (Level 2). Module level design (Level 1). Academical focus

More information

SISTEMI EMBEDDED. Building a Nios II Computer from scratch. Federico Baronti Last version:

SISTEMI EMBEDDED. Building a Nios II Computer from scratch. Federico Baronti Last version: SISTEMI EMBEDDED Building a Nios II Computer from scratch Federico Baronti Last version: 20160321 1 Introduction Problem: Build a (NIOS II) Computer tailored to application needs Solutions: Use library

More information

VHDL: Modeling RAM and Register Files. Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2

VHDL: Modeling RAM and Register Files. Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2 VHDL: Modeling RAM and Register Files Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2 Memory Synthesis Approaches: Random logic using flip-flops or latches Register files in datapaths RAM standard components

More information

MAX 10. Memory Modules

MAX 10. Memory Modules MAX 10 Memory Modules Three types of on-chip memory FF based memory embedded in the LEs Most efficient for very small memories Compiler driven Embedded SRAM block 8K bits + 1024 parity bits (9216b) MAX

More information

Synaptic Labs' Hyperbus Controller Design Guidelines

Synaptic Labs' Hyperbus Controller Design Guidelines Synaptic Labs' Hyperbus Controller Design Guidelines Table of Contents Introduction...1 1.0 Synaptic Labs' HBMC Controller IP Qsys Component...3 2.0 Typical S/Labs HBMC connection in Qsys...4 3.0 Typical

More information

3-D Accelerator on Chip

3-D Accelerator on Chip 3-D Accelerator on Chip Third Prize 3-D Accelerator on Chip Institution: Participants: Instructor: Donga & Pusan University Young-Hee Won, Jin-Sung Park, Woo-Sung Moon Sam-Hak Jin Design Introduction Recently,

More information

Altera DE2: DM9000A Ethernet Controller Application Notes. By: Tarek Kaddoura Jigar Nahar

Altera DE2: DM9000A Ethernet Controller Application Notes. By: Tarek Kaddoura Jigar Nahar Altera DE2: DM9000A Ethernet Controller Application Notes By: Tarek Kaddoura Jigar Nahar Table of Contents Introduction... 1 Hardware Configuration... 1 SOPC Builder... 1 Top Level Modifications... 1 Software

More information

Xilinx Vivado/SDK Tutorial

Xilinx Vivado/SDK Tutorial Xilinx Vivado/SDK Tutorial (Laboratory Session 1, EDAN15) Flavius.Gruian@cs.lth.se March 21, 2017 This tutorial shows you how to create and run a simple MicroBlaze-based system on a Digilent Nexys-4 prototyping

More information

Tutorial for Altera DE1 and Quartus II

Tutorial for Altera DE1 and Quartus II Tutorial for Altera DE1 and Quartus II Qin-Zhong Ye December, 2013 This tutorial teaches you the basic steps to use Quartus II version 13.0 to program Altera s FPGA, Cyclone II EP2C20 on the Development

More information

Field Programmable Gate Array

Field Programmable Gate Array Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational

More information

VHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents

VHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents VHDL Testbench Tutorial 1 Contents 1 VHDL Testbench 2 Test Bench Syntax 3 Testbench Example: VHDL Code for Up Down Binary Counter 4 VHDL Testbench code for up down binary counter 5 Testbench Waveform for

More information

Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses

Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single

More information

Specifying time in VHDL

Specifying time in VHDL Computer System Structures cz:struktury počítačových systémů Lecturer: Richard Šusta richard@susta.cz, susta@fel.cvut.cz, +420 2 2435 7359 Version: 1.0 ČVUT-FEL in Prague, CR subject A0B35SPS Specifying

More information

Laboratory Exercise 5

Laboratory Exercise 5 Laboratory Exercise 5 Bus Communication The purpose of this exercise is to learn how to communicate using a bus. In the designs generated by using Altera s SOPC Builder, the Nios II processor connects

More information

2.5G Reed-Solomon II MegaCore Function Reference Design

2.5G Reed-Solomon II MegaCore Function Reference Design 2.5G Reed-Solomon II MegaCore Function Reference Design AN-642-1.0 Application Note The Altera 2.5G Reed-Solomon (RS) II MegaCore function reference design demonstrates a basic application of the Reed-Solomon

More information

My First Nios II for Altera DE2-115 Board

My First Nios II for Altera DE2-115 Board My First Nios II for Altera DE2-115 Board Digital Circuit Lab TA: Po-Chen Wu Outline Hardware Design Nios II IDE Build Flow Programming the CFI Flash 2 Hardware Design 3 Introduction This slides provides

More information

Building A Custom System-On-A-Chip

Building A Custom System-On-A-Chip Building A Custom System-On-A-Chip Only a few years ago, we could only dream about building our very own custom microprocessor system on a chip. The manufacturing cost for producing a custom chip is just

More information

Using ModelSim to Simulate Logic Circuits in VHDL Designs. 1 Introduction. For Quartus II 13.0

Using ModelSim to Simulate Logic Circuits in VHDL Designs. 1 Introduction. For Quartus II 13.0 Using ModelSim to Simulate Logic Circuits in VHDL Designs For Quartus II 13.0 1 Introduction This tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We

More information

ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University

ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential

More information

Chapter 2 Getting Hands on Altera Quartus II Software

Chapter 2 Getting Hands on Altera Quartus II Software Chapter 2 Getting Hands on Altera Quartus II Software Contents 2.1 Installation of Software... 20 2.2 Setting Up of License... 21 2.3 Creation of First Embedded System Project... 22 2.4 Project Building

More information

VHDL And Synthesis Review

VHDL And Synthesis Review VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only

More information

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA Triple-Speed Ethernet and On-Board

More information

9. Verification and Board Bring-Up

9. Verification and Board Bring-Up 9. Verification and Board Bring-Up July 2011 ED51010-1.3 ED51010-1.3 Introduction This chapter provides an overview of the tools available in the Quartus II software and the Nios II Embedded Design Suite

More information

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Subscribe Latest document on the web: PDF HTML Contents Contents 1. Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference

More information

Lancelot. VGA video controller for the Altera Excalibur processors. v2.1. Marco Groeneveld May 1 st,

Lancelot. VGA video controller for the Altera Excalibur processors. v2.1. Marco Groeneveld May 1 st, Lancelot VGA video controller for the Altera Excalibur processors. v2.1 Marco Groeneveld May 1 st, 2003 http://www.fpga.nl 1. Description Lancelot is a VGA video controller for the Altera Nios and Excalibur

More information

AN 812: Qsys Pro System Design Tutorial

AN 812: Qsys Pro System Design Tutorial AN 812: Qsys Pro System Design Tutorial AN-812 2017.08.15 Subscribe Send Feedback Contents Contents Qsys Pro System Design Tutorial... 3 Hardware and Software Requirements... 4 Download and Install the

More information

CARDBUS INTERFACE USER MANUAL

CARDBUS INTERFACE USER MANUAL CARDBUS INTERFACE USER MANUAL 1 Scope The COM-13xx ComBlock modules are PC cards which support communication with a host computer through a standard CardBus interface. These ComBlock modules can be used

More information

10-Gbps Ethernet Hardware Demonstration Reference Design

10-Gbps Ethernet Hardware Demonstration Reference Design 10-Gbps Ethernet Hardware Demonstration Reference Design July 2009 AN-588-1.0 Introduction This reference design demonstrates wire-speed operation of the Altera 10-Gbps Ethernet (10GbE) reference design

More information

HyperBus Memory Controller (HBMC) Tutorial

HyperBus Memory Controller (HBMC) Tutorial Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T001A: A Qsys based Nios II Reference design with a simple self test of the HyperFlash and HyperRAM device using S/Labs' HBMC IP This tutorial

More information

Synaptic Labs HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices

Synaptic Labs HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices Benjamin Gittins Chief Technical Officer Mbl: +995 551 026 588 b.gittins@synaptic-labs.com Synaptic Laboratories Ltd. Company ID 41272593 www.synaptic-labs.com info@synaptic-labs.com Monday, July 16, 2018

More information

HyperBus Memory Controller (HBMC) Tutorial

HyperBus Memory Controller (HBMC) Tutorial Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T002A: A Qsys based Nios II reference design using Intel s MSGDMA to benchmark memory copy operations on the HyperRAM device using S/Labs' HBMC

More information

DDR and DDR2 SDRAM Controller Compiler User Guide

DDR and DDR2 SDRAM Controller Compiler User Guide DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Operations Part Number Compiler Version: 8.1 Document Date: November 2008 Copyright 2008 Altera

More information

VHDL simulation and synthesis

VHDL simulation and synthesis VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis

More information

Codec. WM8731 Audio Codec

Codec. WM8731 Audio Codec Codec WM8731 Audio Codec Codec Coder / Decoder Audio, Video Compression/decompression signal coding 2 tj WM8731 3 tj WM8731 Data Path Basic Connection 4 tj WM8731 Data Path Basic Timing 5 tj WM8731 Data

More information

SISTEMI EMBEDDED AA 2012/2013 JTAG CIRCUITRY JTAG DEBUG MODULE JTAG-UART PERIPHERAL

SISTEMI EMBEDDED AA 2012/2013 JTAG CIRCUITRY JTAG DEBUG MODULE JTAG-UART PERIPHERAL SISTEMI EMBEDDED AA 2012/2013 JTAG CIRCUITRY JTAG DEBUG MODULE JTAG-UART PERIPHERAL Joint Test Action Group (JTAG) (1) Established in 1985 to develop a method to test populated PCBs A way to access IC

More information

HyperBus Memory Controller (HBMC) Tutorial

HyperBus Memory Controller (HBMC) Tutorial Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T002A: A Qsys based Nios II reference design using Intel s MSGDMA to benchmark memory copy operations on the HyperRAM device using S/Labs' HBMC

More information

Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions

Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG AN-661-1.1 Application Note This application note describes the flow for implementing fractional phase-locked loop (PLL)

More information

Excellent for XIP applications"

Excellent for XIP applications Synaptic Labs' Tiny System Cache (CMS-T003) Tutorial T001A: Boot from On-chip Flash: A Qsys based Nios II Reference design based on S/Labs' Tiny System Cache IP and Intel's On-chip Flash Memory Controller

More information

Creating Multiprocessor Nios II Systems Tutorial

Creating Multiprocessor Nios II Systems Tutorial Creating Multiprocessor Nios II Systems Tutorial May 2006, Version 6.0 Tutorial Introduction...2 Benefits of Multiprocessor Systems...2 Nios II Multiprocessor Systems...2 Hardware Design Considerations...3

More information

13. Recommended HDL Coding Styles

13. Recommended HDL Coding Styles 13. Recommed HDL Coding Styles November 2013 QII51007-13.1.0 QII51007-13.1.0 This chapter provides Hardware Description Language (HDL) coding style recommations to ensure optimal synthesis results when

More information

Introduction to Xilinx Vivado tools

Introduction to Xilinx Vivado tools Introduction to Xilinx Vivado tools This document is meant to be a starting point for users who are new to using the Xilinx Vivado tools. The document will describe the basic steps to start, create, simulate,

More information

Quick Tutorial for Quartus II & ModelSim Altera

Quick Tutorial for Quartus II & ModelSim Altera Quick Tutorial for Quartus II & ModelSim Altera By Ziqiang Patrick Huang Hudson 213c Ziqiang.huang@duke.edu Download & Installation For Windows or Linux users : Download Quartus II Web Edition v13.0 (ModelSim

More information