Fixed-point Multiply and Accumulator IP Exercise

Transcription

1 Electrical and Computer Engineering Fixed-point Multiply and Accumulator IP Exercise By Prawat Nagvajara Synopsis Design and implement a fixed-point multiply accumulator (Fig. 1) custom Intellectual Property (IP) core as an AXI-Lite bus peripheral. Use the IP Catalog Multiply-Adder core [1]. with the IP as its AXI peripheral and an SDK project test application for transferring test data and test results to and from the IP-undertest. The project may also include a simulation script (modelsim_script.txt). Schematic Input Multiply Adder Register Output Fig. 2 Multiply Accumulate Project Directories Guide to User Logic Design Figure 1 shows multiply adder IP and an additional register whose output feeds back to the IP. The Multiply Adder is a core from the IP catalog. Configure the core as in Fig. 3. Build the core. Fig. 1 Fixed-point Multiply Accumulate IP Core Deliverable Deliver a test bench - an embedded system having the IP as a peripheral. Use an SDK application, write fixed-point test data and read the result for verification. The data are 16-bit signed. Results are 32-bit signed. Consider also signed fraction data, 5-bit integral and 11-bit fractional (Q-N format). Narrative A design flow consists of a user logic design, an AXI-bus IP package and a test bench. The design directories may look as the directories shown in Fig. 2 where user_logic directory contains a project for the design (Fig. 1), mult_acc_ip contains the project for custom IP package, and the mult_acc_tb contains an embedded design Fig. 3 Multiply Adder Configuration In the Sources -> IP pane (Fig. 4), the xbip_multadd_0.vho contains a component declaration and an instantiation template of the Multiply Adder core. Copy and paste these codes into the user_logic VHDL code (Project Manager -> Add Sources -> Add or Create Design Sources -> Create File -> VHDL file). 1

2 Fig. 4 Instantiation Templates Figure 5 shows a code for Fig. 1 user logic. Fig. 5 User Logic code Figure 6 shows an image of the core from [1]. It shows a 3-cycle latency from A:B to P. With an additional output register at output Port P (wire w in the code), and additional AXI bus input registers for Port A and Port B, the rate of the input is equal to 1/3, that is, a new input is applied on every 3 rd cycle since the feedback loop latency (delay) is equal to 3 cycles (2 cycles from C to P latency and 1 cycle from the temp register in the code describing Fig. 1). Fig. 6 LogicCORE Product Guide Block Diagram Figure 7 shows simulation results (for vivado simulation script see Appendix). Note that an additional delay in the simulation model. The 2

3 latency is 3 cycles, as the input data are valid one cycle after they appear as the inputs X_A and X_B to the user_logic entity and additional one cycle delay at the input to the xbip_multadd core. The additional xbip_multadd core input delay makes the rate become 1/3 - the application of new data is every 3rd clock cycle. Fig. 7 Modelsim Simulation Results Fig. 9 Design Hierarchy Guide on Custom IP The steps in Vivado IDE: Manage IP, new IP location, create new AXI peripheral, tools create and pack ip create new AXI peripheral with 4 registers and edit IP. Figure 8 shows the file mult_acc_ip_v1_ 0_S_AXI.vhd (mult_acc_ip/ip_repo/mult_acc_ ip_1.0/hdl), the component declaration and the instantiation. Fig. 10 IP File Groups Guide on Test bench Create a project with processing system and the IP as its peripheral. Fig. 8 AXI IP User Logic Instantiation Add Files in the order of the hierarchy (Fig. 9) of the user logic, top down 1. Add Source user_logic.vhd then 2. Add Source for the xbip_multadd_0, the.xci component 3. In IP Files Groups (Fig. 10): Merge files, right click on VHDL Synthesis Add subcore reference scr/xbip_mult_add0/ xbip_multadd0.xci. The steps in Vivado IDE: 1. Block diagram: zynq processing system UART_1, clocks for Programmable Logic, reset, AXI master 2. Project Setting IP repository rep_ip 3. Place the IP and connection (Fig. 11) 4. Create wrapper and generate bit stream 5. Export Hardware and launch SDK 6. In SDK create a C application, connect the board, program FPGA and run application 3

4 XI_BASEADDR, 12, 0x ); // write data read result (rate 1/2) Fig. 11 Block Diagram Guide to Test Application Figure 12 below shows the test application code for Fig. 13 terminal output. The application of new input is applied on every 2nd cycle rate 1/2. In this design, the peripheral advances synchronously to the write enable port mapped to the chip enable CE port of the user_logic entity. Note that the AXI slv_reg adds additional stage to the latency. Results Figure 13 below shows the test application terminal output. Reference [1] LogiCORE IP Multiply Adder v3.0 Product Guide Vivado Design Suite PG192 (v3.0) June 4, 2014 /* --> -X_A-> -A--- --> -X_B-> -B--(*)-->? -A*B-- --> -w---> -temp---->? -C---(+)--> */ #include <stdio.h> #include "platform.h" #include "xparameters.h" #include "mult_acc_ip.h" #include "xil_io.h" #include "xil_types.h" #include "xil_printf.h" int main() { init_platform(); // SCLR high clear XI_BASEADDR, 12, 0x ); // SCLR low enable XI_BASEADDR, 0, 0x ); xil_printf("x_a=1 X_B=1 w=0*0+0 XI_BASEADDR, 0, 0x ); xil_printf("x_a=2 X_B=3 w=0*0+1 temp=0 w valid\r\n"); temp=1\r\n"); XI_BASEADDR, 0, 0x000A0005); xil_printf("x_a=a X_B=5 w=2*3+1 temp=7\r\n"); 4

5 XI_BASEADDR, 0, 0x000A000A); xil_printf("x_a=a X_B=A w=a*5+7 temp=57\r\n"); XI_BASEADDR, 0, 0x A); xil_printf("x_a=14 X_B=A w=14*a // write zeros *0+357 *0+357 *0+357 *0+357 cleanup_platform(); return 0; } Fig. 12 Test Application 5

6 restart add_force {/user_logic/ck} -radix hex {1 0ns} { ps} -repeat_every ps # Chip Enable CE set add_force {/user_logic/ce} -radix hex {1 0ns} add_force {/user_logic/sclr} -radix hex {1 0ns} # registers, X_A, X_B cleared # disable clear add_force {/user_logic/sclr} -radix hex {0 0ns} {1 0ns} {1 0ns} # disable clear, X_A, X_B valid # A, B, temp valid # A*B, C Valid {2 0ns} {3 0ns} # W, X_A and X_B valid # A, B, temp valid # A*B, C valid {5 0ns} # X_A, X_B, W valid Fig. 13 Test Application Terminal Output Appendix Vivado Simulation Script # simulation Multiply accumulate # # --> -X_A-> -A--- # # --> -X_B-> -B--(*)-->? -A*B-- # # --> -w---> -temp---->? -C---(+)--> # # {20 0ns} 6

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