Real Time & Embedded Systems. STM32 GPIO and Timers

Transcription

1 Real Time & Embedded Systems STM GPIO and Timers

2 GPIO

3 Memory Map of Cortex-M. GB xffffffff xe System NVIC, System Timer, SCB, vendor-specific memory GB External Device Such as SD card xa GB External RAM GB Off-chip memory for data. GB. GB x x Peripheral SRAM AHB & APB, such as timers, GPIO On-chip RAM, for heap, stack, & cod. GB x x Code On-chip Flash, for code & data One Byte (8 bits)

4 Memory Map of STML. GB xffffffff System xe GB External Device GB. GB. GB. GB xa x x x x External RAM Peripheral SRAM Code x x8 x8c x88 x8 x8 x GPIO D ( KB) GPIO C ( KB) GPIO B ( KB) GPIO A ( KB) One Byte (8 bits)

5 GPIO Memory Map x8 x8 x8 GPIO A ( KB) x8c x88 x8 x8 x8c x88 x8 x8 x8c x88 x8 x8 ASCR BRR AFR[] AFR[] LCKR BSRR ODR IDR PUPDR OSPEEDR OTYPER MODER 8 bytes Each register has bytes

6 GPIO Memory Map x8 Set pin A. to high x8 x8 GPIO A ( KB) x8c x88 x8 x8 x8c x88 x8 x8 x8c x88 x8 x8 ASCR BRR AFR[] AFR[] LCKR BSRR ODR IDR PUPDR OSPEEDR OTYPER MODER 8 bytes Set bit of ODR to high

7 Output Data Register (ODR) x87 x8 ODR word (i.e. bits) x87 x8 x8 x8 bytes Little Endian

8 Output Data Register (ODR) x87 x8 ODR word (i.e. bits) x87 x8 x8 x8 bytes Little Endian *((uint_t *) x8) = UL<<; Dereferencing a pointer Bitwise OR 8

9 Dereferencing a Memory Address x8c x88 x8 x8 x8c x88 x8 x8 x8c x88 x8 x8 ASCR BRR AFR[] AFR[] LCKR BSRR ODR IDR PUPDR OSPEEDR OTYPER MODER typedef struct { volatile uint_t MODER; // Mode register volatile uint_t OTYPER; // Output type register volatile uint_t OSPEEDR; // Output speed register volatile uint_t PUPDR; // Pull-up/pull-down register volatile uint_t IDR; // Input data register volatile uint_t ODR; // Output data register volatile uint_t BSRR; // Bit set/reset register volatile uint_t LCKR; // Configuration lock register volatile uint_t AFR[]; // Alternate function registers volatile uint_t BRR; // Bit Reset register volatile uint_t ASCR; // Analog switch control register } GPIO_TypeDef; // Casting memory address to a pointer #define GPIOA ((GPIO_TypeDef *) x8) GPIOA->ODR = UL<<; 9

10 General Purpose Input/Output (GPIO) 8 GPIO Ports: A, B, C, D, E, F, G, H Up to pins in each port

11 Basic Structure of an I/O Port Bit Input and Output Schmitt trigger volts=.8v

12 GPIO Input: Pull Up and Pull Down A digital input can have three states: High, Low, and High-Impedance (also called floating, tri-stated, HiZ) Pull-Up If external input is HiZ, the input is read as a valid HIGH. Pull-Down If external input is HiZ, the input is read as a valid LOW.

13 Buttons / switches

14 I/O Debouncing Example signal when a button is pressed Voltage across push button Time (microseconds)

15 Noisy analog signals V in Threshold Analog signals Noisy Rise and fall slowly (small slew rate) A button press can generate a noisy transition for up to msec if not debounced in hardware

16 produce noisy digital signals V in Threshold Simple Comparator

17 Schmitt Trigger V out V in V out V TH V TL Immunity Band V TH V in V out V TL V in V DD Schmitt Trigger V out V TL V TH V in V DD Simple Comparator Trigger Low Trigger High 7

18 Basic Structure of an I/O Port Bit: Input bit= volts=.8v Schmitt trigger Input Data Register (IDR) GPIO Pull-up/Pull-down Register (PUPDR) = No pull-up, pull-down = Pull-up = Pull-down = Reserved 8

19 TIMERS 9

20 Timer Free-run counter (independent of processor) Functions Input capture Output compare Pulse-width modulation (PWM) generation One-pulse mode output STM has many application notes (on all aspects of the STM) App note AN77 General Purpose Timer Cookbook

21 Timer: Clock Reload Value ARR Reload f CL_PSC clock PSC Prescaler f CL_CNT Timer Counter ISR Interrupt ff CCCC_CCCCCC = ff CCCC_PPPPPP PPPPPP +

22 Timer: Output Reload Value ARR Reload f CL_PSC clock PSC Prescaler f CL_CNT Timer Counter ISR Interrupt = Timer Output (OCREF) Compare & Capture Register (CCR)

23 Timer: Input Capture Reload Value ARR Reload f CL_PSC clock PSC Prescaler f CL_CNT Timer Counter ISR Interrupt Trigger event (e.g. rising edge of external signal) Compare & Capture Register (CCR)

24 Multi-Channel Outputs

25 PWM Mode (Pulse Width Modulation) Period Period = T off + T on Mode Duty Cycle = TT oooo TT oooooo +TT oooo Mode Counter < Reference Counter Reference PWM mode (Low True) PWM mode (High True) Active Low Inactive Inactive Active High

26 Edge-aligned Mode (Up-counting) ARR =, RCR = clock counter Counter overflow Counter overflow Counter overflow Counter overflow Update event (UEV) Period = ( + ARR) * Clock Period = 7 * Clock Period ARR = Auto-Reload Register UEV = Update Event RCR = Repetition Count Register

27 Edge-aligned Mode (downcounting) ARR =, RCR = Clock Counter Counter underflow Counter underflow Counter underflow Counter underflow Update event (UEV) Period = ( + ARR) * Clock Period = 7 * Clock Period 7

28 Center-aligned Mode ARR =, RCR = Clock Counter Counter overflow Counter underflow Counter overflow Counter underflow Update event (UEV) Period = ( * ARR) * Clock Period = * Clock Period 8

29 PWM Mode (Low-True) Timer Output = High if counter < CCR Low if counter CCR Upcounting mode, ARR =, CCR =, RCR = Clock Counter CCR = OCREF CCR Duty Cycle = ARR + = 7 Period = ( + ARR) * Clock Period = 7 * Clock Period 9

30 PWM Mode (High-True) Timer Output = Low if counter < CCR High if counter CCR Upcounting mode, ARR =, CCR =, RCR = Clock Counter CCR = OCREF Duty Cycle = - = 7 CCR ARR + Period = ( + ARR) * Clock Period = 7 * Clock Period

31 PWM Mode (High-True) Timer Output = Low if counter < CCR High if counter CCR Upcounting mode, ARR =, CCR =, RCR = Clock Counter CCR = OCREF Duty Cycle = - = 7 CCR ARR + Period = ( + ARR) * Clock Period = 7 * Clock Period

32 PWM Mode (High-True) Timer Output = Low if counter < CCR High if counter CCR Center-aligned mode, ARR =, CCR =, RCR = Clock Counter CCR = OCREF Duty Cycle = - CCR ARR = Period = * ARR * Clock Period = * Clock Period

33 PWM Mode (High-True) Timer Output = Low if counter < CCR High if counter CCR Center-aligned mode, ARR =, CCR =, RCR = Clock Counter CCR = OCREF Duty Cycle = - CCR ARR = Period = * ARR * Clock Period = * Clock Period

34 Auto-Reload Register (ARR) Auto-Reload Preload Enable (ARPE) bit in TIMx_CR ARPE = (Synchronous Update) Write to ARR Read from ARR Preload Register Auto-reload Register (ARR) If UDIS bit in TIMx_CR is, UEV event is disabled. Triggered by Update Event (UEV) ARPE = (Asynchronous Update) Write to ARR Read from ARR Auto-reload Register (ARR)

35 Repetition Counter Register (RCR)

36 Repetition Counter Register (RCR)

37 Repetition Counter Register (RCR) 7

38 Repetition Counter Register (PCR) 8

39 Repetition Counter Register (PCR) 9

40 PWM Output Polarity Mode Counter < CCR Counter CCR PWM mode (Low True) PWM mode (High True) Active (Low) Inactive Inactive Active (High) Output Polarity: Software can program the CCxP bit in the TIMx_CCER register Active Inactive Active High High Voltage Low Voltage Active Low Low Voltage High Voltage

41 Up-Counting: Left Edge-aligned Upcounting mode, ARR =, CCR =, RCR = Clock Counter CCR = CCR = CCR = OCREF CCR = OCREF All rising edges occur at the same time! Left-aligned PWM Period

42 PWM Mode : Right Edge-aligned Upcounting mode, ARR =, CCR =, RCR = Clock Counter CCR = CCR = OCREF CCR = OCREF CCR = All falling edges occur at the same time! Right-aligned PWM Period

43 PWM Mode : Center Aligned Timer Output = Low if counter < CCR High if counter CCR Center-aligned mode, ARR =, CCR =, RCR = Clock Counter CCR = CCR = OCREF CCR = OCREF CCR = PWM signals are center aligned! Center-aligned PWM Period

44 The devil is in the detail Timer output control Enable Timer Output MOE: Main output enable OSSI: Off-state selection for Idle mode OSSR: Off-state selection for Run mode CCxE: Enable of capture/compare output for channel x CCxNE: Enable of capture/compare complementary output for channel x

45 Input Capture Monitor both rising and falling edge

46 Input Capture Monitor only rising edges or only falling edge

47 Input Capture 7

48 Input Capture Diagram 8

49 WHY IS THE MEASUREMENT OF TIME INTERESTING??? 9

50 Bats use echolocation to map their surroundings?

51 Ultrasonic Distance Sensor DDDDDDDDDDDDDDDD = RRRRRRRRRR TTTTTTTT TTTTTTTT SSSSSSSSSS oooo SSSSSSSSSS = RRRRRRRRRR TTTTTTTT TTTTTTTT µss mm/ss = RRRRRRRRRR TTTTTTTT TTTTTTTT µss 8

52 Ultrasonic Distance Sensor The delay from triggered chirp to echo response is the round-trip time t RT. Trigger a call t RT DDDDDDDDDDDDDDDD (cccc) = RRRRRRRRRR tttttttt tttttttt (μμμμ) Echo response If t RT > is ms, no obstacle is detected.

53 Ultrasonic Distance Sensor