11 General-Purpose Timers

Transcription

1 General-Purpose Timers General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The TM4C23GH6PM General-Purpose Timer Module(GPTM) contains six 6/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks. Each 6/32-bit GPTM block provides two 6-bit timers/counters (referredtoastimeraandtimerb)thatcanbeconfiguredtooperateindependentlyastimersor event counters, or concatenated to operate as one 32-bit timer or one 32-bit Real-Time Clock(RTC). Each32/64-bitWideGPTMblockprovides32-bittimersforTimerAandTimerBthatcanbe concatenated to operate as a 64-bit timer. Timers can also be used to trigger μdma transfers. In addition, timers can be used to trigger analog-to-digital conversions(adc) when a time-out occurs in periodic and one-shot modes. The ADC trigger signals from all of the general-purpose timers are ORedtogetherbeforereachingtheADCmodule,soonlyonetimershouldbeusedtotriggerADC events. The GPT Module is one timing resource available on the Tiva C Series microcontrollers. Other timerresourcesincludethesystemtimer(systick)(see23)andthepwmtimerinthepwm modules(see PWM Timer on page 234). The General-Purpose Timer Module(GPTM) contains six 6/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks with the following functional options: 6/32-bit operating modes: 6- or 32-bit programmable one-shot timer 6- or 32-bit programmable periodic timer 6-bit general-purpose timer with an 8-bit prescaler 32-bit Real-Time Clock(RTC) when using an external KHz clock as the input 6-bit input-edge count- or time-capture modes with an 8-bit prescaler 6-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal 32/64-bit operating modes: 32- or 64-bit programmable one-shot timer 32- or 64-bit programmable periodic timer 32-bit general-purpose timer with a 6-bit prescaler 64-bit Real-Time Clock(RTC) when using an external KHz clock as the input 32-bit input-edge count- or time-capture modes with a6-bit prescaler 32-bit PWM mode with a 6-bit prescaler and software-programmable output inversion of the PWM signal Countupordown Twelve 6/32-bit Capture Compare PWM pins(ccp) 74 June 2, 24

2 Tiva TM4C23GH6PMMicrocontroller Twelve 32/64-bit Capture Compare PWM pins(ccp) Daisy chaining of timer modules to allow a single timer to initiate multiple timing events Timer synchronization allows selected timers to start counting on the same clock cycle ADC event trigger User-enabled stalling when the microcontroller asserts CPU Halt flag during debug(excluding RTC mode) Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine Efficient transfers using Micro Direct Memory Access Controller(µDMA) Dedicated channel for each timer Burst request generated on timer interrupt. Block Diagram In the block diagram, the specific Capture Compare PWM(CCP) pins available depend on the TM4C23GH6PMdevice.SeeTable-onpage76fortheavailableCCPpinsandtheirtimer assignments. Figure -. GPTM Module Block Diagram xffff.ffff(up Counter Modes, 32-/64-bit) x. (Down Counter Modes, 32-/64-bit) xffff (Up Counter Modes, 6-/32-bit) x (Down Counter Modes, 6-/32-bit) Timer A Free-Running Timer A Control GPTMTAPS GPTMTAPMR GPTMTAPR TA Comparator Timer A Interrupt Timer B Interrupt Interrupt / Config GPTMCFG GPTMCTL GPTMIMR GPTMRIS GPTMMIS GPTMICR GPTMSYNC GPTMPP GPTMTAMATCHR GPTMTAILR GPTMTAMR Timer B Control GPTMTBMR GPTMTBILR GPTMTART En GPTMTAPV GPTMTAV GPTMTBV GPTMTBPV GPTMTBR En Clock/Edge Detect RTC Divider RTC Predivider GPTMRTCPD Clock/Edge Detect 32KHzor EvenCCPPin OddCCPPin GPTMTBMATCHR TB Comparator Timer B Free-Running GPTMTBPR GPTMTBPMR GPTMTBPS System Clock x (Down Counter Modes, 6-/32-bit) xffff (Up Counter Modes, 6-/32-bit) x. (Down Counter Modes, 32-/64-bit) xffff.ffff(up Counter Modes, 32-/64-bit) June 2, 24 75

3 General-Purpose Timers Table -. Available CCP Pins Timer Up/Down Counter Even CCP Pin OddCCP Pin 6/32-Bit Timer Timer A Timer B TCCP - - TCCP 6/32-Bit Timer Timer A Timer B TCCP - - TCCP 6/32-Bit Timer 2 Timer A Timer B T2CCP - - T2CCP 6/32-Bit Timer 3 Timer A Timer B T3CCP - - T3CCP 6/32-Bit Timer 4 Timer A Timer B T4CCP - - T4CCP 6/32-Bit Timer 5 Timer A Timer B T5CCP - - T5CCP 32/64-Bit Wide Timer Timer A Timer B WTCCP - - WTCCP 32/64-Bit Wide Timer Timer A Timer B WTCCP - - WTCCP 32/64-Bit Wide Timer 2 Timer A Timer B WT2CCP - - WT2CCP 32/64-Bit Wide Timer 3 Timer A Timer B WT3CCP - - WT3CCP 32/64-Bit Wide Timer 4 Timer A Timer B WT4CCP - - WT4CCP 32/64-Bit Wide Timer 5 Timer A Timer B WT5CCP - - WT5CCP.2 Signal The following table lists the external signals of the GP Timer module and describes the function of each.thegptimersignalsarealternatefunctionsforsomegpiosignalsanddefaulttobegpio signals at reset. The column in the table below titled"pin Mux/Pin Assignment" lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function Select(GPIOAFSEL) register(page 67) should be set to choose the GP Timer function. The number inparenthesesistheencodingthatmustbeprogrammedintothepmcnfieldinthe GPIOPort Control(GPIOPCTL) register(page 688) to assign the GP Timer signal to the specified GPIO port pin. For more information on configuring GPIOs, see General-Purpose Input/Outputs (GPIOs) on page 649. Table -2. General-Purpose Timers Signals(64LQFP) Pin Pin Number PinMux / Pin Assignment Pin Buffer a TCCP 28 PB6(7) PF(7) I/O TTL 6/32-Bit Timer Capture/Compare/PWM. TCCP 4 29 PB7(7) PF(7) I/O TTL 6/32-Bit Timer Capture/Compare/PWM. 76 June 2, 24

4 Tiva TM4C23GH6PMMicrocontroller Table -2. General-Purpose Timers Signals(64LQFP)(continued) Pin TCCP TCCP T2CCP T2CCP T3CCP T3CCP T4CCP T4CCP T5CCP T5CCP WTCCP WTCCP WTCCP WTCCP WT2CCP WT2CCP WT3CCP WT3CCP WT4CCP WT4CCP WT5CCP WT5CCP Pin Number PinMux / Pin Assignment PF2(7) PB4(7) PF3(7) PB5(7) PF4(7) PB(7) PB(7) PB2(7) PB3(7) PC(7) PC(7) PC2(7) PC3(7) PC4(7) PC5(7) PC6(7) PC7(7) PD(7) PD(7) PD2(7) PD3(7) PD4(7) PD5(7) PD6(7) PD7(7) Pin a. The TTL designation indicates the pin has TTL-compatible voltage levels. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer a TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL 6/32-Bit Timer Capture/Compare/PWM. 6/32-Bit Timer Capture/Compare/PWM. 6/32-Bit Timer 2 Capture/Compare/PWM. 6/32-Bit Timer 2 Capture/Compare/PWM. 6/32-Bit Timer 3 Capture/Compare/PWM. 6/32-Bit Timer 3 Capture/Compare/PWM. 6/32-Bit Timer 4 Capture/Compare/PWM. 6/32-Bit Timer 4 Capture/Compare/PWM. 6/32-Bit Timer 5 Capture/Compare/PWM. 6/32-Bit Timer 5 Capture/Compare/PWM. 32/64-Bit Wide Timer Capture/Compare/PWM. 32/64-Bit Wide Timer Capture/Compare/PWM. 32/64-Bit Wide Timer Capture/Compare/PWM. 32/64-Bit Wide Timer Capture/Compare/PWM. 32/64-Bit Wide Timer 2 Capture/Compare/PWM. 32/64-Bit Wide Timer 2 Capture/Compare/PWM. 32/64-Bit Wide Timer 3 Capture/Compare/PWM. 32/64-Bit Wide Timer 3 Capture/Compare/PWM. 32/64-Bit Wide Timer 4 Capture/Compare/PWM. 32/64-Bit Wide Timer 4 Capture/Compare/PWM. 32/64-Bit Wide Timer 5 Capture/Compare/PWM. 32/64-Bit Wide Timer 5 Capture/Compare/PWM..3 Functional The main components of each GPTM block are two free-running up/down counters(referred to as Timer A and Timer B), two prescaler registers, two match registers, two prescaler match registers, two shadow registers, and two load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface.timeraandtimerbcanbeusedindividually,inwhichcasetheyhavea6-bitcounting range for the 6/32-bit GPTM blocks and a 32-bit counting range for 32/64-bit Wide GPTM blocks. Inaddition,TimerAandTimerBcanbeconcatenatedtoprovidea32-bitcountingrangeforthe 6/32-bit GPTM blocks and a 64-bit counting range for the 32/64-bit Wide GPTM blocks. Note that the prescaler can only be used when the timers are used individually. TheavailablemodesforeachGPTMblockareshowninTable-3onpage78.Notethatwhen counting down in one-shot or periodic modes, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up in one-shot or periodic modes, the prescaler actsasatimerextensionandholdsthemost-significantbitsofthecount.ininputedgecount,input edgetimeandpwmmode,theprescaleralwaysactsasatimerextension,regardlessofthecount direction. June 2, 24 77

5 General-Purpose Timers Table -3. General-Purpose Timer Capabilities Mode One-shot Periodic RTC Edge Count Edge Time PWM Timer Use Individual Concatenated Individual Concatenated Concatenated Individual Individual Individual Count Direction UporDown UporDown UporDown UporDown Up UporDown UporDown Down 6/32-bit GPTM 6-bit 32-bit 6-bit 32-bit 32-bit 6-bit 6-bit 6-bit Counter Size 32/64-bit Wide GPTM 32-bit 64-bit 32-bit 64-bit 64-bit 32-bit 32-bit 32-bit a. The prescaler is only available when the timers are used individually Prescaler Size a 6/32-bit GPTM 8-bit - 8-bit bit 8-bit 8-bit 32/64-bit Wide GPTM 6-bit - 6-bit bit 6-bit 6-bit Prescaler Behavior (Count Direction) Timer Extension(Up), Prescaler(Down) N/A Timer Extension(Up), Prescaler(Down) N/A N/A Timer Extension (Both) Timer Extension (Both) Timer Extension Software configures the GPTM using the GPTM Configuration(GPTMCFG) register(see page 727), the GPTMTimer A Mode (GPTMTAMR)register(seepage729),andthe GPTMTimer B Mode (GPTMTBMR) register(see page 733). When in one of the concatenated modes, Timer A and Timer Bcanonlyoperateinonemode.However,whenconfiguredinanindividualmode,TimerAand Timer B can be independently configured in any combination of the individual modes..3. GPTM Conditions AfterresethasbeenappliedtotheGPTMmodule,themoduleisinaninactivestate,andallcontrol registersareclearedandintheirdefaultstates.counterstimeraandtimerbareinitializedtoall s, along with their corresponding registers: Load Registers: GPTM Timer A Interval Load(GPTMTAILR) register(see page 756) GPTM Timer B Interval Load(GPTMTBILR) register(see page 757) Shadow Registers: GPTMTimer A (GPTMTAV)register(seepage766) GPTMTimer B (GPTMTBV)register(seepage767) The following prescale counters are initialized to all s: GPTM Timer A Prescale (GPTMTAPR) register(see page 76) GPTM Timer B Prescale (GPTMTBPR) register(see page 76) GPTM Timer A Prescale Snapshot(GPTMTAPS) register(see page 769) GPTM Timer B Prescale Snapshot(GPTMTBPS) register(see page 77) GPTM Timer A Prescale (GPTMTAPV) register(see page 77) 78 June 2, 24

6 Tiva TM4C23GH6PMMicrocontroller GPTM Timer B Prescale (GPTMTBPV) register(see page 772).3.2 Timer Modes Thissectiondescribestheoperationofthevarioustimermodes.WhenusingTimerAandTimerB inconcatenatedmode,onlythetimeracontrolandstatusbitsmustbeused;thereisnoneedto usetimerbcontrolandstatusbits.thegptmisplacedintoindividual/splitmodebywritingavalue of x4 to the GPTM Configuration(GPTMCFG) register(see page 727). In the following sections, thevariable"n"isusedinbitfieldandregisternamestoimplyeitheratimerafunctionoratimer B function. Throughout this section, the timeout event in down-count mode is x and in up-count modeisthevalueinthegptmtimernintervalload(gptmtnilr)andtheoptionalgptmtimer n Prescale (GPTMTnPR) registers, with the exception of RTC mode One-Shot/Periodic Timer Mode Theselectionofone-shotorperiodicmodeisdeterminedbythevaluewrittentotheTnMRfieldof the GPTMTimer n Mode (GPTMTnMR)register(seepage729).Thetimerisconfiguredtocount upordownusingthetncdirbitinthe GPTMTnMRregister. WhensoftwaresetstheTnENbitinthe GPTMControl(GPTMCTL)register(seepage737),the timer begins counting up from x or down from its preloaded value. Alternatively, if the TnWOT bit issetinthe GPTMTnMRregister,oncetheTnENbitisset,thetimerwaitsforatriggertobegin counting(see Wait-for-Trigger Mode on page 78). Table -4 on page 79 shows the values that are loaded into the timer registers when the timer is enabled. Table -4. Counter s When the Timer is Enabled in Periodic or One-Shot Modes Register GPTMTnR GPTMTnV GPTMTnPS GPTMTnPV Count Down Mode GPTMTnILR GPTMTnILR in concatenated mode; GPTMTnPR in combination with GPTMTnILR in individual mode GPTMTnPR in individual mode; not available in concatenated mode GPTMTnPR in individual mode; not available in concatenated mode Count Up Mode x x x in individual mode; not available in concatenated mode x in individual mode; not available in concatenated mode Whenthetimeriscountingdownanditreachesthetimeoutevent(x),thetimerreloadsitsstart valuefromthe GPTMTnILRandthe GPTMTnPRregistersonthenextcycle.Whenthetimeris countingupanditreachesthetimeoutevent(thevalueinthe GPTMTnILRandtheoptional GPTMTnPR registers), the timer reloads with x. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, the timer starts counting again on the next cycle. Inperiodic,snap-shotmode(TnMRfieldisx2andtheTnSNAPSbitissetinthe GPTMTnMR register),thevalueofthetimeratthetime-outeventisloadedintothe GPTMTnRregisterandthe value of the prescaler is loaded into the GPTMTnPS register. The free-running counter value is shown in the GPTMTnV register and the free-running prescaler value is shown in the GPTMTnPV register. In this manner, software can determine the time elapsed from the interrupt assertion to the ISR entry by examining the snapshot values and the current value of the free-running timer. Snapshot mode is not available when the timer is configured in one-shot mode. In addition to reloading the count value, the GPTM can generate interrupts, CCP outputs and triggers whenitreachesthetime-outevent.thegptmsetsthetntorisbitinthe GPTMRaw Interrupt Status (GPTMRIS)register(seepage748),andholdsituntilitisclearedbywritingthe GPTM Interrupt Clear(GPTMICR) register(see page 754). If the time-out interrupt is enabled in the GPTM June 2, 24 79

7 General-Purpose Timers Interrupt Mask (GPTMIMR) register(see page 745), the GPTM also sets the TnTOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register(see page 75). By setting the TnMIE bit in the GPTMTnMR register, an interrupt condition can also be generated when the Timer value equals the value loaded into the GPTM Timer n Match(GPTMTnMATCHR) and GPTM Timer n Prescale Match(GPTMTnPMR) registers. This interrupt has the same status, masking, and clearing functions as the time-out interrupt, but uses the match interrupt bits instead (for example, the raw interrupt status is monitored via TnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register). Note that the interrupt status bits are not updated by the hardware unless the TnMIEbitinthe GPTMTnMRregisterisset,whichisdifferentthanthebehaviorforthetime-out interrupt.theadctriggerisenabledbysettingthetnotebitin GPTMCTL.IftheADCtriggeris enabled, only a one-shot or periodic time-out event can produce an ADC trigger assertion. The μdma trigger is enabled by configuring and enabling the appropriate μdma channel. See Channel Configuration on page 589. If software updates the GPTMTnILR or the GPTMTnPR register while the counter is counting down, thecounterloadsthenewvalueonthenextclockcycleandcontinuescountingfromthenewvalue ifthetnildbitinthe GPTMTnMRregisterisclear.IftheTnILDbitisset,thecounterloadsthe new value after the next timeout. If software updates the GPTMTnILR or the GPTMTnPR register whilethecounteriscountingup,thetimeouteventischangedonthenextcycletothenewvalue. If software updates the GPTM Timer n (GPTMTnV) register while the counter is counting up ordown,thecounterloadsthenewvalueonthenextclockcycleandcontinuescountingfromthe new value. If software updates the GPTMTnMATCHR or the GPTMTnPMR registers, the new values arereflectedonthenextclockcycleifthetnmrsubitinthe GPTMTnMRregisterisclear.Ifthe TnMRSUbitisset,thenewvaluewillnottakeeffectuntilthenexttimeout. Whenusinga32/64-bitwidetimerblockina64-bitmode,certainregistersmustbeaccessedinthe manner described in Accessing Concatenated 32/64-Bit Wide GPTM Register s on page 72. IftheTnSTALLbitinthe GPTMCTLregisterissetandtheRTCENbitisnotsetinthe GPTMCTL register, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. If the RTCEN bit is set, it prevents the TnSTALL bit from freezing the count when the processor is halted by the debugger. The following table shows a variety of configurations for a 6-bit free-running timer while using the prescaler. All values assume an 8-MHz clock with Tc=2.5 ns(clock period). The prescaler can onlybeusedwhena6/32-bittimerisconfiguredin6-bitmodeandwhena32/64-bittimeris configured in 32-bit mode. Table Bit Timer With Prescaler Configurations Prescale (8-bit value) # of Timer Clocks (Tc) a Max Time Units.892 ms ms ms ms ms ms a.tcistheclockperiod. The following table shows a variety of configurations for a 32-bit free-running timer using the prescaler while configured in 32/64-bit mode. All values assume an 8-MHz clock with Tc=2.5 ns(clock period). 7 June 2, 24

8 Tiva TM4C23GH6PMMicrocontroller Table Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations Prescale (6-bit value) # of Timer Clocks (Tc) a Max Time Units x s x s x s xfffd s xfffe s xffff s a.tcistheclockperiod Real-Time Clock Timer Mode In Real-Time Clock(RTC) mode, the concatenated versions of the Timer A and Timer B registers areconfiguredasanup-counter.whenrtcmodeisselectedforthefirsttimeafterreset,the counterisloadedwithavalueofx.allsubsequentloadvaluesmustbewrittentothe GPTM Timer n Interval Load(GPTMTnILR) registers(see page 756). If the GPTMTnILR register is loaded withanewvalue,thecounterbeginscountingatthatvalueandrollsoveratthefixedvalueof xffffffff. Table -7 on page 7 shows the values that are loaded into the timer registers when the timer is enabled. Table -7. Counters Whenthe Timer is Enabledin RTC Mode Register GPTMTnR GPTMTnV GPTMTnPS GPTMTnPV Count Down Mode Not available Not available Not available Not available Count Up Mode x x Not available Not available TheinputclockonaCCPinputisrequiredtobe32.768KHzinRTCmode.Theclocksignalis thendivideddowntoa-hzrateandispassedalongtotheinputofthecounter. When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from its preloaded value of x. When the current count value matches the preloaded value in the GPTMTnMATCHR registers, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting untileitherahardwarereset,oritisdisabledbysoftware(clearingthetaenbit).whenthetimer value reaches the terminal count, the timer rolls over and continues counting up from x. If the RTCinterruptisenabledin GPTMIMR,theGPTMalsosetstheRTCMISbitin GPTMMISand generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. In this mode, the GPTMTnR and GPTMTnV registers always have the same value. Whenusinga32/64-bitwidetimerblockinaRTCmode,certainregistersmustbeaccessedinthe manner described in Accessing Concatenated 32/64-Bit Wide GPTM Register s on page 72. The value of the RTC predivider can be read in the GPTM RTC Predivide(GPTMRTCPD) register. To ensure that the RTC value is coherent, software should follow the process detailed in Figure -2onpage72. June 2, 24 7

9 General-Purpose Timers Figure -2. Reading the RTC ReadTimerB=B ReadTimerA=A Read Predivider ReadTimerA=A 2 Does A =A 2? no yes ReadTimerB=B 2 Does B =B 2? no Done yes In addition to generating interrupts, the RTC can generate a μdma trigger. The μdma trigger is enabled by configuring and enabling the appropriate μdma channel. See Channel Configuration on page Input Edge-Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is /4 of the system frequency. InEdge-Countmode,thetimerisconfiguredasa24-bitor48-bitup-orup-ordown-counterincluding the optional prescaler with the upper count value stored in the GPTM Timer n Prescale(GPTMTnPR) registerandthelowerbitsinthegptmtnrregister.inthismode,thetimeriscapableofcapturing three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, thetncmrbitofthe GPTMTnMRregistermustbecleared.Thetypeofedgethatthetimercounts is determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode, the timer counts from x to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater 72 June 2, 24

10 Tiva TM4C23GH6PMMicrocontroller than the value of GPTMTnPMR and GPTMTnMATCHR. Table -8 on page 73 shows the values that are loaded into the timer registers when the timer is enabled. Table -8. Counter s When the Timer is Enabled in Input Edge-Count Mode Register GPTMTnR GPTMTnV GPTMTnPS GPTMTnPV Count Down Mode GPTMTnPR in combination with GPTMTnILR GPTMTnPR in combination with GPTMTnILR GPTMTnPR GPTMTnPR Count Up Mode x x x x When software writes the TnEN bit in the GPTM Control(GPTMCTL) register, the timer is enabled foreventcapture.eachinputeventontheccppindecrementsorincrementsthecounterbyuntil the event count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnMMIS bit in the GPTM Masked Interrupt Status(GPTMMIS) register. In this mode, the GPTMTnR and GPTMTnPS registers hold the count of the input events while the GPTMTnV and GPTMTnPV registers hold the free-running timer value and the free-running prescaler value.in up count mode, thecurrentcountofinputeventsisheldinboththe GPTMTnRand GPTMTnVregisters. In addition to generating interrupts, a μdma trigger can be generated. The μdma trigger is enabled by configuring and enabling the appropriate μdma channel. See Channel Configuration on page 589. After the match value is reached in down-count mode, the counter is then reloaded using the value in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears thetnenbitinthe GPTMCTLregister.Oncetheeventcounthasbeenreached,allfurtherevents are ignored until TnEN is re-enabled by software. In up-count mode, the timer is reloaded with x and continues counting. Figure-3onpage74showshowInputEdge-Countmodeworks.Inthiscase,thetimerstart valueissettogptmtnilr=xaandthematchvalueissettogptmtnmatchr=x6so thatfouredgeeventsarecounted.thecounterisconfiguredtodetectbothedgesoftheinputsignal. NotethatthelasttwoedgesarenotcountedbecausethetimerautomaticallyclearstheTnENbit after the current count matches the value in the GPTMTnMATCHR register. June 2, 24 73

11 General-Purpose Timers Figure -3. Input Edge-Count Mode Example, Counting Down Count Timer stops, flags asserted Timer reload on next cycle Ignored Ignored xa x9 x8 x7 x6 Input Signal Input Edge-Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is /4 of the system frequency. In Edge-Time mode, the timer is configured as a 24-bit or 48-bit up- or down-counter including the optional prescaler with the upper timer value stored in the GPTMTnPR register and the lower bits inthegptmtnilrregister.inthismode,thetimerisinitializedtothevalueloadedinthegptmtnilr and GPTMTnPR registers when counting down and x when counting up. The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time modebysettingthetncmrbitinthe GPTMTnMRregister,andthetypeofeventthatthetimer captures is determined by the TnEVENT fields of the GPTMCTL register. Table -9 on page 74 showsthevaluesthatareloadedintothetimerregisterswhenthetimerisenabled. Table -9. Counter s When the Timer is Enabled in Input Event-Count Mode Register TnR TnV TnPS TnPV Count Down Mode GPTMTnILR GPTMTnILR GPTMTnPR GPTMTnPR Count Up Mode x x x x When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current timer counter value is captured in the GPTMTnR and GPTMTnPS register and is available to be read by the microcontroller. The GPTM then asserts the CnERIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the 74 June 2, 24

12 Tiva TM4C23GH6PMMicrocontroller GPTMTnR and GPTMTnPS registers hold the time at which the selected input event occurred while the GPTMTnV and GPTMTnPV registers hold the free-running timer value and the free-running prescaler value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. In addition to generating interrupts, a μdma trigger can be generated. The μdma trigger is enabled by configuring the appropriate μdma channel. See Channel Configuration on page 589. Afteraneventhasbeencaptured,thetimerdoesnotstopcounting.Itcontinuestocountuntilthe TnENbitiscleared.Whenthetimerreachesthetimeoutvalue,itisreloadedwithxinup-count mode and the value from the GPTMTnILR and GPTMTnPR registers in down-count mode. Figure-4onpage75showshowinputedgetimingmodeworks.Inthediagram,itisassumed thatthestartvalueofthetimeristhedefaultvalueofxffff,andthetimerisconfiguredtocapture rising edge events. Eachtimearisingedgeeventisdetected,thecurrentcountvalueisloadedintotheGPTMTnRand GPTMTnPS registers, and is held there until another rising edge is detected(at which point the new count value is loaded into the GPTMTnR and GPTMTnPS registers). Figure Bit Input Edge-Time Mode Example Count xffff GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal Note: WhenoperatinginEdge-timemode,thecounterusesamodulo2 24 countifprescaleris enabledor2 6,ifnot.Ifthereisapossibilitytheedgecouldtakelongerthanthecount,then another timer configured in periodic-timer mode can be implemented to ensure detection ofthemissededge.theperiodictimershouldbeconfiguredinsuchawaythat: Theperiodictimercyclesatthesamerateastheedge-timetimer The periodic timer interrupt has a higher interrupt priority than the edge-time timeout interrupt. If the periodic timer interrupt service routine is entered, software must check if an edge-timeinterruptispendingandifitis,thevalueofthecountermustbesubtracted bybeforebeingusedtocalculatethesnapshottimeoftheevent. June 2, 24 75

13 General-Purpose Timers PWM Mode TheGPTMsupportsasimplePWMgenerationmode.InPWMmode,thetimerisconfiguredasa 24-bit or 48-bit down-counter with a start value(and thus period) defined by the GPTMTnILR and GPTMTnPR registers. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by settingthetnamsbittox,thetncmrbittox,andthetnmrfieldtox2.table-onpage76 showsthevaluesthatareloadedintothetimerregisterswhenthetimerisenabled. Table -. Counters Whenthe Timer is Enabledin PWM Mode Register GPTMTnR GPTMTnV GPTMTnPS GPTMTnPV Count Down Mode GPTMTnILR GPTMTnILR GPTMTnPR GPTMTnPR Count Up Mode Not available Not available Not available Not available When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down untilitreachesthexstate.alternatively,ifthetnwotbitissetinthegptmtnmrregister,once the TnEN bit is set, the timer waits for a trigger to begin counting(see Wait-for-Trigger Mode onpage78).onthenextcountercycleinperiodicmode,thecounterreloadsitsstartvalue from the GPTMTnILR and GPTMTnPR registers and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. The timer is capable of generating interrupts based onthreetypesofevents:risingedge,fallingedge,orboth.theeventisconfiguredbythetnevent fieldofthe GPTMCTLregister,andtheinterruptisenabledbysettingtheTnPWMIEbitinthe GPTMTnMRregister.Whentheeventoccurs,theCnERISbitissetinthe GPTMRaw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR)register,theGPTMalsosetstheCnEMISbitinthe GPTMMasked InterruptStatus (GPTMMIS) register. Note that the interrupt status bits are not updated unless the TnPWMIE bit is set. Inthismode,the GPTMTnRand GPTMTnVregistersalwayshavethesamevalue,asdothe GPTMPnPS and the GPTMTnPV registers. TheoutputPWMsignalassertswhenthecounterisatthevalueoftheGPTMTnILRandGPTMTnPR registers(its start state), and is deasserted when the counter value equals the value in the GPTMTnMATCHR and GPTMTnPMR registers. Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a positive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edgeofthepwmsignal. Figure-5onpage77showshowtogenerateanoutputPWMwitha-msperiodanda66%duty cycleassuminga5-mhzinputclockandtnpwml=(dutycyclewouldbe33%forthetnpwml = configuration). For this example, the start value is GPTMTnILR=xC35 and the match value is GPTMTnMATCHR=x4A. 76 June 2, 24

14 Tiva TM4C23GH6PMMicrocontroller Figure Bit PWM Mode Example xc35 Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR x4a Time TnEN set Output Signal TnPWML= TnPWML= When synchronizing the timers using the GPTMSYNC register, the timer must be properly configured toavoidglitchesontheccpoutputs.boththetnploandthetnmrsubitsmustbesetinthe GPTMTnMR register. Figure -6 on page 77 shows how the CCP output operates when the TnPLO and TnMRSU bits are set and the GPTMTnMATCHR value is greater than the GPTMTnILR value. Figure -6. CCP Output, GPTMTnMATCHR > GPTMTnILR GPTMnILR GPTMnMATCHR Counter CCP CCP set if GPTMnMATCHR GPTMnILR Figure-7onpage78showshowtheCCPoutputoperateswhenthePLOandMRSUbitsareset andthegptmtnmatchrvalueisthesameasthegptmtnilrvalue.inthissituation,iftheplo bitis,theccpsignalgoeshighwhenthe GPTMTnILRvalueisloadedandthematchwouldbe essentially ignored. June 2, 24 77

15 General-Purpose Timers Figure -7. CCP Output, GPTMTnMATCHR = GPTMTnILR GPTMnILR GPTMnMATCHR Counter CCP CCP not set if GPTMnMATCHR = GPTMnILR Figure-8onpage78showshowtheCCPoutputoperateswhenthePLOandMRSUbitsareset and the GPTMTnILR is greater than the GPTMTnMATCHR value. Figure -8. CCP Output, GPTMTnILR > GPTMTnMATCHR GPTMnILR GPTMnMATCHR = GPTMnILR- GPTMnMATCHR = GPTMnILR-2 GPTMnMATCHR == CCP CCP CCP PulsewidthisclockwhenGPTMnMATCHR=GPTMnILR- Pulsewidthis2clockswhenGPTMnMATCHR=GPTMnILR-2 Pulse width is GPTMnILR clocks when GPTMnMATCHR=.3.3 Wait-for-Trigger Mode The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured, a single timer can initiate multiple timing events using the Timer triggers. Wait-for-Trigger mode is enabledbysettingthetnwotbitinthegptmtnmrregister.whenthetnwotbitisset,timern+ doesnotbegincountinguntilthetimerinthepreviouspositioninthedaisychain(timern)reaches its time-out event. The daisy chain is configured such that GPTM always follows GPTM, GPTM2 followsgptm,andsoon.iftimeraisconfiguredasa32-bit(6/32-bitmode)or64-bit(32/64-bit wide mode) timer(controlled by the GPTMCFG field in the GPTMCFG register), it triggers Timer A inthenextmodule.iftimeraisconfiguredasa6-bit(6/32-bitmode)or32-bit(32/64-bitwide mode)timer,ittriggerstimerbinthesamemodule,andtimerbtriggerstimerainthenextmodule. CaremustbetakenthattheTAWOTbitisneversetinGPTM.Figure-9onpage79showshow the GPTMCFG bit affects the daisy chain. This function is valid for one-shot, periodic, and PWM modes. 78 June 2, 24

16 Tiva TM4C23GH6PMMicrocontroller Figure -9. Timer Daisy Chain GP Timer N+ GPTMTnMR.TnWOT Timer B Timer A Timer B ADC Trigger Timer A ADC Trigger GP Timer N GPTMTnMR.TnWOT Timer B Timer A Timer B ADC Trigger Timer A ADC Trigger.3.4 Synchronizing GP Timer Blocks The GPTM Synchronizer Control(GPTMSYNC) register in the GPTM block can be used to synchronize selected timers to begin counting at the same time. Setting a bit in the GPTMSYNC register causes the associated timer to perform the actions of a timeout event. An interrupt is not generated when the timers are synchronized. If a timer is being used in concatenated mode, only thebitfortimeramustbesetinthe GPTMSYNCregister. Note: Alltimersmustusethesameclocksourceforthisfeaturetoworkcorrectly. Table-onpage79showstheactionsforthetimeouteventperformedwhenthetimersare synchronized in the various timer modes. Table -. Timeout Actions for GPTM Modes Mode 32- and 64-bit One-Shot (concatenated timers) 32- and 64-bit Periodic (concatenated timers) 32-and64-bitRTC (concatenated timers) 6-and32-bitOneShot (individual/split timers) 6-and32-bitPeriodic (individual/split timers) 6-and32-bit Edge-Count (individual/split timers) 6-and32-bit Edge-Time (individual/split timers) 6-and32-bitPWM Count Dir Down Up Up Down Up Down Up Down Up Down Time Out Action N/A Countvalue=ILR Countvalue= Countvalue= N/A Countvalue=ILR Countvalue= Countvalue=ILR Countvalue= Countvalue=ILR Countvalue= Countvalue=ILR June 2, 24 79

17 General-Purpose Timers.3.5 DMA Operation ThetimerseachhaveadedicatedμDMAchannelandcanprovidearequestsignaltotheμDMA controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs. ThearbitrationsizeoftheμDMAtransfershouldbesettotheamountofdatathatshouldbe transferred whenever a timer event occurs. Forexample,totransfer256items,8itemsatatimeeveryms,configureatimertogeneratea periodictimeoutatms.configuretheμdmatransferforatotalof256items,withaburstsizeof 8items.Eachtimethetimertimesout,theμDMAcontrollertransfers8items,untilall256items have been transferred. No other special steps are needed to enable Timers for μdma operation. Refer to Micro Direct Memory Access(μDMA) on page 585 for more details about programming the μdma controller..3.6 Accessing Concatenated 6/32-Bit GPTM Register s TheGPTMisplacedintoconcatenatedmodebywritingaxoraxtotheGPTMCFGbitfieldin the GPTM Configuration(GPTMCFG) register. In both configurations, certain 6/32-bit GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: GPTM Timer A Interval Load(GPTMTAILR) register[5:], see page 756 GPTM Timer B Interval Load(GPTMTBILR) register[5:], see page 757 GPTMTimer A (GPTMTAR)register[5:],seepage764 GPTMTimer B (GPTMTBR)register[5:],seepage765 GPTMTimer A (GPTMTAV)register[5:],seepage766 GPTMTimer B (GPTMTBV)register[5:],seepage767 GPTM Timer A Match (GPTMTAMATCHR) register[5:], see page 758 GPTM Timer B Match (GPTMTBMATCHR) register[5:], see page 759 Inthe32-bitmodes,theGPTMtranslatesa32-bitwriteaccesstoGPTMTAILRintoawriteaccess to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[5:]:GPTMTAILR[5:] Likewise, a 32-bit read access to GPTMTAR returns the value: GPTMTBR[5:]:GPTMTAR[5:] A 32-bit read access to GPTMTAV returns the value: GPTMTBV[5:]:GPTMTAV[5:].3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register s On the 32/64-bit wide GPTM blocks, concatenated register values(64-bits and 48-bits) are not readilyavailableasthebitwidthfortheseaccessesisgreaterthanthebuswidthoftheprocessor core. In the concatenated timer modes and the individual timer modes when using the prescaler, software must perform atomic accesses for the value to be coherent. When reading timer values that are greater than 32 bits, software should follow these steps: 72 June 2, 24

18 Tiva TM4C23GH6PMMicrocontroller. Read the appropriate Timer B register or prescaler register. 2. Read the corresponding Timer A register. 3. Re-read the Timer B register or prescaler register. 4. ComparetheTimerBorprescalervaluesfromthefirstandsecondreads.Iftheyarethesame, thetimervalueiscoherent.iftheyarenotthesame,repeatsteps-4oncemoresothatthey are the same. The following pseudo code illustrates this process: high = timer_high; low = timer_low; if (high!= timer_high); //low overflowed into high { } high = timer_high; low = timer_low; Theregistersthatmustbereadinthismannerareshownbelow: 64-bit reads GPTMTAV and GPTMTBV GPTMTAR and GPTMTBR 48-bit reads GPTMTAR and GPTMTAPS GPTMTBR and GPTMTBPS GPTMTAV and GPTMTAPV GPTMTBV and GPTMTBPV Similarly, write accesses must also be performed by writing the upper bits prior to writing the lower bits as follows:. Write the appropriate Timer B register or prescaler register. 2. Write the corresponding Timer A register. Theregistersthatmustbewritteninthismannerareshownbelow: 64-bit writes GPTMTAV and GPTMTBV June 2, 24 72

19 General-Purpose Timers GPTMTAMATCHR and GPTMTBMATCHR GPTMTAILR and GPTMTBILR 48-bit writes GPTMTAV and GPTMTAPV GPTMTBV and GPTMTBPV GPTMTAMATCHR and GPTMTAPMR GPTMTBMATCHR and GPTMTBPMR GPTMTAILR and GPTMTAPR GPTMTBILR and GPTMTBPR Whenwritinga64-bitvalue,Iftherearetwoconsecutivewritestoanyoftheregisterslistedabove underthe"64-bitwrites"heading,whethertheregisterisintimeraortimerb,orifaregistertimer AiswrittenpriortowritingthecorrespondingregisterinTimerB,thenanerrorisreportedusingthe WUERISbitinthe GPTMRISregister.Thiserrorcanbepromotedtointerruptifitisnotmasked. Note that this error is not reported for the prescaler registers because use of the prescaler is optional. As a result, programmers must take care to follow the protocol outlined above..4 Initialization and Configuration TouseaGPTM,theappropriateTIMERnbitmustbesetinthe RCGCTIMERor RCGCWTIMER register(seepage338andpage357).ifusinganyccppins,theclocktotheappropriategpio modulemustbeenabledviathercgcgpioregister(seepage34).tofindoutwhichgpioport toenable,refertotable23-4onpage344.configurethepmcnfieldsinthegpiopctlregisterto assigntheccpsignalstotheappropriatepins(seepage688andtable23-5onpage35). This section shows module initialization and configuration examples for each of the supported timer modes..4. One-Shot/Periodic Timer Mode The GPTM is configured for One-Shot and Periodic modes by the following sequence:. Ensurethetimerisdisabled(theTnENbitinthe GPTMCTLregisteriscleared)beforemaking any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of x.. 3. Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR): a. WriteavalueofxforOne-Shotmode. b. Writeavalueofx2forPeriodicmode. 4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMR register to select whether to capture the value of the free-running timer at time-out, use an external trigger to start counting, configure an additional trigger or interrupt, and count up or down. 5. Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR). 722 June 2, 24

20 Tiva TM4C23GH6PMMicrocontroller 6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register (GPTMIMR). 7. SettheTnENbitinthe GPTMCTLregistertoenablethetimerandstartcounting. 8. Pollthe GPTMRISregisterorwaitfortheinterrupttobegenerated(ifenabled).Inbothcases, thestatusflagsareclearedbywritingatotheappropriatebitofthe GPTMInterruptClear Register (GPTMICR). IftheTnMIEbitinthe GPTMTnMRregisterisset,theRTCRISbitinthe GPTMRISregisterisset, and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads the timer and continues counting after the time-out event..4.2 Real-Time Clock (RTC) Mode TousetheRTCmode,thetimermusthavea KHzinputsignalonanevenCCPinput.To enable the RTC feature, follow these steps:. Ensurethetimerisdisabled(theTAENbitiscleared)beforemakinganychanges. 2. Ifthetimerhasbeenoperatinginadifferentmodepriortothis,clearanyresidualsetbitsinthe GPTM Timer n Mode (GPTMTnMR) register before reconfiguring. 3. Write the GPTM Configuration Register (GPTMCFG) with a value of x.. 4. Write the match value to the GPTM Timer n Match Register (GPTMTnMATCHR). 5. Set/clear the RTCEN and TnSTALL bit in the GPTM Control Register(GPTMCTL) as needed. 6. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register(GPTMIMR). 7. SettheTAENbitinthe GPTMCTLregistertoenablethetimerandstartcounting. When the timer count equals the value in the GPTMTnMATCHR register, the GPTM asserts the RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware reset.theinterruptisclearedbywritingthertccintbitinthe GPTMICRregister.Notethatifthe GPTMTnILRregisterisloadedwithanewvalue,thetimerbeginscountingatthisnewvalueand continues until it reaches xffff.ffff, at which point it rolls over..4.3 Input Edge-Count Mode A timer is configured to Input Edge-Count mode by the following sequence:. Ensurethetimerisdisabled(theTnENbitiscleared)beforemakinganychanges. 2. Write the GPTM Configuration(GPTMCFG) register with a value of x Inthe GPTMTimer Mode (GPTMTnMR)register,writetheTnCMRfieldtoxandtheTnMR field to x3. 4. Configurethetypeofevent(s)thatthetimercapturesbywritingtheTnEVENTfieldoftheGPTM Control(GPTMCTL) register. 5. Program registers according to count direction: June 2,

21 General-Purpose Timers In down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. Inup-countmode,thetimercountsfromxtothevalueinthe GPTMTnMATCHRand GPTMTnPMR registers. Note that when executing an up-count, the value of the GPTMTnPR and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR. 6. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. SettheTnENbitintheGPTMCTLregistertoenablethetimerandbeginwaitingforedgeevents. 8. PolltheCnMRISbitintheGPTMRISregisterorwaitfortheinterrupttobegenerated(ifenabled). Inbothcases,thestatusflagsareclearedbywritingatotheCnMCINTbitofthe GPTM Interrupt Clear (GPTMICR) register. When counting down in Input Edge-Count Mode, the timer stops after the programmed number of edgeeventshasbeendetected.tore-enablethetimer,ensurethatthetnenbitisclearedand repeat steps 4 through Input Edge Time Mode AtimerisconfiguredtoInputEdgeTimemodebythefollowingsequence:. Ensurethetimerisdisabled(theTnENbitiscleared)beforemakinganychanges. 2. Write the GPTM Configuration(GPTMCFG) register with a value of x Inthe GPTMTimer Mode (GPTMTnMR)register,writetheTnCMRfieldtoxandtheTnMR fieldtox3andselectacountdirectionbyprogrammingthetncdirbit. 4. ConfigurethetypeofeventthatthetimercapturesbywritingtheTnEVENTfieldofthe GPTM Control(GPTMCTL) register. 5. Ifaprescaleristobeused,writetheprescalevaluetothe GPTMTimer n Prescale Register (GPTMTnPR). 6. Load the timer start value into the GPTM Timer n Interval Load(GPTMTnILR) register. 7. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. SettheTnENbitintheGPTMControl(GPTMCTL)registertoenablethetimerandstartcounting. 9. PolltheCnERISbitintheGPTMRISregisterorwaitfortheinterrupttobegenerated(ifenabled). Inbothcases,thestatusflagsareclearedbywritingatotheCnECINTbitofthe GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timer n (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, butthetimerintervalcanbechangedatanytimebywritingthe GPTMTnILRregisterandclearing thetnildbitinthegptmtnmrregister.thechangetakeseffectatthenextcycleafterthewrite..4.5 PWM Mode A timer is configured to PWM mode using the following sequence: 724 June 2, 24

22 Tiva TM4C23GH6PMMicrocontroller. Ensurethetimerisdisabled(theTnENbitiscleared)beforemakinganychanges. 2. Write the GPTM Configuration(GPTMCFG) register with a value of x Inthe GPTMTimer Mode (GPTMTnMR)register,settheTnAMSbittox,theTnCMRbitto x,andthetnmrfieldtox2. 4. ConfiguretheoutputstateofthePWMsignal(whetherornotitisinverted)intheTnPWMLfield of the GPTM Control(GPTMCTL) register. 5. Ifaprescaleristobeused,writetheprescalevaluetothe GPTMTimer n Prescale Register (GPTMTnPR). 6. If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the GPTMCTL register and enable the interrupts by setting the TnPWMIE bit in the GPTMTnMR register. Note that edge detect interrupt behavior is reversed when the PWM output is inverted (see page 737). 7. Load the timer start value into the GPTM Timer n Interval Load(GPTMTnILR) register. 8. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value. 9. SettheTnENbitinthe GPTMControl(GPTMCTL)registertoenablethetimerandbegin generation of the output PWM signal. InPWMTimemode,thetimercontinuesrunningafterthePWMsignalhasbeengenerated.The PWMperiodcanbeadjustedatanytimebywritingtheGPTMTnILRregister,andthechangetakes effectatthenextcycleafterthewrite..5 Register Map Table -2 on page 726 lists the GPTM registers. The offset listed is a hexadecimal increment to the register's address, relative to that timer's base address: 6/32-bit Timer : x43. 6/32-bit Timer : x43. 6/32-bit Timer 2: x43.2 6/32-bit Timer 3: x43.3 6/32-bit Timer 4: x43.4 6/32-bit Timer 5: x /64-bit Wide Timer : x /64-bit Wide Timer : x /64-bit Wide Timer 2: x44.c 32/64-bit Wide Timer 3: x44.d 32/64-bit Wide Timer 4: x44.e 32/64-bit Wide Timer 5: x44.f The SIZE field in the GPTM Peripheral Properties(GPTMPP) register identifies whether a module has a 6/32-bit or 32/64-bit wide timer. NotethattheGPTimermoduleclockmustbeenabledbeforetheregisterscanbeprogrammed (seepage338orpage357).theremustbeadelayof3systemclocksafterthetimermoduleclock is enabled before any Timer module registers are accessed. June 2,

23 General-Purpose Timers Table -2. Timers Register Map Offset See page x GPTMCFG x. GPTM Configuration 727 x4 GPTMTAMR x. GPTMTimerAMode 729 x8 GPTMTBMR x. GPTMTimerBMode 733 xc GPTMCTL x. GPTM Control 737 x GPTMSYNC x. GPTM Synchronize 74 x8 GPTMIMR x. GPTM Interrupt Mask 745 xc GPTMRIS x. GPTM Raw Interrupt Status 748 x2 GPTMMIS x. GPTM Masked Interrupt Status 75 x24 GPTMICR WC x. GPTM Interrupt Clear 754 x28 GPTMTAILR xffff.ffff GPTM Timer A Interval Load 756 x2c GPTMTBILR - GPTM Timer B Interval Load 757 x3 GPTMTAMATCHR xffff.ffff GPTMTimerAMatch 758 x34 GPTMTBMATCHR - GPTMTimerBMatch 759 x38 GPTMTAPR x. GPTM Timer A Prescale 76 x3c GPTMTBPR x. GPTM Timer B Prescale 76 x4 GPTMTAPMR x. GPTM TimerA Prescale Match 762 x44 GPTMTBPMR x. GPTM TimerB Prescale Match 763 x48 GPTMTAR xffff.ffff GPTMTimerA 764 x4c GPTMTBR - GPTMTimerB 765 x5 GPTMTAV xffff.ffff GPTMTimerA 766 x54 GPTMTBV - GPTMTimerB 767 x58 GPTMRTCPD x.7fff GPTM RTC Predivide 768 x5c GPTMTAPS x. GPTM Timer A Prescale Snapshot 769 x6 GPTMTBPS x. GPTM Timer B Prescale Snapshot 77 x64 GPTMTAPV x. GPTM Timer A Prescale 77 x68 GPTMTBPV x. GPTM Timer B Prescale 772 xfc GPTMPP x. GPTM Peripheral Properties Register s The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. 726 June 2, 24

24 Tiva TM4C23GH6PMMicrocontroller Register : GPTM Configuration(GPTMCFG), offset x This register configures the global operation of the GPTM module. The value written to this register determineswhetherthegptmisin32-or64-bitmode(concatenatedtimers)orin6-or32-bit mode(individual, split timers). Important: BitsinthisregistershouldonlybechangedwhentheTAENandTBENbitsinthe GPTMCTL register are cleared. GPTM Configuration(GPTMCFG) 6/32-bit Timer base: x43. 6/32-bit Timer base: x43. 6/32-bit Timer 2 base: x43.2 6/32-bit Timer 3 base: x43.3 6/32-bit Timer 4 base: x43.4 6/32-bit Timer 5 base: x /64-bit Wide Timer base: x /64-bit Wide Timer base: x /64-bit Wide Timer 2 base: x44.c 32/64-bit Wide Timer 3 base: x44.d 32/64-bit Wide Timer 4 base: x44.e 32/64-bit Wide Timer 5 base: x44.f Offset x, reset x GPTMCFG 3:3 x. Softwareshouldnotrelyonthevalueofabit.Toprovide compatibility with future products, the value of a bit should be p across a read-modify-write operation. June 2,

25 General-Purpose Timers 2: GPTMCFG x GPTM Configuration The GPTMCFG values are defined as follows: x For a 6/32-bit timer, this value selects the 32-bit timer configuration. For a 32/64-bit wide timer, this value selects the 64-bit timer configuration. x For a 6/32-bit timer, this value selects the 32-bit real-time clock(rtc) counter configuration. For a 32/64-bit wide timer, this value selects the 64-bit real-time clock(rtc) counter configuration. x2-x3 Reserved x4 For a 6/32-bit timer, this value selects the 6-bit timer configuration. For a 32/64-bit wide timer, this value selects the 32-bit timer configuration. Thefunctioniscontrolledbybits:of GPTMTAMRand GPTMTBMR. x5-x7 Reserved 728 June 2, 24