HW D1: Gates & Flops: Spring 2015

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1 HW D1: Gates & Flops: Spring 15 1 Contents HW D1: Gates & Flops: Spring Apply a Regulator (6 pts, total) VariableRegulator(1 pt) Power Dissipation, efficiency(1 pt) HeatSinking(2 pts) Power Dissipation and Maximum Current without heat sink (1 pt) Power Dissipation with heat sink (1 pt) Effect of Overload (1 pt) Ripple(1pt) Numbers (2 points) 3 3 Implement this and that function (2 points) 3 4 Say it with VERILOG (PAL talk) (1 point) 4 5 ActiveLow(1 point) Whatfunction? Drawit ActiveLow s(2 points) Gates Verilog equivalent Flop Reminder: edge recorder (1 point) 6 8 A Versatile IC Gate (2 pts) An Example: AND with one input Banged The task: Make Other Functions (here is the task for which the 2 points areassigned) Counter Applications: Sync vs Async Function (3 points) Crummy: asyncclear(1 point) Good: fully synchronous divide-by-eleven (2 points, total) Timing Diagram of Synchronous vs Asynchronous Schemes (2 points) 11 Total points: 22 Due Monday, March 30, 2015 Reminder: Do take advantage of the worked examples in your notes. Often a HW question will resemble one of these, as probably you have noticed. 1 Apply a Regulator (6 pts, total) Just to get some practice. Here is a link to the 317 data sheet, which you ll probably need to consult Variable Regulator (1 pt) Show how to use an LM317 to produce an output that is adjustable between 5V and 10V. Assume the available input voltage is 15V, with 2V ripple down from that level.

2 HW D1: Gates & Flops: Spring Power Dissipation, efficiency (1 pt) Under maximum load (1.5A for an LM317 in a TO-220 package, like the one you met in lab), what power would the 317 dissipate worst case? What would its efficiency be, in that case? (Ignore ripple, here.) 1.3 Heat Sinking (2 pts) In these heat-sinking problems, assume that ambient temperature is 50 C. This may sound high, but remember that electronics usually operate in a box, alongside other electronics Power Dissipation and Maximum Current without heat sink (1 pt) You re not likely to use a regulator without heat sink. But if you did, how much current could could the LM317 safely deliver, with output voltages at worst case? Power Dissipation with heat sink (1 pt) What is the maximum current you could safely run in the 317, at V in =15V, if you use a heat sink with thermal resistance R ΘSA =5 C/W, along with an insulating gasket whose thermal resistance is 0.07 C/W. Maximum junction temperature for the 317 appears in the data sheet. See classnotes on voltage requlators, and a worked example on thermal resistance. You may ignore the ripple (which in fact would somewhat reduce power in the regulator). 1.4 Effect of Overload (1 pt) What happens if you exceed the max current you ve determined is permissible, in the preceding sub-question? It may help to recall what happened when you overloaded the 78L05 in the regulator lab. Here, we ll settle for a qualitative answer.

3 HW D1: Gates & Flops: Spring Ripple (1 pt) If you do all you can to minimize the effect of the input ripple of 2V (max), about what output ripple amplitude will your circuit show? (Consult data sheet, again.) sketchy summary 317 data sheet appears at end of this HW 2 Numbers (2 points) Write the decimal equivalents of the following binary numbers (even if you ve learned another algorithm for evaluating 2 s comp, try using the fact that the MSB carries its usual weight but is negative). (See Class Notes D1.) Number Decimal: --if Unsigned binary --if signed (2 s comp) binary Implement this and that function (2 points) Show how to use AND, OR and NOT gates to implement the following functions: Inputs: X 1 X 0 f 1 f 2 f 3 f

4 HW D1: Gates & Flops: Spring Say it with VERILOG (PAL talk) (1 point) Suppose inputs X 1 and X 0, in the preceding question, are assigned to two inputs of a PAL; each of the functions is assigned to a separate output pin, as stated below. Your task is just to write (with a pencil, not computer program!) the 3 equations in VERILOG s terms, for the 3 functions we have not done for you (we did the first). A reminder of the symbols Verilog uses to express logical operations appears in the comments for the file below. timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 13:14:56 01/10/2008 // Design Name: // Module Name: func1 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module func1(x1, x2, f1,f2,f3,f4); // here we list all the signals that go in and out of the thing we re designing input x1; //...then we say whether each is an INPUT or an OUTPUT (or both) input x2; output f1,f2,f3,f4; wire x1, x2; //...finally, we say what type of signal each is (wire vs reg vs net) wire f1,f2,f3,f4; // this is mysterious jargon that means, roughly, this thing doesn t remember assign f1 =!x1 &!x2; ; //...and here you write the Boolean equations: AND is & ("A & B"), OR is ("A B"), assign f2 = ; // XOR is ˆ ("A ˆ B"), NOT is! (as in "!A") assign f3= ; assign f4 = ; endmodule 5 ActiveLow(1 point) Note: this question is easy. Don t let all the talk here confuse you! Here are the symbol and truth table for a 3-input OR gate, as you know: truth table Figure 1: 3-input OR

5 HW D1: Gates & Flops: Spring 15 5 Inputs OUT Both the symbol and the name OR assume the convention that 1 is true, 0 is false. But what happens if you adopt the contrary assumption and many circuits make it convenient to make this change of assumptions: 5.1 What function? What function would this same piece of hardware perform for you, if you treated all inputs and outputs as active low? That is, what logical function of input LOW s (0 s) would this piece of hardware carry out? 5.2 Draw it Draw the same gate but choose the assertion level symbol appropriate when you assume the gate is taking in and putting out signals that are active low. See classnotes D1 if you re puzzled. 6 ActiveLow s (2 points) 6.1 Gates Draw gates (any number of inputs; use the shape that better expresses what s going on, from the two forms that demorgan teaches us always are available) to do the following: Given a 16-bit address bus (A0...A15) and the signals listed below, enable each of two memory chips as described: enable the ROM when RD* is asserted, and the memory location is in the bottom half of all address space; 1 enable the RAM when RD* or WR* is asserted and the memory location is between the bottom half and the top quarter (we ll reserve the top quarter for something else I/O and you need not wire that in this design). 1 If this notion, bottomhalf..., baffles you, please consult a handout on the subject of address decoding: 17S2. It is posted on the course website.

6 HW D1: Gates & Flops: Spring Verilog equivalent Figure 2: ROM, RAM enabling logic Note: we intend this question as just a paper-and-pencil warmup; soon enough, you will be compiling Verilog files (that task makes up most of a later homework). Show the equations for the two signals to enable ROM and RAM. We have written the start of the Verilog file for you. Notethat we have provided inverted signals for all that are active-low. Thus you can, if you like, write your equations in a pure, active-high world, by using these signal names (these signals are not brought out to any pin). For example assign ramen = rd is logically the same as assign ramen bar =!rd bar. Again we remind you of Verilog s way of indicating logic operations: AND = &; OR = ; XOR = ˆ ;NOT or BAR = or!. (For a single-bit variable,! and are equivalent. But their meanings differ.! is simple negation, and its result is True or False: for example,!(3 == 2) = True., in contrast, performs a bitwise negation: if the variable V has the binary value 101, then V = 010.) To specify a particular address line, 15, as part of a bus named addr, write addr[15]. ////////////////////////////////////////////////////////////////////////////////// module addr_decode_hw_mar10( input [15:0] addr, // this is a 16-line address "bus", A15...A0 input rd_bar, input wr_bar, output romen_bar, output ramen_bar ); // temporary signals, assigned to no pin, used to make every signal active high wire romen, ramen; // this specifies the sort of signal this is (keeps Verilog happy) // inputs assign rd =!rd_bar; assign wr =!wr_bar; //outputs assign romen_bar =!romen; assign ramen_bar =!ramen; assign assign endmodule 7 Flop Reminder: edge recorder (1 point) Design a circuit that lights an LED when a rising edge occurs on a signal named TRIG (you needn t generate that signal). The LED should stay lit till someone presses a pushbutton, asserting a signal named CLEAR*. The CLEAR* should be effective even if TRIG happens to stay high. Show wiring of the CLEAR* pushbutton.

7 HW D1: Gates & Flops: Spring A Versatile IC Gate (2 pts) In an era when large arrays of gates and computer logic synthesizers do much of the work that used to be logic design, it s reassuring to know that small-scale logic isn t entirely gone. One an buy a single gate in a small package (Fairchild calls its series, in packages of 5 to 8 pins, Tiny Logic ). Some curious pairings of gates also are available, such as the two-in OR feeding two-in AND described in AoE??. If you re using a single gate, you won t need to apply any of your intelligence. But it is refreshing to run into a gadget that does require some simple, old-fashioned back-of-the-envelope work. Such a gadget is the 4-gate array, 1G97, packaged in a 6-pin IC. If you need to implement a rather simple logic operation, the part can be handy, replacing several single-gate packages. Figure 3: Versatile IC universal logic gate Here, we invite you to try out this versatile IC, as a way to warm up your Boolean skills. 8.1 An Example: AND with one input Banged This is the sort of problem you may want to do with pencil and paper. It may help but also may not be necessary to write out combinations of inputs and intermediate signals, as well as the ultimate output. Let s try to apply the 1G97 to make an AND with a single active-low or banged input 2 (you may prefer to think of this as an inverted input). Here is a reminder of what we start with, and what we would like to implement: And here s a scribbled solution: Figure 4: The 1G97, and the logic we d like to use it to implement Figure 5: The 1G97 wired to implement AND with a single input active LOW 2 Bang is jargon for invert or make active-low.

8 HW D1: Gates & Flops: Spring The task: Make Other Functions (here is the task for which the 2 points are assigned) See how many other functions you can implement: we ll be happy with five. Draw the 1G97 wiring, and alongside that show the tidiest logic drawing you can provide (it will look simpler than the 1G97). A total of seven logic functions can be built with the 1G97 (including the one we showed in 8.1). All but one are single-gate equivalents. The one exception is the two-to-one multiplexer. (If you re not clear on what that is, take a look at a worked example on the topic of multiplexers: 14W1.)

9 HW D1: Gates & Flops: Spring Counter Applications: Sync vs Async Function (3 points) Use a 74HC161, a 4-bit binary up counter with synchronous load, asynchronous clear, to make a divide-byeleven counter in several ways: Note: CY is high if Count = (= 1111 in binary) and EN T is asserted; CY is low otherwise; the counter simply holds its present state if EN T is not asserted; Synchronous Load : Data (at the 4 D inputs) is loaded into the counter on the next rising edge of the clock if LD* is low (during setup time: the time just before the rise of the clock). 9.1 Crummy: async clear (1 point) Show how to use the asynchronous clear to make a crummy divide-by-eleven counter: By the way, what s so crummy about this design?

10 HW D1: Gates & Flops: Spring Good: fully synchronous divide-by-eleven (2 points, total) 1- Let the counter run up from state zero (1 point) 2- Use any states you like, taking advantage of the CarryOut function (1 point)

11 HW D1: Gates & Flops: Spring Timing Diagram of Synchronous vs Asynchronous Schemes (2 points) In the preceding question, you used both an asynchronous (crummy) method, and a fully-synchronous (classy) method. Your counters, in two cases, ran from zero up, and were to divide by 11. Use the timing diagrams below to show how the sync version is better than the async. Let your timing diagrams begin near the end of the cycle: at count 9, and show what happens in the next 4 clock periods.

12 HW D1: Gates & Flops: Spring Figure 6: LM317 Sketchy Data hwd1p mar wi data 15.tex; March 23, 2015

ENSC E-123: HW D3: Counter Applications; Counter in Verilog

HW D3; Counter Applications 1 ENSC E-123: HW D3: Counter Applications; Counter in Verilog REV 0 1 ; February 12, 2015 Contents 1 Counter Applications: Sync vs Async Function (5 points) 2 1.1 Crummy: asyncclear(2points).................