COMP12111 Fundamentals of Computer Engineering Paul Nutter Vasilis Pavlidis Comments
|
|
- Sherman Paul
- 5 years ago
- Views:
Transcription
1 Fundamentals of Computer Engineering Paul Nutter Vasilis Pavlidis Comments Please see the attached report. 12 February 2016 Page 2 of 7
2 Exam Feedback 2015/16 Q1 set by Paul Nutter Q2 set by Vasilis Pavlidis Q3 set by Paul Nutter Q4 set by Vasilis Pavlidis Overall exam average approx. 55%. Q1 Section A Q1 and Q2 are compulsory. A compulsory question marked out of 10, where there is some choice and students can answer 5 parts out of 8. A number of students choose to answer more than 5 questions, sometimes all 8, in this section. Whilst I am often generous and take the best five marks, attempting more than is required is somewhat of a waste of time. Time is better at answering questions that will contribute to final mark, rather attempting to maximise just a few marks. a) The aim of this question was to fully specify the values in the required format, by specifying the number of bits and the base of the number. ½ mark for each question. i) you are required to specify the 8-bit binary equivalent of +25, i.e. 8`b ii) 16`d65 (although I did allow a binary representation) iii) 16 hffee iv) 8`h119 In a number of cases the number of bits was left out, the base was not specified, or the value was not specified in the required format. In part iii) the two s complement negative value, FFEE, was not always specified, instead a negative value was quoted. b) The aim of this question was for you to discuss the difference, in terms of the format of the sensitivity list, between an always block containing blocking or non-blocking assignments. In the case of a block containing blocking assignments the sensitivity list would contain either all the inputs that cause a variable (or variables) in the block to be re-evaluated, or in more generally *. In the case of a block containing non-blocking assignments, then we have a sequential block, so the sensitivity list contains some timing dependency, such as posedge, or negedge clock. 1 mark for discussing each. Page 1 of 12
3 A number of answers focused on discussing the difference between the way blocking and non-blocking assignments are evaluated the question was not asking this! In some cases the discussion focused on discussing only one case, i.e. that in the case of nonblocking the sensitivity list contains some dependency on the edge of a clock signal, i.e. posedge clock (which is correct) but then preceded to say that in the case of blocking it doesn t! Some answers discussed blocking as representing an asynchronous circuit! c) The aim of this question was to spot the errors in the Verilog module provided. The errors include: Module name starting with a number tricky but a few spotted this! Output Q not defined as a reg blocking statements are used6 Sensitivity list should use * and not posedge S Missing endmodule On reflection I also allowed missing begin as a error, although strictly speaking a begin and end is not required. In a number of cases only 2 errors were reported, I suspect this was because the question is worth 2 marks, rather than they could only find 2 errors. In fact there were 4 errors - ½ mark each! Some random errors were identified, such as: The number of bits is not specified for input S why? The inputs need to be declared as reg why? The assignments should be non-blocking as there is a posedge in the sensitivity list you are told that the block is combinatorial! d) This was a relatively well answered question. 1 mark was awarded for some evidence of DeMorgan s theorem being used, 1 mark for a correct answer. Working out and not Q! Not providing a product of sums expression as requested. e) The aim of this question was to test your understanding of the operation of a D-type flip-flop; in this case with a CE input which you have come across in the lab. The question sort of gave the answer away by defining CE clock enable - which simply enables the clock and controls on which clock edge the flip-flop is loaded 1 mark for a suitable description. You were also asked to produce a sketch of a timing waveform to show how it works 1 mark for a sketch. Page 2 of 12
4 Not adequately describing the operation of CE there were a lot of answers that failed to even mention clock in the discussion! Waveform sketches that do not include all the required signals (in particular CE and clock!). f) The aim of this question is to test your ability to produce an exhaustive test stimulus for the given design, this involves testing all possible combinations of the input signals, D0, d1 and s. The stimulus should be implemented as an initial block with structure: initial begin d0 = 0; d1 = 0; s = 0; // set inputs #10 // add delay // do rest $stop end Testing all possible input combinations 1 mark, initial, begin, $stop and end - ½ mark, using sensible delays after setting inputs ½ mark. Creating a clock where is a clock used in the design? Not producing a test stimulus that is exhaustive the question does ask for this! Missing out the initial, begin end, and $stop. g) The aim of this question is to test you ability to extract a Boolean expression from a truth table and then translate this to a circuit schematic. 1 mark for the Boolean expression, 1 mark for an appropriate circuit diagram. Note, the Boolean expression can be simplified if the non-simplified expression is given then only ½ mark was awarded. On the whole the extraction of a Boolean expression was handled well. However, it was clear some did not know how to do this! When it came to drawing the circuit diagram, it was clear that some hadn t read the question! You are told that standard gates are available AND, OR and NOT, yet still some logic gates were drawn with bubbles at the input to represent inversion you don t have such a gate available! Page 3 of 12
5 h) This was a wordy question and involved discussing the operation of the datapath and control blocks in a sequential system bookwork. 1 mark for an adequate discussion of both. It was surprising how many answers failed to discuss the operation (as requested) and simply drew a diagram with no discussion! Not identifying the interplay between control and datapath, i.e. the control tells the datapath what to do with the data. Not recognising that the control consists of a FSM. Page 4 of 12
6 Q2 A compulsory question marked out of 10. Answer 5 parts out of 8. The majority of students attempted this question even if they attempted only fewer parts or in very few cases more than five parts although they should not have done so. a) Standard lecture material related question. It was attempted by most of the students and the majority got it right. One mark was awarded for the right order and another one for the correct mapping of the memory hierarchy levels to memory technologies. Half marks were given for partially corrected answers. Some answers did not provide a clear relationship of proximity. Indicating the CPU, either with text or drawing boxes as many students did would help to remove any confusion. Several answers showed that the traits of the memory technologies were not understood although these were explained in lecture notes and were extensively discussed in lectures. b) This question was also quite popular. It only meant to check the understanding of the concepts of critical path delay, clock frequency, and the link between them. One mark was given for each part of the question. Accuracy in the numbers was not so important unless they were far off but units were important and marks were lost for such errors. Many answers reported unreasonable numbers. Frequencies in phz(!) were reported. Other answers gave the frequency in seconds(!) which shows clear lack of understanding. No marks were given for such results even if arithmetic was right. Some flexibility for answers that reported MHz instead of GHz was shown depending on the quality of the solution. c) Another popular question but not so well answered. One mark was given for a reasonable definition of the timer and another mark was given for a logical description of its operation. Standard textbook question that did not require much thinking. Many seem to confuse the timer with the clock signal of the processor, for example, while it was emphasized that this is not the case. Other answers stated that it is not the clock but did not describe what the timer is. Several incorrect answers which had nothing to do with the operation of a timer. Page 5 of 12
7 d) About half of the class attempted this part. One mark was given for answering the DMA (and spelling it out) and another mark for giving the benefit (and overhead) of this peripheral. Some answers referred to caching, a topic not discussed in class and not included in the syllabus for this course as well. Some answers mentioned registers. It is not clear how these answers relate to the question since the CPU will still be making the transfers. Some answers mentioned only the name of the mechanism but did not describe the benefit/overhead of it. e) Several attempted this part. Two full marks were given for the correct truth table, one mark for partially correct and no marks for largely erroneous answers. A similar example has been demonstrated in the last revision class. Most of the answers wrote down the entire truth table (16 cases) wasting time, the smart use of don t cares (X) would have reduced the table to only 5 rows! Some answers failed to consider that the INT signal is described as active low in the instructions and gave inverted answers. One mark was taken off for that if the rest of the thinking was correct. f) Many attempted this answer. Although the initial intent was to answer the arithmetic operation of multiplication/division along with an appropriate arithmetic example, several answers referred to SER/DES and more specifically to the example of UART and drew its operation. This answer was also considered equally correct. One mark was given for describing the operation and another mark for a proper example. Several answered that shift registers do shifting! This is rather obvious and definitely not the sought answer. Some gave an example with decimal numbers which was incorrect, since shift registers operate with binary numbers. Other answers mentioned multiplication and provided as an example the full algorithm of full and long multiplication. This is exactly what we want to avoid with shift registers, so that this is not an appropriate example. Page 6 of 12
8 g) This part was also relatively popular. Most of the students have studied this in depth. One mark was given for giving the correct number and name of USB signals and some discussion and another mark for describing the principle of bit stuffing. If the exact number of bits was not given, marks were not taken off as long as the use of bit stuffing was correctly described. Nothing significant as no great misunderstandings or confusion about this answer was noticed. Some made random guesses about bit stuffing but these were faulty. Few confused the USB protocol with memory! h) This question required some critical thinking and it was not just about recalling textbook material. Sadly few attempted it. The idea was to think inversely as compared to the example given to speed up MU0 by adding the register DIN. Some students got this exactly right, however, and gave nice explanations. I would like to thank them for that. Page 7 of 12
9 Section B Answer one question from Q3 and Q4. Q3 was by far the most popular question in this section with almost everyone answering it. Q3 A popular question - almost everyone attempted it with mixed success. Overall, a decent attempt though around 54% overall. However, there were a number of very poor answers. The question tested your understanding of the operation and design of finite state machines, and how to translate designs into Verilog, which is something you have ALL had experience of doing in the lab. Consequently, I would have felt it would have been a relatively straightforward question to answer. How wrong I was a) Part a) required you to identify the errors in a state transition diagram. There were six in total: Boolean conditions out of state_0 are not all satisfied No Boolean conditions for the transitions out of state_1 Hung state_2 how do you get out? state_2 and state_4 have the same state code Boolean conditions out of state_4 are not all satisfied state_6 invalid state code it should be 3 bits Only giving 3 errors yes, there were 3 marks available, but that doesn t mean there are 3 errors! The state code for state_6 is NOT the same as state_1 Reset comes from nowhere as a squiggly line into state_0 what? This illustrates an asynchronous reset we have covered this in lectures. The state codes are not in numerical increasing order they don t have to be! When have I said this? In fact, example are given in lectures where the state codes are randomly assigned, which is perfectly fine. Generally however, the initial state should be given a 0 state vector, i.e No condition for z=1 for state_6 it s not shown for simplicity. If a condition is not shown, then it implies you stay in the state for that condition again covered in lectures. My favourite incorrect mistake was conflicting conditions for leaving state_3 since DeMorgan s theorem states a.b = someone needs to refresh their understanding of DeMorgan s theorem! Page 8 of 12
10 b) You are required to discuss the operation of the three functional blocks in the implementation of the FSM, i.e. A mark was awarded for a suitable discussion for each, i.e. A combinatorial block of logic that determines the next state from the current state and any inputs A sequential block that assigns the value of next state to the current state at each rising edge of the clock A combinatorial logic block that determines any outputs from the current state. I was actually quite generous with this question and awarded marks based on the production of a correct diagram (as shown above), without an accompanying discussion. Not mentioning combinatorial or sequential Not being clear what output is produced and for what input(s) for each block Complete random discussions for example, a functional block implementing reset what? c) This proved an interesting question. You were simply required to translate the working state transition diagram into a state transition table (3 marks), and assign state codes to each state (1 mark). A suitable state transition table is given below. I didn t drop marks if a default row wasn t given. Page 9 of 12
11 Current State Inputs Next State Outputs A B C 10p 20p A B C ready reject dispense x x x x default x x Not listing transitions for conditions where 10p = 0 and 20p = 0 in the 0p_state, 10p_state, and 20p_state states. Showing reset in the table when have we shown this? Giving a non-standard state transition table random, made-up tables. Setting outputs to don t cares I stressed in lectures that outputs should always be set to a value, 0 or 1. Redrawing the state transition diagram simply to annotate the state codes why waste time? Setting the outputs for the next state rather than the current state. d) This involved taking the design from part c) and translating it into a Verilog implementation. The question actually tells you to implement this as three functional blocks (see part b) ), which implies three always blocks. The question does not require you to define the module, just to produce the three always blocks. Marks were awarded as follows: Next state logic 4 marks o 1 mark for a sensitivity list with *, or all inputs listed o 1 mark for the use of blocking statements o 1 mark for a default a case statement is the best implementation approach (here default should default to state 000) o 1 mark for being functionally correct when defining the next state value Current state assignment 3 marks o 1 mark for the correct sensitivity list posedge clk and posedge reset o ½ mark for a correct reset action Page 10 of 12
12 o ½ mark for a correct current state assignment o 1 mark for the use of non-blocking assignments Output assignment 3 marks o 1 mark for correct sensitivity list with *, or current state o 1 mark for blocking assignments o 1 mark for outputs being functionally correct Not providing the answer as three blocks as instructed. There were quite a lot of answers where an attempt was made to merge the two or more blocks in a single always block. This is perfectly fine, with experience, however, you have NEVER been shown how to do this, so why do it? This often results in state changes and outputs being out of sync. Marks were often lost as a result! Using nested if else statements, invariably with dangling elses, rather than a case statement. What s a break in a case statement? Having a synchronous reset action by not having a timing dependency on reset in the sensitivity list for the current state assignment. Having no idea what the difference is between blocking and non-blocking assignments and when it is appropriate to use them! Only setting outputs to 1, never setting them to 0. In a combinatorial block you should set ALL outputs to a value for ALL cases. General poor, incomprehensible, made-up Verilog code Page 11 of 12
13 Q4 Unfortunately, only a few students attempted this question, which was a bit disappointing as the first two parts were explained thoroughly in regular and revision lectures, the third was closely related to one practical exercise in the lab, and only the last part required some critical thinking based on the material taught in the module. Marked out of 20. a) A standard questions where several examples were given in the class. Most of the answers determined right the number of chips but the majority couldn t remember how a decoder works and provided the drawing of a MUX, which was not correct. Note a separate CS (chip select) signal is needed for each chip! b) The majority of the students who attempted this part got it fully or partially right, where the examples in the class helped a lot to understand the timing of MU0. Thank you! One part of the question was asking to provide the mnemonic of the instructions and then to fill out the table. This intended to help the students who could determine the instructions but not the timing to receive some marks. Some answers ignored this part and directly filled out the table. In principle, they should have not done so. Only one mark, however, was taken off form the overall question as long as the table was correctly filled in. c) Most of the students who tried this part got it right as it was based on the lab exercises. The schematics were mostly correctly drawn and the faulty connection was detected. d) Only a couple of students managed to solve this correctly. The idea was to recursively apply the given formulas to determine the Boolean expression for the carry out and then draw a circuit diagram. Adding up the delay of the gates on the longest path would yield the required answer. However, no path delay was determined correctly, the terms G and P add some delay to the drawn circuit diagram. This delay could have been readily determined as the logical expressions for each of these terms was given (involved only one gate) and the delay of these gates was given in the instructions. Page 12 of 12
One and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE
One and a half hours Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Fundamentals of Computer Engineering Date: Thursday 21st January 2016 Time: 14:00-15:30 Answer BOTH Questions
More informationOne and a half hours. Section A is COMPULSORY
One and a half hours Section A is COMPULSORY An additional answersheet is provided for Question 4. Please remember to complete the additional answersheet with your University ID number and attach it to
More informationOne and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE
COMP 12111 One and a half hours Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Fundamentals of Computer Engineering Date: Monday 23rd January 2017 Time: 09:45-11:15 Answer
More information(Refer Slide Time 3:31)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 5 Logic Simplification In the last lecture we talked about logic functions
More information(Refer Slide Time 6:48)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 8 Karnaugh Map Minimization using Maxterms We have been taking about
More informationECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
More informationRecommended Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto
Recommed Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto DISCLAIMER: The information contained in this document does NOT contain
More informationSynthesizable Verilog
Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
More information2015 Paper E2.1: Digital Electronics II
s 2015 Paper E2.1: Digital Electronics II Answer ALL questions. There are THREE questions on the paper. Question ONE counts for 40% of the marks, other questions 30% Time allowed: 2 hours (Not to be removed
More informationENCM 369 Winter 2019 Lab 6 for the Week of February 25
page of ENCM 369 Winter 29 Lab 6 for the Week of February 25 Steve Norman Department of Electrical & Computer Engineering University of Calgary February 29 Lab instructions and other documents for ENCM
More informationSequential Logic Design
Sequential Logic Design Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted
More informationEngin 100 (section 250), Winter 2015, Technical Lecture 3 Page 1 of 5. Use pencil!
Engin 100 (section 250), Winter 2015, Technical Lecture 3 Page 1 of 5 Use pencil! Last time Introduced basic logic and some terms including bus, word, register and combinational logic. Talked about schematic
More informationEPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
More informationStudents received individual feedback throughout year on assignments.
ACS108 No exam. Students received individual feedback throughout year on assignments. ACS123 In general, during ACS123 exam session, students have shown satisfactory performance, clear understanding of
More information1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]
HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you
More informationOutline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?
Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Eamination ECE 4F - Digital Systems Eaminers: S. Brown, J.
More informationFinite-State Machine (FSM) Design
1 Finite-State Machine (FSM) Design FSMs, an important category of sequential circuits, are used frequently in designing digital systems. From the daily used electronic machines to the complex digital
More informationCARLETON UNIVERSITY. Laboratory 2.0
CARLETON UNIVERSITY Department of Electronics ELEC 267 Switching Circuits Jan 3, 28 Overview Laboratory 2. A 3-Bit Binary Sign-Extended Adder/Subtracter A binary adder sums two binary numbers for example
More informationControl and Datapath 8
Control and Datapath 8 Engineering attempts to develop design methods that break a problem up into separate steps to simplify the design and increase the likelihood of a correct solution. Digital system
More informationEECS150 - Digital Design Lecture 20 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited April 2, 2009 John Wawrzynek Spring 2009 EECS150 - Lec20-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationECE 2300 Digital Logic & Computer Organization. More Finite State Machines
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Finite State Machines Lecture 9: 1 Announcements Prelab 3(B) due tomorrow Lab 4 to be released tonight You re not required to change partner(s)
More informationSpring 2013 EE201L Instructor: Gandhi Puvvada. Time: 7:30-10:20AM SGM124 Total points: Perfect score: Open-Book Open-Notes Exam
Spring 2013 EE201L Instructor: Gandhi Puvvada Final Exam 2 (25%) Date: May 9, 2013, Thursday Name: Open-Book Open-Notes Exam Time: 7:30-10:20AM SGM124 Total points: Perfect score: 1 ( points) min. Memory
More informationChapter 4 :: Topics. Introduction. SystemVerilog. Hardware description language (HDL): allows designer to specify logic function only.
Chapter 4 :: Hardware Description Languages Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Chapter 4 :: Topics Introduction Combinational Logic Structural Modeling Sequential
More informationstructure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationHere is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Introductory Digital Systems Lab (6.111) uiz - Spring 2004 Prof. Anantha Chandrakasan Student Name: Problem
More informationCS 61C Summer 2012 Discussion 11 State, Timing, and CPU (Solutions)
State Elements State elements provide a means of storing values, and controlling the flow of information in the circuit. The most basic state element (we re concerned with) is a DQ Flip-Flop: D is a single
More informationARM 64-bit Register File
ARM 64-bit Register File Introduction: In this class we will develop and simulate a simple, pipelined ARM microprocessor. Labs #1 & #2 build some basic components of the processor, then labs #3 and #4
More informationRegister Transfer Level
Register Transfer Level Something between the logic level and the architecture level A convenient way to describe synchronous sequential systems State diagrams for pros Hierarchy of Designs The design
More informationFPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]
FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed
More informationDigital Systems Design with PLDs and FPGAs Kuruvilla Varghese Department of Electronic Systems Engineering Indian Institute of Science Bangalore
Digital Systems Design with PLDs and FPGAs Kuruvilla Varghese Department of Electronic Systems Engineering Indian Institute of Science Bangalore Lecture-32 Simple PLDs So welcome to just lecture on programmable
More informationUNIVERSITY OF MALTA THE MATRICULATION EXAMINATION ADVANCED LEVEL. COMPUTING May 2016 EXAMINERS REPORT
UNIVERSITY OF MALTA THE MATRICULATION EXAMINATION ADVANCED LEVEL COMPUTING May 2016 EXAMINERS REPORT MATRICULATION AND SECONDARY EDUCATION CERTIFICATE EXAMINATIONS BOARD Computing Advanced Level May 2016
More information(Refer Slide Time: 00:01:53)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 36 Design of Circuits using MSI Sequential Blocks (Refer Slide Time:
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationEECS150 - Digital Design Lecture 4 - Verilog Introduction. Outline
EECS150 - Digital Design Lecture 4 - Verilog Introduction Feb 3, 2009 John Wawrzynek Spring 2009 EECS150 - Lec05-Verilog Page 1 Outline Background and History of Hardware Description Brief Introduction
More informationSlide Set 5. for ENCM 369 Winter 2014 Lecture Section 01. Steve Norman, PhD, PEng
Slide Set 5 for ENCM 369 Winter 2014 Lecture Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Winter Term, 2014 ENCM 369 W14 Section
More informationEECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15
1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,
More informationContinuing with whatever we saw in the previous lectures, we are going to discuss or continue to discuss the hardwired logic design.
Computer Organization Part I Prof. S. Raman Department of Computer Science & Engineering Indian Institute of Technology Lecture 10 Controller Design: Micro programmed and hard wired (contd) Continuing
More informationEE 231 Fall EE 231 Homework 8 Due October 20, 2010
EE 231 Homework 8 Due October 20, 20 1. Consider the circuit below. It has three inputs (x and clock), and one output (z). At reset, the circuit starts with the outputs of all flip-flops at 0. x z J Q
More informationLecture 32: SystemVerilog
Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:
More information2. You are required to enter a password of up to 100 characters. The characters must be lower ASCII, printing characters.
BLACK BOX SOFTWARE TESTING SPRING 2005 DOMAIN TESTING LAB PROJECT -- GRADING NOTES For all of the cases below, do the traditional equivalence class and boundary analysis. Draw one table and use a new line
More informationQuick Introduction to SystemVerilog: Sequental Logic
! Quick Introduction to SystemVerilog: Sequental Logic Lecture L3 8-545 Advanced Digital Design ECE Department Many elements Don Thomas, 24, used with permission with credit to G. Larson Today Quick synopsis
More informationTwo hours - online EXAM PAPER MUST NOT BE REMOVED FROM THE EXAM ROOM UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE
COMP 12111 Two hours - online This paper version is made available as a backup In this event, only MCQ answers written in the boxes on the exam paper will be marked. EXAM PAPER MUST NOT BE REMOVED FROM
More informationDigital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University
Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register
More information(Refer Slide Time 5:19)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 7 Logic Minimization using Karnaugh Maps In the last lecture we introduced
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 11. Introduction to Verilog II Sequential Circuits
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 11 Introduction to Verilog II Sequential Circuits OBJECTIVES: To understand the concepts
More informationproblem maximum score 1 8pts 2 6pts 3 10pts 4 15pts 5 12pts 6 10pts 7 24pts 8 16pts 9 19pts Total 120pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2010 3/31/09 Name: ID number: Midterm Exam This is a closed-book,
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationScheme G. Sample Test Paper-I
Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable
More informationAbstraction of State Elements. Sequential Logic Implementation. Forms of Sequential Logic. Finite State Machine Representations
Sequential ogic Implementation! Models for representing sequential circuits " Finite-state machines (Moore and Mealy) " epresentation of memory (states) " hanges in state (transitions)! Design procedure
More informationCS 250 VLSI Design Lecture 11 Design Verification
CS 250 VLSI Design Lecture 11 Design Verification 2012-9-27 John Wawrzynek Jonathan Bachrach Krste Asanović John Lazzaro TA: Rimas Avizienis www-inst.eecs.berkeley.edu/~cs250/ IBM Power 4 174 Million Transistors
More informationChapter 5 Registers & Counters
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 5 Registers & Counters Originals by: Charles R. Kime Modified for course
More informationHomework deadline extended to next friday
Norm Midterm Grading Finished Stats on course homepage Pickup after this lab lec. Regrade requests within 1wk of posted solution Homework deadline extended to next friday Description Design Conception
More informationECE 550D Fundamentals of Computer Systems and Engineering. Fall 2017
ECE 550D Fundamentals of Computer Systems and Engineering Fall 2017 Combinational Logic Prof. John Board Duke University Slides are derived from work by Profs. Tyler Bletsch and Andrew Hilton (Duke) Last
More informationIn this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.
1 In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. I will also introduce the idea of a testbench as part of a design specification.
More informationGraduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:
Design of Datapath Controllers and Sequential Logic Lecturer: Date: 2009.03.18 ACCESS IC LAB Sequential Circuit Model & Timing Parameters ACCESS IC LAB Combinational Logic Review Combinational logic circuits
More informationStarting Boolean Algebra
Boolean Algebra March 2, 27 Diagram for FunChip2 Here is a picture of FunChip2 that we created more or less randomly in class on /25 (used in various Activities): Starting Boolean Algebra Boolean algebra
More informationDigital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur.
Digital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur Lecture 05 DFT Next we will look into the topic design for testability,
More informationChapter 2.6: Testing and running a solution
Chapter 2.6: Testing and running a solution 2.6 (a) Types of Programming Errors When programs are being written it is not surprising that mistakes are made, after all they are very complicated. There are
More informationThe Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science
The Verilog Language COMS W4995-02 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient event-driven
More informationEECS 140 Laboratory Exercise 5 Prime Number Recognition
1. Objectives EECS 140 Laboratory Exercise 5 Prime Number Recognition A. Become familiar with a design process B. Practice designing, building, and testing a simple combinational circuit 2. Discussion
More informationIn this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and
In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and shift registers, which is most useful in conversion between
More informationEECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
More informationLast Lecture. Talked about combinational logic always statements. e.g., module ex2(input logic a, b, c, output logic f); logic t; // internal signal
Last Lecture Talked about combinational logic always statements. e.g., module ex2(input logic a, b, c, output logic f); logic t; // internal signal always_comb t = a & b; f = t c; should use = (called
More informationa, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign
I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify
More informationENCM 369 Winter 2015 Lab 6 for the Week of March 2
page of 2 ENCM 369 Winter 25 Lab 6 for the Week of March 2 Steve Norman Department of Electrical & Computer Engineering University of Calgary February 25 Lab instructions and other documents for ENCM 369
More informationProgramming with HDLs
Programming with HDLs Paul Chow February 11, 2008 1 Introduction The purpose of this document is to encourage the proper approach or mindset for programming in a hardware description language (HDL), particularly
More informationChapter 10. case studies in sequential logic design
Chapter. case studies in sequential logic design This is the last chapter of this course. So far, we have designed several sequential systems. What is the general procedure? The most difficult part would
More informationNikhil Gupta. FPGA Challenge Takneek 2012
Nikhil Gupta FPGA Challenge Takneek 2012 RECAP FPGA Field Programmable Gate Array Matrix of logic gates Can be configured in any way by the user Codes for FPGA are executed in parallel Configured using
More informationEECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
More informationEECS 270 Midterm Exam
EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4
More informationRegister Transfer Level in Verilog: Part I
Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part I Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National
More informationEECS 373 Practice Midterm / Homework #3 Fall 2014
Exam #: EECS 373 Practice Midterm / Homework #3 Fall 2014 Name: Uniquename: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Problem #
More informationENCM 369 Winter 2018 Lab 9 for the Week of March 19
page 1 of 9 ENCM 369 Winter 2018 Lab 9 for the Week of March 19 Steve Norman Department of Electrical & Computer Engineering University of Calgary March 2018 Lab instructions and other documents for ENCM
More informationDigital Integrated Circuits
Digital Integrated Circuits Lecture 4 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University BCD TO EXCESS-3 CODE CONVERTER 0100 0101 +0011 +0011 0111 1000 LSB received first Chung
More informationMemory Supplement for Section 3.6 of the textbook
The most basic -bit memory is the SR-latch with consists of two cross-coupled NOR gates. R Recall the NOR gate truth table: A S B (A + B) The S stands for Set to remember, and the R for Reset to remember.
More informationPlease write your name and username here legibly: C212/A592 6W2 Summer 2017 Early Evaluation Exam: Fundamental Programming Structures in Java
Please write your name and username here legibly: C212/A592 6W2 Summer 2017 Early Evaluation Exam: Fundamental Programming Structures in Java Use BigDecimal (a class defined in package java.math) to write
More informationVerilog Behavioral Modeling
Verilog Behavioral Modeling Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:
More informationMusic. Numbers correspond to course weeks EULA ESE150 Spring click OK Based on slides DeHon 1. !
MIC Lecture #7 Digital Logic Music 1 Numbers correspond to course weeks sample EULA D/A 10101001101 click OK Based on slides 2009--2018 speaker MP Player / iphone / Droid DeHon 1 2 A/D domain conversion
More informationEE178 Spring 2018 Lecture Module 4. Eric Crabill
EE178 Spring 2018 Lecture Module 4 Eric Crabill Goals Implementation tradeoffs Design variables: throughput, latency, area Pipelining for throughput Retiming for throughput and latency Interleaving for
More information(Refer Slide Time: 2:20)
Data Communications Prof. A. Pal Department of Computer Science & Engineering Indian Institute of Technology, Kharagpur Lecture-15 Error Detection and Correction Hello viewers welcome to today s lecture
More informationWriting Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationCSCB58 - Lab 3. Prelab /3 Part I (in-lab) /2 Part II (in-lab) /2 TOTAL /8
CSCB58 - Lab 3 Latches, Flip-flops, and Registers Learning Objectives The purpose of this exercise is to investigate the fundamental synchronous logic elements: latches, flip-flops, and registers. Prelab
More informationIntro. Scheme Basics. scm> 5 5. scm>
Intro Let s take some time to talk about LISP. It stands for LISt Processing a way of coding using only lists! It sounds pretty radical, and it is. There are lots of cool things to know about LISP; if
More informationENGR 3410: MP #1 MIPS 32-bit Register File
ENGR 3410: MP #1 MIPS 32-bit Register File Due: Before class, September 23rd, 2008 1 Introduction The purpose of this machine problem is to create the first large component of our MIPS-style microprocessor
More information6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )
6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate logical values from place to place.
More informationEN2911X: Reconfigurable Computing Lecture 05: Verilog (2)
EN2911X: Lecture 05: Verilog (2) Prof. Sherief Reda Division of Engineering, Brown University Fall 09 http://scale.engin.brown.edu Dataflow modeling Module is designed by specifying the data flow, where
More informationENSC E-123: HW D3: Counter Applications; Counter in Verilog
HW D3; Counter Applications 1 ENSC E-123: HW D3: Counter Applications; Counter in Verilog REV 0 1 ; February 12, 2015 Contents 1 Counter Applications: Sync vs Async Function (5 points) 2 1.1 Crummy: asyncclear(2points).................
More informationLAB #3: ADDERS and COMPARATORS using 3 types of Verilog Modeling
LAB #3: ADDERS and COMPARATORS using 3 types of Verilog Modeling LAB OBJECTIVES 1. Practice designing more combinational logic circuits 2. More experience with equations and the use of K-maps and Boolean
More informationDesign of Digital Circuits ( L) ETH Zürich, Spring 2017
Name: Student ID: Final Examination Design of Digital Circuits (252-0028-00L) ETH Zürich, Spring 2017 Professors Onur Mutlu and Srdjan Capkun Problem 1 (70 Points): Problem 2 (50 Points): Problem 3 (40
More informationDigital Fundamentals. Lab 6 2 s Complement / Digital Calculator
Richland College Engineering Technology Rev. 0. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. radbury Digital Fundamentals CETT 1425 Lab 6 2 s Complement / Digital Calculator Name: Date: Objectives:
More informationCSE 140L Final Exam. Prof. Tajana Simunic Rosing. Spring 2008
CSE 140L Final Exam Prof. Tajana Simunic Rosing Spring 2008 NAME: ID#: Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page.
More informationECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks
ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class next-next Mon MLK Day ECE230 Review
More informationGraduate Institute of Electronics Engineering, NTU Design of Datapath Controllers
Design of Datapath Controllers Lecturer: Wein-Tsung Shen Date: 2005.04.01 ACCESS IC LAB Outline Sequential Circuit Model Finite State Machines Useful Modeling Techniques pp. 2 Model of Sequential Circuits
More informationVerilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
More informationESE 150 Lab 07: Digital Logic
LAB 07 In this lab we will do the following: 1. Investigate basic logic operations (AND, OR, INV, XOR) 2. Implement an ADDER on an FPGA 3. Implement a simple Finite- State Machine on an FPGA Background:
More information