A High Performance ATM Switch Architecture

Transcription

1 A High Performance ATM Switch Architecture Hong Xu Chen A thesis submitted for the degree of Doctor of Philosophy at The Swinburne University of Technology Faculty of Information and Communication Technology Swinburne University of Technology September 2006

2 Except where otherwise indicated, this thesis is my own original work. Hong Xu Chen September 2006 ii

3 Acknowledgements I would like to take this opportunity to thank my supervisor, Associate Professor Jim Lambert, for his consistent guidance, teaching and support during my Ph.D candidature. I would also like to thank Professor Brad Gibson, Professor Jun Han, Dr. Hai Vu and Ms Charlotte Swain for their help during my thesis examination and their amendments to finalise the thesis. In addition, I would like to thank Associate Professor Bin Qiu from Monash University and Dr. Xi Ying Hu. I would like to thank my aunt, Ms Zhang Han Qiu, for her initial financial support, which gave me the opportunity to pursue both my Masters and Ph.D in Australia. Finally, I would like to thank my mother, Zhang Lin Xia and my father, Chen Chang Ling for their teaching, advice and support in my everyday life. The degree is for them. iii

4 Abstract ATM is based on the efforts of the ITU-T Broadband Integrated Services Digital Network (B-ISDN) standard. It was originally conceived as a high-speed transfer technology for voice, video, and data over public networks. The ATM Forum has broadened the ITU-T s vision of ATM for extended use over public and private networks, multi-protocol support and mobile ATM. There are also some ATM applications in High Performance Computing (HPC). ATM is a packet switching technique based on a virtual circuit mechanism. Data flows are statistically multiplexed and communication resources are dynamically shared. Therefore the high performance ATM switch is essential for quality of services (QoS). This thesis introduces typical ATM switch architecture design and analyses design problems. The research objective is to propose a switch architecture design that can solve or improve those existing problems to achieve a superior performance. The research goal is an integrated ATM switch architecture that will handle both unicast and multicast packets. Unlike the usual design for the multicast ATM switch which concentrates on a cell copy network with a unicast switching network, the proposed switch architecture processes the network packets in a single switching block, and allows unicast and multicast packets to co-exist without competing. The switch design has a simple topology and operation principle and is easy to implement. Furthermore, no copy network is required. Three major components are proposed to form the core of the new switch architecture: the parallel buffering strategy for improved buffer performance, the fast table lookup algorithm for packet duplication and routing, and the relay ring controller for solving the contention problem associated with multiple packets destined for the same output port. A mathematical model is presented and its numerical results are analysed. In addition, the simulation algorithms for the proposed switching design are presented and compared against the switching design with input and output buffering strategies. The simulation results are also compared and analysed against the numerical results. iv

5 A multicast traffic model is also presented. Its performance calculation for the proposed switch is achieved through simulation. Performance analysis is compared against the output buffering switch under the same multicast traffic model. The performance analysis shows that the proposed switch architecture achieves high throughput with low cell loss rate and low time delay. Its performance can be as good as the output buffering strategy or better. Therefore the proposed switch design has solved the problems associated with input and output buffering. This thesis also analyses the complexity of the proposed switch architecture and suggests a topology to build a large scale ATM switch. The suitability and feasibility for production implementation are also addressed. v

6 Table of Contents ACKNOWLEDGEMENTS...III ABSTRACT...IV TABLE OF CONTENTS...VI LIST OF FIGURES...IX LIST OF TABLES...XVI ACRONYMS... XVII PUBLICATIONS...XVIII 1 INTRODUCTION BROAD OBJECTIVES MAJOR CONTRIBUTIONS ATM SWITCH BACKGROUND DETAILED OBJECTIVES OUTLINE OF THE PROPOSED APPROACH ORGANISATION OF THE THESIS LITERATURE REVIEW OF ATM SWITCH ARCHITECTURES LITERATURE REVIEW OF ATM SWITCH ARCHITECTURES Batcher-Banyan network Knockout switch Shared memory and medium switch Crossbar switch Summary LITERATURE REVIEW OF MULTICAST ATM SWITCH ARCHITECTURE Starlite switch Knockout switch Turner s broadcast switch A recursive multistage structure for multicast ATM switching Tony Lee s multicast switch SCOQ Switch ORCN multicast switch Summary NEW MULTICAST SWITCH ARCHITECTURE BUS INTERFACES ATM CELL INFORMATION STRUCTURE MGT TRANSLATION TABLE vi

7 3.4 TRUNK NUMBER TRANSLATOR (TNT) RELAY RING TIMING DIAGRAM OF THE PROPOSED SWITCH ABR AND VBR TRAFFIC DISCUSSION SUMMARY MATHEMATICAL MODELLING AND NUMERICAL RESULTS OF THE PROPOSED SWITCH DESIGN MATHEMATICAL MODELLING NUMERICAL RESULTS Computer aid program Gauss elimination algorithm with partial pivoting Numerical results analysis MULTICAST TRAFFIC MODEL SUMMARY SIMULATION DESIGN AND RESULTS COMPARISON WITH PROPOSED SWITCH, INPUT QUEUING SWITCH AND OUTPUT QUEUING SWITCH SIMULATION FOR PROPOSED SWITCH DESIGN SIMULATION FOR INPUT BUFFERING SWITCH SIMULATION FOR OUTPUT BUFFERING SWITCH SUMMARY SIMULATION DESIGN AND RESULTS COMPARISON UNDER MULTICAST TRAFFIC WITH PROPOSED SWITCH, AND OUTPUT QUEUING SWITCH SIMULATION FOR PROPOSED SWITCH DESIGN UNDER MULTICAST TRAFFIC SIMULATION FOR OUTPUT BUFFERING SWITCH DESIGN UNDER MULTICAST TRAFFIC SIMULATION FOR PROPOSED SWITCH DESIGN WITH PRIORITY QUEUE STRATEGY UNDER MULTICAST TRAFFIC SUMMARY COMPLEXITY AND FEASIBILITY ANALYSIS OF THE PROPOSED SWITCH DESIGN COMPLEXITY AND FEASIBILITY ANALYSIS OF PROPOSED SWITCH COMPLEXITY COMPARISON WITH TYPICAL ATM SWITCHING NETWORK TOPOLOGIES BUILDING A LARGE SCALE ATM SWITCH SUMMARY CONCLUSION REFERENCES vii

8 APPENDIX A MATLAB PROGRAM FOR CALCULATING THE NUMERICAL RESULTS FOR THE QUEUING MODEL OF THE PROPOSED SWITCH APPENDIX B SIMULATION PROGRAM FOR PROPOSED SWITCH APPENDIX C SIMULATION PROGRAM FOR INPUT BUFFERING SWITCH APPENDIX D SIMULATION PROGRAM FOR OUTPUT BUFFERING SWITCH APPENDIX E SIMULATION PROGRAM FOR PROPOSED SWITCH UNDER MULTICAST TRAFFIC APPENDIX F SIMULATION PROGRAM FOR OUTPUT BUFFERING SWITCH UNDER MULTICAST TRAFFIC APPENDIX G SIMULATION PROGRAM FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL UNDER MULTICAST TRAFFIC viii

9 List of Figures FIGURE 1 BATCHER-BANYAN SWITCHING NETWORK [1] FIGURE 2 INTERNAL BLOCKING IN THE BATCHER-BANYAN NETWORK FIGURE 3 KNOCKOUT SWITCH ARCHITECTURE [9] FIGURE 4 BUS INTERFACE ARCHITECTURE [9] FIGURE 5 SHARED MEMORY SWITCH ARCHITECTURE [43] FIGURE 6 SHARED MEDIUM SWITCH ARCHITECTURE [39] FIGURE 7 CROSSBAR SWITCH ARCHITECTURE [27] FIGURE 8 STARLITE SWITCH ARCHITECTURE [4] FIGURE 9 KNOCKOUT SWITCH ARCHITECTURE [22] FIGURE 10 BUS INTERFACE ARCHITECTURE WITH A MULTICAST FUNCTION [22] FIGURE 11 TURNER S BROADCAST SWITCH ARCHITECTURE [17] FIGURE 12 RECURSIVE MULTICAST SWITCH ARCHITECTURE [19] FIGURE 13 TONY LEE S MULTICAST SWITCH ARCHITECTURE [6] FIGURE 14 COPY NETWORK STRUCTURE [6] FIGURE 15 ALGORITHM OF CELL REPLICATION [6] FIGURE 16 SCOQ MULTICAST SWITCH ARCHITECTURE [20] FIGURE 17 COPY NETWORK STRUCTURE [18] FIGURE 18 ORCN MULTICAST SWITCH ARCHITECTURE [18] FIGURE 19 PROPOSED MULTICAST ATM SWITCH ARCHITECTURE FIGURE 20 BUS INTERFACE STRUCTURE FIGURE 21 ATM CELL STRUCTURE FIGURE 22 PROPOSED VCI INFORMATION STRUCTURE FIGURE 23 TABLE LOOKUP ILLUSTRATION FOR LOCN FIGURE 24 STRUCTURE OF THE RELAY RING FIGURE 25 CONTROL LOGIC OF EACH RELAY FIGURE 26 CONTROL LOGIC FOR PRIORITY QUEUE IN EACH RELAY.. 36 FIGURE 27 PHYSICAL MODEL OF A PARTICULAR OUTPUT FIGURE 28 DISCRETE TIME QUEUING MODEL OF THE ATM SWITCH DESIGN FIGURE 29 STATE TRANSITION DIAGRAM OF THE MODELLED SYSTEM FIGURE 30 FLOW DIAGRAM FOR A COMPUTER AID PROGRAM TO CALCULATE FIGURE 31 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L= FIGURE 32 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L= FIGURE 33 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L= ix

10 FIGURE 34 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L=3, 10 AND FIGURE 35 MEAN QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L=3, 10 AND FIGURE 36 AVERAGE PACKET DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L=3, 10 AND FIGURE 37 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L= FIGURE 38 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L= FIGURE 39 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L= FIGURE 40 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 WITH L=3,10 AND FIGURE 41 SIMULATION PROGRAM FLOW CHART FOR PROPOSED SWITCH DESIGN FIGURE 42 PROGRAM FLOW CHART FOR DISTRIBUTING GENERATED PACKETS TO ITS FIGURE 43 PROGRAM FLOW CHART FOR APPLYING THE RELAY RING FIGURE 44 PROGRAM FLOW CHART FOR APPLYING THE FIFO QUEUING SCHEME FIGURE 45 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 46 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 47 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 48 MEAN QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 49 MEAN QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 50 MEAN QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 51 PACKET LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 52 PACKET LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 53 PACKET LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 54 SIMULATION PROGRAM FLOW CHART FOR THE SWITCH.. 78 FIGURE 55 PROGRAM FLOW CHART FOR APPLYING A CONTENTION CONTROL SCHEME FIGURE 56 PROGRAM FLOW CHART FOR COUNTING HOL BLOCKING 80 FIGURE 57 PROGRAM FLOW CHART FOR TRANSMITTING PACKETS WITH RANDOM SELECTION POLICY x

11 FIGURE 58 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING SWITCH FIGURE 59 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING SWITCH FIGURE 60 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING SWITCH FIGURE 61 DELAY VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING SWITCH FIGURE 62 DELAY VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING SWITCH FIGURE 63 DELAY VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING SWITCH FIGURE 64 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING FIGURE 65 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD FOR INPUT FIGURE 66 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD FOR INPUT QUEUING FIGURE 67 SIMULATION PROGRAM FLOW CHART FOR THE SWITCH WITH OUTPUT FIGURE 68 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR THE FIGURE 69 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR THE FIGURE 70 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR THE FIGURE 71 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR THE FIGURE 72 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR THE FIGURE 73 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR THE FIGURE 74 PACKET LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR FIGURE 75 PACKET LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 76 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND FIGURE 77 SIMULATION PROGRAM FLOW CHART FOR PROPOSED SWITCH UNDER MULTICAST TRAFFIC FIGURE 78 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=50 AND BURST TRAFFIC LENGTH= FIGURE 79 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=100 AND BURST TRAFFIC LENGTH= xi

12 FIGURE 80 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=200 AND BURST TRAFFIC LENGTH= FIGURE 81 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=50,100,200 AND BURST TRAFFIC LENGTH=50,100, FIGURE 82 AVERAGE QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=50,100,200 AND BURST TRAFFIC LENGTH=50,100, FIGURE 83 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=50 AND BURST TRAFFIC LENGTH= FIGURE 84 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=100 AND BURST TRAFFIC LENGTH= FIGURE 85 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH L=200 AND BURST TRAFFIC LENGTH= FIGURE 86 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR FIGURE 87 SIMULATION PROGRAM FLOW CHART FOR OUTPUT BUFFERING SWITCH UNDER MULTICAST TRAFFIC FIGURE 88 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=400 AND BURST TRAFFIC LENGTH= FIGURE 89 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=800 AND BURST TRAFFIC LENGTH= FIGURE 90 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=1600 AND BURST TRAFFIC LENGTH= FIGURE 91 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=400 AND BURST TRAFFIC LENGTH= FIGURE 92 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=800 AND BURST TRAFFIC LENGTH= FIGURE 93 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=1600 AND BURST TRAFFIC LENGTH= xii

13 FIGURE 94 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=400 AND BURST TRAFFIC LENGTH= FIGURE 95 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=800 AND BURST TRAFFIC LENGTH= FIGURE 96 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR OUTPUT BUFFERING SWITCH VERSUS PROPOSED SWITCH WITH L=1600 AND BURST TRAFFIC LENGTH= FIGURE 97 SIMULATION PROGRAM FLOW CHART FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL FIGURE 98 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=10 VERSUS OUTPUT BUFFERING SWITCH WITH L=50 FOR BURST TRAFFIC LENGTH=50 AND PRIORITY QUEUE COUNT= FIGURE 99 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=20 VERSUS OUTPUT BUFFERING SWITCH WITH L=100 FOR BURST TRAFFIC LENGTH=100 AND PRIORITY QUEUE COUNT= FIGURE 100 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=40 VERSUS OUTPUT BUFFERING SWITCH WITH L=200 FOR BURST TRAFFIC LENGTH=200 AND PRIORITY QUEUE COUNT= FIGURE 101 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH NL=80 VERSUS OUTPUT BUFFERING SWITCH WITH L=80 FOR BURST TRAFFIC LENGTH=50 AND PRIORITY QUEUE COUNT= FIGURE 102 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH NL=160 VERSUS OUTPUT BUFFERING SWITCH WITH L=160 FOR BURST TRAFFIC LENGTH=100 AND PRIORITY QUEUE COUNT= FIGURE 103 DELAY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH NL=320 VERSUS OUTPUT BUFFERING SWITCH WITH L=320 FOR BURST TRAFFIC LENGTH=200 AND PRIORITY QUEUE COUNT= xiii

14 FIGURE 104 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH NL=80 VERSUS OUTPUT BUFFERING SWITCH WITH L=80 FOR BURST TRAFFIC LENGTH=50 AND PRIORITY QUEUE COUNT= FIGURE 105 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH NL=160 VERSUS OUTPUT BUFFERING SWITCH WITH L=160 FOR BURST TRAFFIC LENGTH=100 AND PRIORITY QUEUE COUNT= FIGURE 106 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH NL=320 VERSUS OUTPUT BUFFERING SWITCH WITH L=320 FOR BURST TRAFFIC LENGTH=200 AND PRIORITY QUEUE COUNT= FIGURE 107 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=10 AND BURST TRAFFIC LENGTH=50 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 108 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=20 AND BURST TRAFFIC LENGTH=100 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 109 THROUGHPUT VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=40 AND BURST TRAFFIC LENGTH=200 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 110 AVERAGE QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=10 AND BURST TRAFFIC LENGTH=50 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 111 AVERAGE QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=20 AND BURST TRAFFIC LENGTH=100 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 112 AVERAGE QUEUE LENGTH VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=40 AND BURST TRAFFIC LENGTH=200 FOR PRIORITY QUEUE COUNT=5 AND xiv

15 FIGURE 113 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=10 AND BURST TRAFFIC LENGTH=50 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 114 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=20 AND BURST TRAFFIC LENGTH=100 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 115 CELL LOSS PROBABILITY VERSUS OFFERED TRAFFIC LOAD BETWEEN 0 AND 0.13 FOR PROPOSED SWITCH WITH PRIORITY QUEUE BUFFER CONTROL WITH L=40 AND BURST TRAFFIC LENGTH=200 FOR PRIORITY QUEUE COUNT=5 AND FIGURE 116 THREE-STAGE MARS SWITCHING NETWORK ARCHITECTURE FIGURE 117 THREE-STAGE CLOS SWITCHING NETWORK ARCHITECTURE xv

16 List of Tables TABLE 1 CELL LOSS PROBABILITY FOR PROPOSED SWITCH WITH N= TABLE 2 CELL LOSS PROBABILITY FOR PROPOSED SWITCH WITH N= TABLE 3 CELL LOSS PROBABILITY FOR OUTPUT QUEUING SWITCH WITH N= TABLE 4 CELL LOSS PROBABILITY FOR OUTPUT QUEUING SWITCH WITH N= xvi

17 Acronyms ABR AF ATM BBN B-ISDN CAM CBR CDN CRP FIFO HOL HPC ITU-T LOCN MCN MGT MPLS NC ORCN QoS TNT TDM UMI VBR VC VCI VP VPI Available Bit Rate Address Filter Asynchronous Transfer Mode Broadcast Banyan Network Broadband Integrated Services Digital Network Content Addressable Memory Constant Bit Rate Cyclic Distribution Network Contention Resolution Processors First In First Out Head of Line High Performance Computing International Telecommunication Union Telecommunication Standardisation Sector Logic Output Channel Number Multicast Channel Number Multicast and Group Translator Multi-Protocol Label Switching Number of Copies Output-Reserved Copy Network Quality of Services Trunk Number Translator Time Division Medium Unicast/Multicast Indicator Variable Bit Rate Virtual Channel Virtual Channel Identifier Virtual Path Virtual Path Identifier xvii

18 Publications [1] Hongxu Chen, J. Lambert, A. Pitsillides, RC-BB Switch: a High Performance Switching Network for B-ISDN, IEEE Proceedings, GLOBECOM, November [2] Hongxu Chen, J. Lambert, A. Pitsillides, Input Queuing Strategy for Batcher- Banyan Switching Network, Proceedings, ATNAC, December [3] Hongxu Chen, J. Lambert, Design of a High Performance Multicast ATM Switch for B-ISDN, IEEE Proceedings, GLOBECOM, November 1998, pp xviii

19 1 Introduction Asynchronous Transfer Mode (ATM) technology is based on the efforts of the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) Study Group XVIII to develop a Broadband Integrated Services Digital Network (B-ISDN) for the high-speed transfer of voice, video, and data through public networks. Through the efforts of the ATM Forum, ATM is capable of transferring voice, video, and data through private networks and across public networks. ATM continues to evolve as the various standards groups finalise specifications that allow interoperability among the equipment produced by vendors in the public and private networking industries, multi-protocol support and mobile ATM. There are also some ATM applications in the High Performance Computing (HPC) area. This study aims to overcome some weaknesses in ATM switch technology and has broader relevance to switch technology in general (not necessarily in the context of ATM). This may also have some relevance to other high speed switching applications and to variable size packet switching such as MPLS, but the main focus here is ATM switches. This thesis has been delayed due to external circumstance and because my former supervisor was retired during the last phase of my PhD study. 1.1 Broad objectives The main objective of this research is to identify the key weaknesses of the major ATM switch architectures that have been used in the past, and seek to propose an architecture that will overcome these weaknesses and optimise switch performance. 1.2 Major contributions The major contributions to this field of study are: a new multicast ATM switch architecture is proposed that has a simple design, a simple switching algorithm and also performs well. It is modular, and can be scaled up to a larger size. Based on reverse Knockout switch architecture, it was presented in the research paper Design of a high performance multicast ATM switch for B-ISDN in the Proceedings of the 1998 IEEE GLOBECOM conference one of the most prestigious international 1

20 conferences in this field. Performance analysis for the new multicast ATM switch architecture is provided. A queuing model based on multiple-access protocol is introduced and the numerical results are plotted and analysed. The analysis shows that the proposed switch has excellent performance characters. A performance comparison for input and output buffering switches is provided and analysed. The comparison shows that the proposed switch design has better performance than the input buffering switch, and also performs as well as the output buffering switch that has been proven to have optimal performance relative to any other buffering strategy a new mechanism to make cell copy for multicast without using a copy network is proposed. It has a simple internal bus structure combined with MGT (multicast and group translator) and TNT (trunk number translator). This mechanism was also presented in the research paper Design of a high performance multicast ATM switch for B-ISDN in the Proceedings of the 1998 IEEE GLOBECOM conference a new routing algorithm based on table lookup technique is proposed that can handle both unicast and multicast packets. The routing algorithm is implemented in MGT. A new table structure that can handle both unicast and multicast packets is also proposed. This was presented in the research paper Design of a high performance multicast ATM switch for B-ISDN in the Proceedings of the 1998 IEEE GLOBECOM conference a new contention resolution mechanism called a relay ring is proposed. A parallel buffering strategy is introduced to solve the HOL blocking problem associated with input buffering. The relay ring is introduced to solve contention among packets for the same output link without the internal speedup required by output buffering. This was initially presented in the research paper RC-BB switch: a high performance switching network for B- ISDN in the Proceedings of the 1995 IEEE GLOBECOM conference one of the most prestigious international conferences in this field. It was also used in two additional research papers Input queuing strategy for the Batcher- Banyan switching network in the Proceedings of the 1995 Australian 2

21 Telecommunications Conference one of the most prestigious national conferences in this field, and Design of a high performance multicast ATM switch for B-ISDN in the Proceedings of the 1998 IEEE GLOBECOM conference the priority queue switching algorithm to improve switch performance is introduced and easily implemented within the relay ring. The detailed control logic of the relay ring for the priority queue switching algorithm is also presented and described. The priority queue idea was initially presented in the research paper Queuing in high-performance packet switching in the Proceedings of the 1988 IEEE Journal of Selected Areas Communications an extensive list of references are provided, including 114 research papers, journals or books on ATM switching or HPC and queuing theory well-designed and tested simulation programs for the proposed switch and the input and output buffering switches are provided. Well drawn and logical simulation flow charts are described. The detailed C++ programs are provided in the appendixes. The simulation results are compared and analysed against numerical results for the proposed switch and the input and output buffering switches a multicast traffic model is proposed. Simulation for the proposed switch and the output buffering switch using the multicast traffic model are provided. Well drawn and logical simulation flow charts are described. The detailed C++ programs are provided in the appendixes. Simulation results for the proposed switch and the output buffering switch are compared and analysed complexity, feasibility and scalability are provided and analysed. The analysis is described in a new angle, derived from topology, buffer, scalability, implementation and functionality aspects. The complexity is also compared with some other typical ATM switching architectures. The analysis shows that the new multicast ATM switch architecture has a simple design, a simple topology and a simple switching algorithm. The architecture is also modular, scalable and feasible. 3

22 1.3 ATM switch background In this section, an overview of ATM switch research is introduced, thus establishing a framework and perspective for the specific objectives of the research, as follows: new communication services such as video on demand, voice-over IP, teleconferencing and distributed data processing have varying requirements of bandwidth, transfer delay, tolerated information loss and call blocking probability ATM was proposed by ITU to address these requirements Asynchronous Transfer Mode (ATM) is based on the efforts of the ITU-T Broadband Integrated Services Digital Network (B-ISDN) standard. ATM is a packet switch technique based on a virtual circuit mechanism. Data flows are statistically multiplexed and communication resources are dynamically shared the aim of ATM switch design is to allocate switch and transmission bandwidth to satisfy the quality of service (QoS) parameters without under utilising network resources. A large number of switch architectures are proposed for implementing an ATM switch [1-65]. We can group them into three major classes: multistage switches, shared memory or shared medium switches and crossbar switches. In multistage switches such as the Banyan switch [14] and its many subclasses, internal link blocking can occur due to more than one cell contending for the same internal link, and output blocking can also occur due to more than one cell being destined for the same output. In shared memory [40], [43], [51], shared medium [39] or crossbar switches such as the crossbar switch [24], [27] and the Knockout switch [9], internal link blocking cannot occur, but output blocking cannot be avoided. Queuing is therefore required. There are three types of queuing: input, shared and output queuing. Input queuing is good for resolving contention at the input. But it needs contention control logic to transfer the packet from the input queue to the output port without internal contention. This approach suffers from Head of Line (HOL) blocking, which has a throughput of only about 58 per cent with first-in-first-out input queues. Output queuing accepts packets from every input port simultaneously during one time slot. However, only a single packet may be served by an output port, thus causing possible output contention. 4

23 Therefore output queuing is required to solve the contention. Output queuing has the best performance characteristic. But it needs N times faster internal links in order to accept N packets destined for the same output port simultaneously from the N input port. The shared buffer approach still provides for output queuing, but rather than have a separate queue for each output, all memory is pooled into a shared queue. The shared queue approach requires fewer queues than output queuing, because several separate queues are combined in a single memory. More complicated control logic is required to ensure that the single memory performs the FIFO discipline to all output ports. The Batcher-Banyan, Knockout and crossbar switches with good interconnection structures and good performance have received more attention and are preferably chosen to implement the cell-routing function. But output blocking will certainly occur when more than one cell is destined for the same output port. Several studies have been completed on output port contention resolution [3-5], [30], [31], [53]. The Starlite switch was designed based on the Batcher-Banyan switch by Huang in 1984 [4]. A trap network is located between the Batcher and Banyan networks. If there is more than one cell with the same destination address, the Batcher will let one pass and feed the rest back to the input of the Batcher network for the next cycle. Two major drawbacks of the trap network are complexity of implementation and the possibility of causing out-of-sequence cells. Another architecture based on the Batcher- Banyan switch is the moonshine switch proposed by Hui in 1987 [3]. It deploys a threephase algorithm in conjunction with input queuing at each input port. The three phases are the arbitration phase, which checks whether contending cells are waiting at the input by sending special messages called requests; the acknowledgement phase which informs the waiting cells of the winning requests selected from those contending requests in phase one; and the sending phase which sends the winning cells acknowledged in phase two through the network. Since both phases do not perform real data transfer, but merely introduce overhead processing, a 14 per cent speedup is required as described by Hui, which is a drawback of this architecture. Another drawback is that the input buffer can only achieve about 58 per cent of the maximum throughput. The switch architecture described so far is based on multistage interconnection networks comprised of small switching elements. Now a fully interconnected topology, 5

24 in the sense that every input has a non-overlapping direct path to every output so that no cell blocking or contention may occur internally, is introduced. The Knockout Switch is an example [9]. It uses a fully interconnected topology to passively broadcast all input packets to all outputs. The bus interface performs several functions. First, it filters out all packets that are not destined to the output port. This operation effectively achieves the switching function in a fully distributed manner, but requires the N simple filtering element per output port. Next, it buffers the packets for that output among all input lines. The buffer is shared, is filled in a cyclical manner, and is served to the output port by FIFO. The structure of this topology is simple and has low latency, and the bus structure makes multicast much easier. But there is still a possibility of packet loss in the concentrator in the bus interface in this switch architecture. The crossbar switch still has its advantages since it is always possible to set-up a connection between any arbitrary input and output pair [24], [27]. Internal blocking will not occur in the crossbar switch. Low latency is another advantage. But output blocking may still occur and it also uses the maximum number of cross points within the switch and it is difficult to build a large scale switch. Another important fact for switch design is the queuing strategy. In input queuing, a FIFO buffer is placed at each input port [29]. Only the packet at the head of the queue can be transmitted. The advantage for input queuing is that the packet sequence is always in order. The drawback is poor performance due to head of line (HOL) blocking. In this case, the switch interconnection network will also transfer the packet from input buffer to the output port without internal condition knowledge. Therefore the internal buffering or internal control mechanism is required for multistage switching architecture. Depending on the control algorithm, the internal control mechanism could be simple (round robin) or more complex. In output queuing strategy, the buffer is located at each output port [24], [26]. Good performance is a proven advantage in [2] and [8]. The drawback is that it needs internal speedup in the case of multiple packets destined for the same output port. For multistage switching architecture, it also needs internal buffering or internal control mechanism for transferring packets from the input port to the output buffer (controlling the internal collision). 6

25 In shared queuing strategy, a simple buffer space is shared by all the inputs for writing and all the outputs for reading [43], [51], [63]. The advantages are proven performance [2], [96] and everything is under control, such as routing control, signal control and packet sequence, etc. The drawback is that a fast internal processor and internal link are needed, therefore hardware limitation exists. It also needs a complicated switching algorithm and buffer management algorithm. There is another very special parallel queuing strategy described in [2], [24] and [61]. Each queue is split into N separate queues, one for each output link. In [24], the switch is built based on crossbar switch topology. The parallel buffers are placed at each crosspoint. As it is proven in [24], the performance of this switch is optimal and is just as good as the output buffering switch. But it uses a maximum number of cross points and has no multicast function. In [61], the parallel buffers are shared by all input ports and surely good performance is the advantage. But it has no multicast function and needs a fast internal link if more than one packet goes to the same buffer. In addition, multicast is a must support function in the ATM switch design. In the future many networking services for B-ISDN, such as video on demand, voice-over IP, teleconferencing and distributed data processing will require transmission of information from one source to multiple destinations simultaneously. The multicast function in the ATM switch is designed to support those networking services. Usually a multicast switch is constructed by cascading a cell copy network and a routing network. A complex issue for multicast switch design is to generate as many copies as the number of target users and to route copied cells with a satisfactory performance. Many multicast switching studies have been reported [17-23], [41], [47-48], [54], [63-65]. They are mainly grouped into three classes: tandem class [6], [17-18], [47-48], [63-64], recursive class [19], [21], [54] and multicast bus class [20], [22-23], [65]. The tandem class usually is a copy network followed by a point to point routing network. In this approach, a multicast cell is replicated in the copy network, which is then sent through the routing network as a unicast cell. The advantages are constant latency and no modification is needed in the routing network. However, there are two drawbacks with this approach: replicated multicast cells must compete with normal unicast cells in 7

26 the copy network, which can cause cell loss and unicast cells experience additional delays due to the copy network. The recursive class recirculates the outputs of the routing network back to the input. In this approach, cells that cannot reach their destination in the first pass are recirculated back in order to replicate and try to pass through the routing network again. The advantage of this approach is that no copy network is needed and the switch structure is simple, but the cell replication requires cell recirculation which introduces additional delays and non-constant latency. The multicast bus class has separate multicast buses. Cell replication can be performed easily without contending with unicast cells, but additional hardware is needed for the multicast function. Large-scale implementation is also difficult. In this section, we have introduced new communication services, ATM, the ATM switch and ATM switch research, the multicast ATM switch and queuing strategy. By studying ATM switches and multicast ATM switches, research objectives are established. and the researcher s approach is clearly defined. 1.4 Detailed objectives By now, we have analysed the merits and drawbacks for different ATM switching topology and buffering strategies. This identifies the problems that we are seeking to solve in this research project. Our research objectives are to find a switching architecture that is simple, modular, maintainable, fault tolerant and feasible according to switch design principles. The proposed switch architecture should: solve the HOL blocking problem associated with input buffering and the internal speedup requirement for output buffering and shared buffering have the multicast function without the duplicated copy network or packet recirculation that is usually required seek a switching/routing algorithm that is easy, fast and programmable demonstrate a performance that is at least as good or better than the output buffering switch find a mathematical model for theoretical support 8

27 develop the simulation algorithms and programs to prove the performance of the proposed switch architecture seek an expandable architecture to build a large scale ATM switch based on the proposed switch architecture be flexible and provide support for ATM, ABR and VBR traffic. 1.5 Outline of the proposed approach First, we need to study typical ATM switches and multicast ATM switches. By analysing their advantages and drawbacks, we should arrive at a new design that can inherit advantages and overcome drawbacks, thereby: creating a new multicast ATM switch design applying a mathematical model to prove the proposed switch design theoretically and finding a multicast traffic model for multicast simulation applying simulation and comparing simulation results with numerical results from a mathematical model to prove the mathematical model applying simulation to compare new switch design with input queuing switch and output queuing switch to prove the performance applying simulation for the new switch design and output queuing switch under a multicast traffic model and comparing the results to prove the performance providing complexity analysis proposing a topology to build a large scale switch. 1.6 Organisation of the thesis The rest of the thesis is organised as follows: Chapter 2 offers a literature review of ATM switch architectures including typical ATM switching network topologies and typical ATM multicast switching topologies. Chapter 3 describes the new proposed switch architecture. The queuing model for the proposed switch architecture and its numerical results are introduced in Chapter 4. A performance comparison against a mathematical model for the input and output buffering switch using simulation is offered in Chapter 5. Chapter 6 analyses the performance for the proposed switch design using a multicast traffic model and compares its performance against the output buffering switch. 9

28 Chapter 7 provides a complexity and feasibility analysis of the proposed switch design. This chapter also proposes a solution to build a large scale ATM switch based on the proposed switch design. Chapter 8 is the concluding chapter in the thesis, followed by the references and appendixes. 10

29 2 Literature review of ATM switch architectures Many designs for ATM switches have been proposed. The purpose here is to review existing switch designs in order to assess their strengths and weaknesses in order to develop a better design. As a multicast function is required by the ATM switch, the review of multicast ATM switches is introduced in section Literature review of ATM switch architectures In this section, various ATM switches are examined. The switches are classified according to whether they are a multistage switching network, a fully interconnected topology, a shared memory and shared medium switch or a crossbar switch Batcher-Banyan network Figure 1 shows a block diagram of an 8 8 Batcher-Banyan network. A Batcher sorting network is placed in front of the Banyan routing network with a shuffle-exchange network connecting them. Sort 2 Merge 4 Merge Batcher Network Banyan Network Shuffle Exchange Figure 1 Batcher-Banyan switching network [1] The Batcher network is constructed of sorting elements (each with two inlets) which compare the bits of the destination address and switch to either pass or exchange. In Figure 1, it sorts the cells in ascending order according to their destination address and places the cell with the lower address at the upper outlet of the Batcher network. The arrow in Figure 1 points to the outlet at which the larger number is to be routed. If only a single cell is present at one of two inlets, it will be taken as the lower 11

30 value [33]. Figure 1 shows how the Batcher sorting network sorts three cells with destination addresses 010, 011, 111. After cells arriving at the inlets of the Banyan network are already sorted into ascending order. This ensures non-blocking inside the Banyan network if no multiple cells are destined to a single outlet as proven by Lee in [6]. The banyan network is a simple self-routing network constructed from 2 2 switching elements. Each element is a 2 2 crossbar switch and routes the incoming cell according to the value of a bit in its destination address, 0 or 1. No matter from which inlet a cell enters the network, it will always be routed stage by stage to the outlet which corresponds to its destination address. Figure 1 shows how three cells with destination addresses 010, 011, 111 are routed to their own outlet via the Banyan network. Now the problem with a non-blocking switch network is that output port blocking will certainly occur and internal link blocking may occur as well if no buffering strategy is adopted, and more than one cell with the same destination address arrives at the Banyan routing network. Figure 2 shows how internal link blocking occurs when two incoming cells have the same destination address. Sort 2 Merge 4 Merge Batcher Network Banyan Network Shuffle Exchange Figure 2 Internal blocking in the Batcher-Banyan network A rectangular N x N (For N = 2 to 2 n ) Banyan network is constructed from identical 2 X 2 switching elements with Log 2 N stages; each stage consists of N/2 switching elements. This makes it much more suitable than the crossbar structures for the construction of large switch fabrics. Unfortunately, the Banyan is an internal blocking network and its performance degrades rapidly as the size of the network increases. The 12

31 number of elements in the Batcher sorting network is (N/4)*((log 2 N) 2 + log 2 N). Achieving the Batcher network becomes increasingly more difficult for larger switch sizes, because the placement/arrow of the sorting element in the Batcher network will become more and more complex, especially during the sorting stage and the first merging stage. In addition, the growth of a Batcher network is of the order of N*log 2 N 2, so many more switching stages are required in the Batcher network than in the Banyan network Knockout switch The Knockout switch architecture is shown in Figure 3. It uses a fully interconnected topology to passively broadcast all input packets to all outputs [9]. It has two basic characteristics: 1) each input has a separate broadcast bus 2) each output has access to the packets arriving at all inputs. Figure 3 illustrates these characteristics where each of the N inputs is placed directly on a separate broadcast bus and each output passively interfaces to the complete set of N buses. This simple structure has several important features: 1) with each input having a direct path to every output, no internal switching collision occurs. The only congestion in the switch takes place at the interface to each output where multiple packets can arrive simultaneously with the same output address, 2) the switch architecture is modular, 3) the bus structure can achieve a higher transmission rate, 4) it is easier to implement broadcast and multicast functions with the bus structure. Figure 4 illustrates the architecture of bus interface associated with each output in the Knockout switch. It has three major components: the packet filter, concentrator and shared buffer. The packet filter checks incoming packets that will be discarded if their address is not for this output port. The concentrator achieves an N to L concentration of the input lines. Maximum L packets can make it through the concentrator if there are more than L packets destined for this output port. This is where the cell loss occurs. The Knockout tournament principle is implemented to achieve the concentration. It is from this principle that the term Knockout Switch originates. The shared buffer consists of a shifter and L separate FIFO buffers. It is the equivalent of a single queue with L inputs and one output under FIFO discipline. Complete sharing of the L FIFO buffers is controlled by the shifter that works in a cyclic manner. 13

32 Inputs 1 2 : N Bus Interfaces N Outputs Figure 3 Knockout switch architecture [9] INPUTS N PACKET FILTERS 1 2 L CONCENTRATOR SHIFTER 1 2 L PACKET BUFFERS OUTPUT Figure 4 Bus interface architecture [9] In the Knockout switch, the number of cell filters is N 2 and the number of the concentrator is N. The number of interconnection wires in the crossbar-link network is N 2. In the concentrator, more and more knockout tournament stages and tournament elements 14

33 will be required when the switch size N grows. It is a good alternative for constructing non-blocking switching elements and switches of modest size Shared memory and medium switch The shared memory switch architecture is illustrated in Figure 5. In this approach, there is only one buffer that is shared by all input and output ports [40], [43], [51]. The memory controller decides the order in which cells are read from the memory. It has the better performance in terms of throughput versus cell loss under heavy load. But the drawback is that the shared memory must operate N times faster than the port speed. In addition, the control algorithm for the memory controller is very complicated. Therefore a faster processor is required and more software control algorithms are involved in the memory controller. A shared memory switch has very simple hardware architecture compared with other switch architectures described in this section. But as it needs N times speed for memory access, it is not suitable for large N due to physical limitation. It can only be used to build switching elements that can be used as a building block in larger multistage switching systems. Controller Headers WA/RA 1 S/P S/P 1.. Memory.. N S/P S/P N Figure 5 Shared memory switch architecture [43] Figure 6 shows the shared medium switch architecture. The shared medium could be a ring, bus or dual bus. Time-division multiplexed buses are a popular example of this approach [39]. The incoming packets are sequentially broadcast on the TDM bus in a round-robin manner. At each output, address filters pass the appropriate cells to the 15

34 output buffers based on their routing tag. The bus speed must be at least N times faster than the port speed to eliminate input queuing. This will place a physical and hardware technology limitation on the switch specification. In addition, the address filters and output buffers also have to operate at bus speed to avoid cell loss due to multiple packets destined to the same output port. The shared medium switch has very simple hardware architecture. But as it needs N times speed for TDM bus, it is not suitable for large N due to physical limitations. It can only be used to build switching elements that can be used as a building block in larger multistage switching systems. 1 N S/P.. S/P T D M B U S AF.. AF P/S.. P/S 1 N Buffers Figure 6 Shared medium switch architecture [39] Crossbar switch The crossbar switch is the simplest example of a matrix-like space division fabric that physically interconnects any of the N inputs to any of the N outputs as shown in Figure 7. It is easy to implement. The address filter (AF) at each cross point checks the incoming packet to read for the output address that the AF is assigned to. It will then pass the incoming packet to the output port. The controller is responsible to solve the output contention in case more than one packet is destined for the same output port. Various algorithms for contention resolution can be implemented such as round robin or random selection. There is no internal blocking that exists for this topology, but in order to avoid the packet loss at the output port, either the output port and the controller must operate at N times faster than the input port or output buffers must be placed at each cross point [24], [27]. 16

35 1 AF AF.... AF 2 N... AF C O N T R O L E R AF C O N T R O L E R.... AF C O N T R O L E R AF AF AF 1 2 N Figure 7 Crossbar switch architecture [27] Crossbar designs have a complexity in paths or cross points that grows as a function of N 2 where N is the number of input ports or output ports for the ATM switch. Thus, they do not scale well to large sizes. They are however very useful for the construction of non-blocking, self-routing, switching elements and switches of modest size Summary In this chapter, four typical ATM switch topologies are introduced. Their advantages and drawbacks are analysed. So far, most ATM switch architecture designs have been based on the above topologies [1-65]. In principle, contention resolution, performance, multicasting, scalability and complexity are the issues that researchers address. Many approaches have been proposed to improve or solve one or more of these issues. In the following section, more multicast ATM switches based on these four topologies are studied and analysed. 17

36 2.2 Literature review of multicast ATM switch architecture Many designs for multicasting ATM switches have been proposed [114]. The purpose here is to review existing designs in order to assess their strengths and weaknesses in order to propose a better design. In the following sections, various multicast ATM switches are examined. The switches are classified according to copy networks and recursive structure Starlite switch Sorter Copy Concentrator Figure 8 Starlite switch architecture [4] The structure of the Starlite switch [4] is shown in Figure 8. It is built and based on the Batcher-Banyan switch architecture. It carries out multicasting by a two-stage copy network placed above the concentrator, as shown above. The first stage is a sorting network. New cells entering the switching fabric are put into input ports on the left. Multicasting cells are put into input ports on the right. Multicasting cells are special cells that contain the channel identification of the cells they want to copy and the destination port to which the copy is to be sent. The sorting network sorts the cells based on their source addresses (channel identification), so that each new cell appears next to multicasting cells that want to copy it. The copy network then duplicates each new cell 18

37 into all of its copies and injects the cells into the concentrator. In the previous cell replication process, the Starlite switch assumes the synchronisation of the source and destinations, and an empty packet set-up procedure is also required. But it is not feasible to implement this approach in a broadband packet network in which packets may usually experience delay variation due to buffering, multiplexing and switching in a multiple-hop connection Knockout switch Figure 9 Knockout switch architecture [22] The original Knockout switch [9] does not support multicasting. To support multicasting, in addition to the N bus interfaces, M multicast modules [22] are specially designed to handle multicast packets. As shown in Figure 9, each multicast module has N inputs and one output. The inputs are the signals from the input interface modules. The output drives one of M bus for broadcasting to all the N bus interfaces. There are two proposed approaches to implement the multicast module. A block diagram of the multicast module is illustrated in Figure 10. The incoming cells are selected through the cell filters which are set to accept multicasting cells only. 19

38 The selecting principle adopted is the same as in the original Knockout switch: an N-L (L<<N) Knockout concentrator is used and L winners' from the N-L concentrator are stored in an L-input, one-output FIFO buffer after proper shifting. Upon exit from the buffer, a multicasting cell enters into the cell duplicator to duplicate cells with different destination addresses in the header. The duplicated cells are sent along the broadcast bus to the required bus interfaces. In this scheme, the various destination addresses of replicated cells are obtained by table lookup. Figure 10 Bus interface architecture with a multicast function [22] Knockout is based on a crossbar network and therefore performs best. It has a simple principle for multicasting and cell duplication. But extra hardware and buses are required for multicasting Turner s broadcast switch The switch fabric architecture of Turner s broadcast switching network [17] is shown in Figure 11. This is also an ATM switch based on Banyan switching topology. 20

39 Figure 11 Turner s broadcast switch architecture [17] Where CP is the Connection Processor, CN is the Copy Network, PP is the Packet Process, DN is the Distribution Network, BGT is the Broadcast and Group Translator and RN is the Routing Network. When a broadcast cell having K destinations passes through the copy network, it is replicated so that K copies of that cell emerge from the copy network. Unicasting cells, pass through the copy network without any change. The broadcast and group translators will then determine the routing information for each cell in the rest of the switch. Based on translated routing information, the distribution and routing networks route the cells to the proper outgoing packet processor. The novelty of Turner s switch is its clear design logic and flexible broadcast capability. However, Turner s switch is a blocking switch. When two cells arrive at the same switching element in the routing network, collision will occur if these cells attempt to exit on the same output link. Therefore, buffers are required for every internal node in the routing network to prevent packet loss and cell collision. An extra copy network is required in order to implement multicast function A recursive multistage structure for multicast ATM switching This switch provides self-routing switching nodes with a multicast facility, based on a buffered N x N multistage interconnection network (a kind of Banyan network) with external links connecting outlets to inlets [19]. The structure of this multicast switch is shown in Figure 12. Such a network is able to route a cell to the addressed output for transmission and generate M copies of the same cell (with M<<N) on M pre-defined adjacent outlets. M is the multiplication factor of the multicast connection network 21

40 (MCN). In order to reach more than M outputs, some of the M cells generated in the first crossing of the network are recycled back to the corresponding inputs, and each generate other cells until the requested number of copies are obtained. If a copy bit in the routing tag is set to 0 (unicast cell) for a MCN with a general multiplication factor M, the input cell is addressed to a single output line. Likewise, if the copy bit is set to 1 (multicast cell), C copies (with 2<=C<=M) are simultaneously generated on C consecutive outlets, starting from the addressed output. The number C is specified in the routing tag. If the requested copy number B (with 2<=B<=N) is less or equal to M, all copies can be generated in a single network crossing. If B>M, more crossings are necessary. The concentrators at the inlets merge input and recycling cells, while the binary switches on the outlets manage forwarding and recycling by routing the cells respectively toward their upper or lower output line. Although the proposed recursive mechanism seems very simple, the switching elements located inside the switch architecture have to perform more operations. This will make the switching elements more complex and hardware complexity will be high. In addition, recycle lines will introduce delay to the switch, and cells leaving the switch might be out of sequence. Figure 12 Recursive multicast switch architecture [19] 22

41 2.2.5 Tony Lee s multicast switch Figure 13 Tony Lee s multicast switch architecture [6] Figure 14 Copy network structure [6] The copy network structure is illustrated in Figure 14. It consists of a broadcast Banyan network with switch nodes capable of cell replication. When a multicasting cell contains a set of arbitrary n-bit destination addresses and arrives at a node in stage k, the cell routing and replication are determined by the k bit of all the destination addresses in the header. If they are all 0 or 1, the cell will be sent to the upper or lower link respectively. Otherwise, the cell and its replica are sent on both links with the following modified header information: the header of the cell sent to the upper or lower link contains these addresses in the original header with their k bit equal to 0 or 1 respectively. The modification of cell headers is performed by the node whenever the cell is replicated. In this way, the set of paths from any input to a set of outputs forms a (binary) tree 23

42 embedded in the network, and it will be called an input-output tree or multicasting tree. Figure 15 shows an example of the corresponding multicasting tree. Figure 15 Algorithm of cell replication [6] The actual Lee s multicast switch [6] is shown in Figure 13. When the multicasting cells are received at the running adder network, the number of copies specified in the cell headers is calculated recursively. The dummy address encoders form new headers consisting of two fields: a dummy address interval and an index reference. The dummy address interval, formed by adjacent running sums, is represented by two binary numbers, namely, the minimum and maximum. The index reference is equal to the minimum of the address interval. It is later used by the trunk number translators to determine the copy index. The broadcast Banyan network replicates cells as shown in Figure 15. When copies finally appear at the outputs, the trunk number translators compute the copy index for each copy from the output address and index reference. The broadcast channel number with the copy index forms a unique identifier for each copy. The trunk number translators then translate this identifier into a trunk number, which is added to the cell header and used by the switch to route the cell to its final destination. There are two problems with this design. The first is the copy network capacity s overflow. It means the total number of copies requested exceed the number of outputs in the copy network. The second problem is output port conflicts in the routing network and this occurs when multiple cells request the same output port concurrently. Beyond the previous discussion, there is also a serious problem inside the broadcast Banyan network. When there is more than one multicasting tree in the network, it might be that an internal link is used by more than one tree. This phenomenon is called internal conflict or internal blocking. This phenomenon degrades switch performance 24

43 and increases the cell loss probability in the switch. In addition to the extra copy network that is required, the actual cell duplication algorithm inside the copy network is complex and difficult to implement SCOQ Switch Figure 16 SCOQ multicast switch architecture [20] Where SN is the sorting network and SM is the switching module. Figure 16 shows the multicasting SCOQ switch [20], built and based on the Batcher-Banyan network. It is modified from the original [7], with a copy network in the feedback loop. In a multicasting SCOQ switch, there is a sorting network, L switching modules, a copy network and N input buffers. The sorting network and the switching modules operate as in the original SCOQ switch. While transmitting the multicast and broadcast cells, these cells will be fed back through the copy network. Cells will be duplicated in the copy network according to their requests, and the destination addresses of replicated cells will be assigned by the trunk number translators inside the copy network. A multicasting cell will then be replaced by several unicasting cells. Cell duplication in the multicasting SCOQ switch is performed in the feedback configuration. The advantages of this method are: (1) there is no interference between unicasting cells and the duplication of multicasting cells, (2) the copy network is nonblocking, even without an extra selection or arbitration mechanism, and (3) the buffers at the input ports operate independently and without central control. Although the feedback duplication has the above advantages, this presents a serious problem in itself. The copy network has a similar principle to that of Tony Lee s. 25

44 Therefore it inherits particular drawbacks as described in section 3.5. The main drawback is that more multicast trees cross each other and an internal link in the copy network might be used by more than one tree, which causes internal blocking when there are more and more cells requesting replication at the same switch cycle. This will rapidly degrade and destabilise switch performance [114]. In addition, extra sorting and copy networks are required to perform the multicasting function ORCN multicast switch The shared-buffer copy networks in the various multicast architectures can be divided into two categories from the viewpoint of cell replication mechanism: (1) those in which copies are generated recursively, that is, some are made by feeding some copies cells back to the input side of the network, and (2) those in which copies are generated by a Broadcast Banyan network (BBN) where output ports are reserved before replication. The former is called the recursive copy network (RCN), and the latter is the outputreserved copy network (ORCN). The BBN has already been discussed in the earlier section on Tony Lee s multicast switch [6] and the ORCN is shown in Figure 17. The ORCN [18] consists of a cyclic distribution network (CDN), a set of contention resolution processors (CRP), a BBN, and a set of Trunk Number Translators (TNTs). The CRPs are coordinated through a token ring. The objective of the CDN is to distribute the master multicasting cells to the CRPs cyclically and this will ensure that all CRPs are shared uniformly. Furthermore, by making the active incoming master multicasting cells cyclically concentrated and the corresponding outputs sequence of the master multicasting cells monotonic, cells will not block in the BBN. The CDN consists of a running adder network and a reverse Banyan network. The main functions of the CRPs are (1) to store the master multicasting cells distributed by the CDN and process them in FIFO order, and (2) to update the header of the master multicasting cell in order to reserve as many consecutive outputs of the BBN as the number of copies requested. The combination of the CDN and a token-ring reservation scheme ensures the cyclically non-blocking property of the BBN. 26

45 Figure 17 Copy network structure [18] Figure 18 ORCN multicast switch architecture [18] Copy networks as extra hardware are still required. Although the design of the copy network and cell duplication is logical, it requires a cyclic distribution network, a token ring and a broadcast Banyan network, which is redundant and complicated. 27