Sample Routers and Switches. High Capacity Router Cisco CRS-1 up to 46 Tb/s thruput. Routers in a Network. Router Design

Transcription

1 outer Design outers in a Network Overview of Generic outer Architecture Input-d Switches (outers) IP Look-up Algorithms Packet Classification Algorithms Sample outers and Switches Cisco 46 outer up to 60 Gb/s throughput up to 0 Gb/s ports Juniper Networks T640 outer up to 60 Gb/s throughput up to 0 Gb/s ports High Capacity outer Cisco CS- up to 46 Tb/s thruput two rack types 640 Gb/s thruput up to 6 line cards up to 40 Gb/s each up to 7 racks 3Com port gigabit Ethernet switch 3 4

2 Components of a Basic outer Input/Output Interfaces (II, OI) convert between optical signals and electronic signals extract timing from received signals encode (decode) data for transmission Input Port Processor (IPP) synchronize signals determine required OI or OIs from routing table Output Port Processor (OPP) queue outgoing cells shared bus interconnects IPPs and OPPs II routing table IPP CP OPP OI output queue Control Processor (CP)» configures routing tables» coordinates end-to-end channel setup together with neighboring routers Data Hdr Data Hdr Generic outer Architecture IP Header IP Header IP Header N times line rate Data Hdr N N Packet N times line rate Packet Packet 5 6 Point-to-Point Switch (3 rd Generation) Placement: Output Port Queuing Switched Backplane Line Card CPU Card Line Card Local outing Local Typically < 50Gbps aggregate capacity Fwding MAC Fwding MAC ing when the aggregate arrival rate exceeds the output line speed must operate at very high speed 7 8

3 Data Hdr Switching Speed-up Needed IP Header Packet Simple model of output queued switch Data Hdr IP Header Data Hdr N N IP Header N times line rate N times line rate Packet Packet Link, ingress Link rate, Link, ingress Link 3, ingress Link 4, ingress Link, egress Link rate, Link, egress Link 3, egress Link 4, egress 9 0 Characteristics of an output queued (OQ) switch arriving packets immediately written into output queue, without intermediate buffering flow of packets to one output does not affect flow to another output OQ switch is work conserving: output line always busy when there is a packet in switch for it OQ switch has highest throughput, lowest average delay Placement: Input Port Queuing Fabric slower than input ports combined So, queuing may occur at input queues Head-of-the-Line (HOL) blocking d packet at the front of the queue prevents others in queue from moving forward

4 Simple model of input queued switch Link Link Link 3 Link 4 Link, ingress Link, ingress Link 3, ingress Link 4, ingress Link, egress Link, egress Link 3, egress Link 4, egress Head-of-line Blocking Packet at the head of an input queue cannot be transferred, thus blocking the following packets (or cells packets of fixed size) Cannot be transferred because is blocked by red packet Input Input Input 3 Cannot be transferred because output buffer full Output Output Output Characteristics of an input queued (IQ) switch Placement: Design Trade-offs arriving packets written into input queue only one packet can be sent to output link at a time head-of-line blocking IQ switch cannot keep output links fully utilized Output queues Pro: work-conserving, so maximizes throughput Con: memory must operate at speed N* Input queues Pro: memory can operate at speed Con: head-of-line blocking for access to output Work-conserving: output line is always busy when there is a packet in the switch for it Head-of-line blocking: head packet in a FIFO cannot be transmitted, forcing others to wait 5 6

5 What is capacity of IQ: Model [optional: Karol et al Globecom 86] Large input-queued switch with single FIFO at each input packet destinations iid (independently, identically distributed), uniform across outputs HoL blocked packets not flushed throughput analysis saturated switch (ie, always arrival at each input queue) focus on one output port O X t - number of packets that did not get to O at end of slot t D t - number balls removed from inputs port at the end of t D t is switch thruput 7 Model (cont d) A t+ - no of new HOL packets in input ports with destination O X t+ = (X t -) + + A t+ D = / N k t k Dt k where ( ) ( ) ( ) P A t+ k = / N E(D t ) = ρn where ρ is output throughput for large N, binomial distribution can be approximated by Poisson distribution, k ρ ρ P( A t = k) e k! 8 EX = Model (cont d) E( A ) + EA ( EA) ( EA) A outer with Input s Head of Line Blocking where EA = ρ, E(A ) = ρ + ρ therefore ρ ρ EX = ( ρ ) Delay EX =, therefore = and ρ =- 586% ρ ρ ( ρ) 0% 0% 40% 60% 80% 00% Load 58% 9 0

6 Solution to Avoid Head-of-line Blocking Virtual Output ing How to improve capacity without increasing switching fabric speed? Maintain at each input N virtual queues, ie, one per output use non-fifo scheduler, matching input/output Input Input Input 3 Output Output Output 3 assume fixed length packets each input manages separate queue per output at each time, matching scheduler finds best possible packets from inputs to said to outputs maximum-weight matching N matching scheduler N Matching L ij (t): no of packets at input i for output j at t bipartite graph (V V,E), E V V V,V inputs, outputs (i,j) E iff L ij (t) > 0 matching: subset of E such that input no two edges are adjacent output Scheduling Algorithms Practical Maximal Matchings Max Size Matching Max Wt Matching Not stable Not stable Stable 3 4

7 Maximal matching Not stable Switch Algorithms Max Size Matching Max Wt Matching Not stable Stable, low backlogs Better performance Better Matching Algorithms Need simple algorithms that perform well efficient packet processing packets at line speeds high throughput low latencies/backlogs andomized algorithms with linear complexity available Tassiulas andomized Algorithm LAUA SEENA Use both randomization, history, problem structure and arrival information Easier to implement 5 6 Combined Input-Output d (CIOQ) outers Both input and output interfaces store packets Advantages Easy to built Utilization can be achieved with limited input/output speedup (<= ) Disadvantages Harder to design algorithms Two congestion points Need to design flow control input interface Backplane output interface O C OQ Emulation Each input and output maintains a preference list Input preference list: list of cells at that input ordered in the inverse order of their arrival Output preference list: list of all input cells to be forwarded to that output ordered by the times they would be served in an Output ing schedule Use Gale Shapely Algorithm (GSA) to match inputs to outputs Outputs initiate the matching Can emulate all work-conserving schedulers 7 8

8 Output Emulation using CIOQ (with Speed-up) Stable Matching -- Gale Shapely Algorithm (GSA) While there are unmatched output that are not rejected by all input do Each unmatched output requests its most preferred packet from an input that has not rejected it yet Each input grants the request to the output with the most preferred cell A stable matching exists for every set of preference lists Complexity: worst-case O(N ) 9 Example 30