Multi-wavelength switching in IP optical nodes adopting different buffering strategies

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1 Optical Switching and Networking 1 (2005) Multi-wavelength switching in IP optical nodes adopting different buffering strategies Achille Pattavina Department of Electronics and Information, Politecnico di Milano, Piazza Leonardo da Vinci 32, Milan, Italy Received 16 June 2004; received in revised form 22 October 2004; accepted 3 November 2004 Available online 8 December 2004 Abstract The paper addresses the topic of long-haul optical networking for the provision of large-bandwidth IP services. A class of optical packet switching architectures is considered which adopts an arrayed wavelength grating device as packet router. The architecture performs slotted packet switching operations and fully exploits the wavelength routing capabilities by allowing multi-wavelength switching. Fiber delay lines are used to perform optical packet buffering, which accomplishes either input queueing or shared queueing. Here a thorough performance evaluation is carried out with different buffering configurations and the effect of various switch parameters on traffic performance is studied Elsevier B.V. All rights reserved. Keywords: WDM network; Optical switching; Arrayed waveguide grating (AWG); IP packets; Traffic performance 1. Introduction The growth of existing and new services is creating a large increase in bandwidth request in telecommunication networks, which is likely to grow in the near future. In the last few years, great efforts were made to bring fast traffic channels to the end user, thus making the Broadband Integrated Service Digital Network (B-ISDN) finally real. In order to support this huge amount of traffic, optical backbone networks are being employed, exploiting Work supported by MIUR, Italy, under FIRB project ADONIS and by EU IST Network of Excellence e-photon/one. Fax: address: pattavina@elet.polimi.it. the virtually unlimited bandwidth provided by Dense Wavelength Division Multiplexing (DWDM). However, nowadays packets undergo an Optical/Electrical (O/E) conversion before being switched and another Electrical/Optical (E/O) conversion to be transmitted. Therefore, these optical electrical optical (OEO) switches suffer from a bottleneck in the switching phase, since not all of these operations (i.e., conversions and electronic switching) can be performed at an adequate rate. The development of devices able to switch optical signals resulted in a burst of research works, promising to make switching directly available in the optical domain. Moreover, recently DWDM has evolved to support some network functions such as circuit /$ - see front matter 2004 Elsevier B.V. All rights reserved. doi: /j.osn

2 66 A. Pattavina / Optical Switching and Networking 1 (2005) routing and wavelength conversion and assignment, leading to the idea of all-optical networks, employing Optical Optical Optical (OOO) switching nodes. Unfortunately, today optical devices used in market equipment are still too crude to allow packet-bypacket operation, so the arrival of full-optical networks will probably occur gradually. The simplest solutions are WDM-routed networks, where a wavelength is assigned to each connection in such a way that all traffic is handled in the optical domain, without any electrical processing on transmission. Such networks are basically circuit switched. An interesting solution which tries to represent a balance between circuit switching low hardware complexity and packet switching efficient bandwidth utilization is Optical Burst Switching (OBS, [1,2]). In an optical burst switching system, the basic units of data transmitted are bursts, made up of multiple packets, which are sent after control packets, carrying routing information, whose task is to reserve electronically the necessary resources on the intermediate nodes of the transport network. Such operation results in a lower average processing and synchronization overhead than optical packet switching, since packet-by-packet operation is not required. However, packet switching has a higher degree of statistical resource sharing, which leads to a more efficient bandwidth utilization in a bursty, IP-like, traffic environment. The last solution is Optical Packet Switching (OPS), which promises to perform traffic switching with packet granularity, like with current electronic switches, in order to exploit optical bandwidth more efficiently. Many hurdles are still to be overcome in this field, such as the high reconfiguration speed needed and, mainly, the impossibility of storing optical packets to resolve packet contention. The most promising OPS architectures developed in the last few years are based on two different solutions for the switching fabric: broadcast-and-select architectures, e.g. KEOPS [3] and DAVID [4] projects, and wavelength routing architectures, e.g. OPERA [5]and WASPNET [6,7] projects. In this paper we follow the latter solution and present an OPS node that is a more complex extension of the architecture previously introduced in Ref. [8]. In particular, this node fully exploits the routing device Fig. 1. The optical transport network architecture. (an Arrayed Waveguide Grating) by allowing multiwavelength switching on the same input or output port. In such new optical node configurations packet buffering is allowed by adopting either pure input queueing or combined input-shared queueing. Hence a thorough traffic performance evaluation is carried out here considering different buffering alternatives. The paper is organized as follows. Section 2 describes the optical networking environment and the corresponding switching node architecture is detailed in Section 3. Section 4 shows how a single optical node behaves in terms of traffic performance when loaded by a typical IP traffic pattern. Finally, some conclusions are drawn in Section Optical transport network architecture The architecture of the optical transport network that we propose consists of M optical packet switching nodes, each denoted by an optical address made of m = log 2 M bits, which are linked together in a mesh-like topology. A number of Edge Systems (ES) interfaces the optical transport network with IP legacy (electronic) networks (see Fig. 1). The transport network operation is asynchronous; that is, packets can be received by nodes at any instant, with no time alignment. The internal operation of the optical nodes, on the other hand, is synchronous or slotted, since the behavior of packets in an unslotted node is less regulated and more unpredictable, resulting in a larger contention probability. An ES receives packets from different electronic networks and performs optical packet generation. The optical packet is composed of a simple optical header, which comprisesthe m-bit destination address, and an optical payload containing an IP packet. In principle multiple IP packets could be packed in the

3 A. Pattavina / Optical Switching and Networking 1 (2005) Fig. 2. The optical packet format. also other information needed to correctly receive and manage the optical packet, such as preamble data and packet length information. It is assumed that 60 bits are enough for carrying all information, thus leading to T H = 6 ns. Hence, the total overhead time is equal to T OH = T H + 2T G = 8ns. The slot duration (T ) has been chosen to be equal to the time needed to transmit an optical packet whose payload consists of the smallest TCP/IP packet (i.e. 320 bits, the size of an IP packet carrying a TCP acknowledgment). The time slot duration is therefore equal to T = T OH + 32 ns = 40 ns. IP packets longer than the minimum size are transmitted, since as many consecutive slots as are needed are engaged, considering that the optical header is present just in the first slot of the optical packet. The reader interested in a deeper analysis of the motivations of these choices is referred to Ref. [8]. 3. Optical switching node architecture Fig. 3. The optical packet switching node architecture. same optical packet payload, if they are all addressed to the same ES. The optical packets are buffered and routed through the optical transport network to reach their destination ES, which delivers the traffic that it receives to its destination electronic networks. At each intermediate node in the transport network, optical packet headers are received and electronically processed, in order to provide routing information to the control electronics, which will properly configure the node resources to switch packet payloads directly in the optical domain. The header and payload of an optical packet are transmitted serially, as shown in Fig. 2, where the header duration is equal to T H and payload duration to T P. At each switching node the optical header is read, dropped and regenerated at the node output; therefore, guard times (T G ) are needed in order to avoid payload/header superposition, due to clock jitter in the transmission phase. A guard time T G = 1 ns has been assumed, assuming that optical transmission is carried out at 10 Gbit/s. The optical packet header carries not only the m-bit destination address but The general architecture of a network node consists of N incoming (and outgoing) fibers with W wavelengths per fiber. It includes three stages: a first stage of channel demultiplexing, a second stage of switching and a third stage of channel multiplexing (see Fig. 3). In the first stage the incoming fiber signals are demultiplexed and G wavelengths per channel are fed into each of the W/G second-stage switching planes, which constitute the switching fabric core. Once signals have been switched in one of the switching planes, packets can reach every output port through multiplexing carried out in the third stage. Wavelength conversion must be used for contention resolution, since up to G packets can be concurrently transmitted by each second-stage plane on the same output link. A multi-plane architecture similar to that proposed here can be found in Ref. [9]. The optical components envisioned to be used in this switching architecture proposed here are discussed following this section; in some cases the technology involved is really complex and fully commercial products at affordable costs are not yet available. Nevertheless, our aim is to show that the proposed architectural solution is feasible, albeit not using off-the-shelf components and systems. In this paper we do not discuss the issue of optical signal quality. Thus the possible needs for optical signal

4 68 A. Pattavina / Optical Switching and Networking 1 (2005) Fig. 4. The architecture of the switching plane. regeneration inside the switch, as well as the cost issues, are not investigated, as being closely related to the optical technology adopted, which is likely to be improving constantly in the near future Switching plane structure The detailed structure of one of the W/G switching planes is presented in Fig. 4. It includes three main blocks. One is an input synchronization unit, required as the node is slotted and incoming packets need to be slot aligned. This unit consists of a series of 2 2 optical switches interconnected by fiber delay lines of different lengths. These are arranged in such a way that, depending on the particular path set through the switches, the packet can be delayed for a variable amount of time, ranging between t min = 0 and t max = 2(1 (1/2) n+1 ) T, with a resolution of T/2 n, where T is the time slot duration and n the number of delay line stages. Due to the fast reconfiguration speed needed, fast 2 2 switching devices, such as 2 2 Semiconductor Optical Amplifier (SOA) switches [10] having a switching time in the nanosecond range, must be used. A Fiber Delay Line (FDL) unit is then used to store packets for contention resolution. As was pointed out in Ref. [11] a better performance is obtained by using this stage as an optical scheduler, by proper operation of a set of Tunable Wavelength Converters (TWC) [12,13], in order to schedule the transmission of the maximum number of packets onto the correct output link. This is obtained by delaying each packet by a variable amount of time, ranging between 0 and D max, expressed as a multiple of the basic slot T ; access to the selected delay line is granted by each demultiplexer through selection of a proper wavelength in the TWC. Finally a switching matrix unit, described in Section 3.2, is used to achieve switching of signals. These three blocks are all managed by an electronic control unit which carries out the following tasks: optical packet header processing; synchronization unit managing, in order to properly set the correct path through the synchronizer for each incoming packet, so that these enter the FDL stage slot aligned; tunable wavelength converter managing, in order to properly delay and route incoming packets Switching matrix unit structure Once packets have crossed the fiber delay lines unit, they enter the switching matrix stage in order to be routed to the desired output port. This is achieved using a set of tunable wavelength converters combined with an Arrayed Waveguide Grating (AWG) wavelength router [14]. The AWG is used as it gives better performance than a normal space switch interconnection network, as far as insertion losses are concerned. This is due to the high insertion losses of all the high-speed all-optical switching fabrics available at the moment, that could be used to build a space switch interconnection network. Commercially available devices support channels with GHz spacing and have an insertion loss of less than 6 db. Other optical switch architectures adopting AWGs as router devices can be found in [9,15,16]. Three different structures were proposed in [8] for accomplishing the tasks of this stage; in this paper we will consider the one which resulted in the best performance/cost ratio. Only singleplane implementation of the switching node will be considered (i.e. W = G). The extension to the multiplane scenario is immediate and is deeply examined in Ref. [8]. The basic structure of the switching matrix is shown in Fig. 5. The wavelength of the signals entering the switching matrix is converted to an appropriate wavelength, in order to route the signal to the desired output fiber. Unlike the case for the switching matrix considered in Ref. [8], the key feature of this switching unit is its ability to route more than one packet from a single AWG inlet to different outlets. In fact, the AWG working principle is such that signals with different wavelengths entering the same

5 A. Pattavina / Optical Switching and Networking 1 (2005) adjusting the priorities of packets being recirculated. In this paper each of these lines delays a packet by the same amount of time, D rec, a multiple of the time slot duration T. The effect of using different delay lines for packet recirculation has been analyzed in Ref. [11], albeit in a treatment limited to the case of an AWG that does not allow per-port multi-wavelength switching. It is clear that, since the key property of this structure is having a W W AWG, if R AWG ports are reserved for recirculation lines, a different number k of wavelengths are to be multiplexed now on each AWG inlet. The number of required AWG ports A can be expressed as A = R + NW/k. Therefore, since the relationship A = W must be satisfied, Fig. 5. The switching matrix structure. inlet will emerge on different outlets and different wavelengths are needed to route signals from different inlets to the same outlet. So, no superposition can happen at the AWG outlets between signals coming from the same inlet, if the TWCs convert them to different wavelengths. Since NW different channels enter the switching matrix, if N wavelengths are multiplexed on the same AWG inlet, this structure requires a W W AWG. So, if the AWG works on the same wavelengths as are used in the outgoing fibers, no wavelength conversion is needed at the switching matrix output, since packets exit the AWG using one of the transmission wavelengths. Finally, W/N AWG outlets will be multiplexed onto the same output fiber. Therefore, a packet entering an AWG outlet can be routed to the desired output fiber using one of the W/N wavelengths which will route it to an outlet connected to the fiber. Particular attention must be paid by the electronic controller, in order to avoid wavelength superposition in the output fibers. Two signals coming from different inlets using the same wavelengths will be routed to different outlets, but if these outlets are multiplexed onto the same fiber, wavelength superposition can happen. We will now consider the realization of a shared buffer, obtained by means of recirculation lines. For this purpose R AWG ports are reserved to manage recirculation delay lines. These recirculation lines can make provision of different switching service classes more easily than pure input buffers, by dynamically W = R + NW k. Given the number of wavelengths per channel W and the number of recirculation ports R, the number of wavelengths fed to each AWG inlet k is expressed as k = NW W R, (1) or alternatively, given W and k, R is obtained from W(k N) R =, (2) k where obviously N, W, k and R must be integer values. Given these considerations, the switching matrix structure with R > 0isshowninFig. 6. UptoW packets on different wavelengths can be concurrently routed to each recirculation line. While allowing us to better exploit the buffering capacity of each delay line, this solution implies that before re-entering the AWG, the different wavelengths travelling through the FDL must be split and sent to different TWCs. W TWCs will be needed to implement a single recirculation line. Given that TWCs are among the most expensive components of this architecture, and a higher number of TWCs implies heavier work for the electronic controller, it would be useful to be able to reduce the number of components needed and therefore the node cost. Regrettably, the number of recirculation lines cannot be chosen freely, as pointed out by Eq. (1). So, in order to reduce the structure cost, P recirculation ports can be connected to each recirculation line, as

6 70 A. Pattavina / Optical Switching and Networking 1 (2005) Fig. 6. The switching matrix with recirculation lines. Packet transmission within the switch performed by the control electronics is carried out by a scheduling algorithm. For each new packet received by the node, the packet scheduling algorithm performs reservation of the transmission slots needed for the optical packet to cross the node without conflicts. Therefore a suitable delay is first selected in the FDL unit so that the new packet enters the switching matrix without conflicts with previous packets already in the delay line set serving the same input port. Such delay must also guarantee that an output port of the switching matrix leading to the desired switch outlet can be reserved for the slots required by the packet transmission. If recirculation lines are equipped in the switching node, packet recirculation is accomplished when access to one of these lines can be granted without conflicts before any the addressed outlets are available. Selecting a delay in the FDL and a given switch outlet from the AWG implies choosing a suitable wavelength in the TWC preceding the respective unit. 4. Simulation results Fig. 7. Recirculation line architecture with P > 1. shown in Fig. 7. Hence, the number of recirculation lines will be R/P and W/P TWCs per recirculation port will be required, for a total of WR/P + NW TWCs. Finally, in order to limit packet delay and power losses, packets are limited to a maximum number r max of loops inside recirculation lines. Moreover, it is assumed that only packets whose duration is less than D rec slots are allowed to perform more than one loop, so that packets cannot engage more than one recirculation line at a time. We now show some traffic performance results given by the different node architecture configurations obtained through computer simulation. All the performance figures plotted in this section, expressing either packet loss probability or average packet delay, are characterized by a 95% confidence interval not larger than 30% of the plotted value. Packet arrivals have been modelled as a Poisson process with negative exponential interarrival times. On the basis of measurement of real IP traffic [17], the following distribution of packet length, L, has been assumed: 1 p 0 = Pr(L = 40 bytes) = 0.6 p 1 = Pr(L = 576 bytes) = 0.25 p 2 = Pr(L = 1500 bytes) = 0.15 In this traffic model, the resulting average packet length is 393 bytes. Considering the optical packet format, in which the first slot of a multi-slot packet 1 The effect of a different distribution of packet lengths on a similar switch that does not support multi-wavelength switching has been studied in Ref. [18].

7 A. Pattavina / Optical Switching and Networking 1 (2005) Fig. 8. The packet loss probability of a switching node with W = 32 and different values of N. is engaged by the optical packet header, the three IP packet lengths correspond to 1, 12 and 31 slots. How the maximum input buffer delay D max and the chosen AWG size affect the node performance, in the case of pure input buffering (i.e. R = 0), has been deeply analyzed in Ref. [8]. There it was shown that the node performance improves selecting large values of D max and, more importantly, employing AWGs of large size, compared to the number of fibers N. In fact, given the same offered load per optical channel and a maximum number of packets to be switched (i.e., the AWG size N G), a better performance is given when fewer output lines (N) can be addressed by more packets (G). This phenomenon is well known in multipleserver systems under the name of channel grouping. In our case of a single-plane multi-wavelength switch, in which each AWG output can carry multiple packets (up to N), the same channel grouping phenomenon occurs. Let us compare different switch configurations characterized by the same number of wavelengths W = 32 and different switch sizes N = 2, 4, 8, 16, in a structure without shared queueing (R = 0) and with fixed input buffer depth D max = 8T. The packet loss probability of this configuration is shown in Fig. 8: performance improves as N decreases, since a larger number of packets can share a larger number of output lines, given that the load per channel is the same. Now we will focus on how the number of recirculation ports, R, and the recirculation line delay, D rec, affect the overall packet loss performance of Fig. 9. The packet loss probability of a switching node with D rec = 0, 16T and different values of R. the node. To this end we have chosen to consider structures which employ a AWG. 2 Given this AWG port count, the number of wavelengths per channel has been set to W = 12 and the number of input/output fibers to N = 2. When not otherwise indicated, the input FDL maximum delay is D max = 8T, the maximum number of loops is r max = 10 and the number of recirculation lines per recirculation port is P = 1. Given these values of W and N, we can develop different configurations of the switching matrix. In fact, if we use Eq. (2) with the different valid values of k (i.e. k N and k divides W, which means k ={2, 3, 4, 6}), we can derive the corresponding values of R ={0, 4, 6, 8}. We first examine the effect of a shared buffer with large delays with respect to the input buffer, by initially assuming the recirculation delay to be D rec = 16T. Figs. 9 and 10 show the packet loss probability and the average packet delay of delivered packets. As can be seen, the node loss probability lowers with the implementation of the shared buffer, while the delays grow. This behaviour is quite expected, since the overall buffer capacity is increased. What could be surprising is that, while the average delay grows with the number of recirculation ports, the loss probability benefits from the introduction of recirculation lines, but the benefit is better for small 2 This value has been chosen in order to give us the possibility of comparing different architecture implementations, with varying values of R and k.

8 72 A. Pattavina / Optical Switching and Networking 1 (2005) Fig. 10. The average packet delay of a switching node with D rec = 16T and different values of R. Fig. 11. The packet loss probability of a switching node with D max = 8T, 16T and different values of R. values of R. These can be explained by these two effects of R and k parameters: (1) the smaller the value of R, the smaller the value of k, and therefore the greater the number of wavelengths (W/k) that can be used to route a packet from a given inlet to a given outlet; so, for large values of R, more wavelengths are multiplexed onto the same AWG inlet, and fewer routes are available for the indexed output fiber; (2) when a packet is routed to a recirculation line, it re-enters the AWG after a time interval D rec from a different inlet; so, a different set of wavelengths will be available to route this packet to its output fiber. Hence, effect 1 implies that higher values of R lead to higher delays; in fact more packets will need to be routed to a recirculation line, since fewer packets can be routed to the desired fiber after entering the AWG from the input buffer stage. Higher loss probability values are also implied, since the channel grouping phenomenon is less exploited. On the other hand, effect 2 implies that the introduction of recirculation lines can lead to a smaller loss probability due to the possibility of using different sets of wavelengths to route the packets. In the case examined, R = 4isa balance between the two effects, which leads to the lowest packet loss probability. In order to validate the assumptions drawn in effect 2, the previous structures have been simulated setting D rec = 0. This means that all packets perform no or one loop, since no packet can have duration shorter than D rec. Moreover, packets travelling through a recirculation line are then transmitted in the same time slot in which they enter the AWG, and therefore no shared buffering is performed. The loss probability results, still as shown in Fig. 9, show that different values of R do not affect the improvement given by adopting shared buffering with null delay. Therefore it is the shared buffer depth that provides most of the performance improvement when shared queuing is adopted. A deeper insight into the switch performance can be obtained by comparing different depths of the input buffer for a given recirculation line delay, i.e. D rec = 16T. Fig. 11 compares the switch performance with the two maximum buffer sizes D max = 8T, 16T for the three values of numbers of recirculation lines R = 4, 6, 8. The availability of a deeper input buffer improves loss performance by even an order of magnitude for the largest size of the shared buffer and a low offered load. We evaluate now the effect of the recirculation delay D rec. On the basis of the behavior previously observed, Figs. 12 and 13 show the packet loss probability and the average packet delay of a switching node with R = 4 and different values of D rec ranging from 2T to 32T. As was expected, the packet loss probability diminishes and the delay increases when D rec grows. Average packet delay grows with offered load and with shared buffer depth; this last parameter affects delay much more for higher levels of offered

9 A. Pattavina / Optical Switching and Networking 1 (2005) Fig. 12. The packet loss probability of a switching node with R = 4 and different values of D rec. Fig. 14. Packet loss probability of a switching node with R = 6, D rec = 16T and different values of P. Fig. 13. The average packet delay of a switching node with R = 4 and different values of D rec. load. Interestingly enough, most of the improvements in packet loss probability can be obtained when the shared buffer capacity is large enough, in our case D rec = 16T, 32T. The explanation is that the delay D rec = 16T makes it possible for packets with medium size (L = 576 bytes) to be recirculated more than once; analogously a delay D rec = 32T enables recirculation of all packets, thus including the longest packets (L = 1500 byte). In fact in these cases the recirculation line delay is larger than the packet transmission time. The effect of the possible values that can be assumed by the shared FDL multiplexing parameter P can be investigated as follows. We consider a switching node with R = 6 recirculation ports with delay D rec = 16T. This value of R enables us to choose among different values of P, i.e. P ={1, 2, 3, 6}. Fig. 14 shows how the packet loss probability grows as the multiplexing parameter P grows. This is due to the fact that by multiplexing more than one AWG outlet onto the same delay line, we are reducing the shared buffer capacity, since at most W packets can concurrently travel through each recirculation line, while keeping constant R and therefore also the number k of wavelengths multiplexed onto each AWG inlet. Hence, when trying to reduce node costs, it is preferable to reduce the recirculation lines R rather than increasing the multiplexing factor P. This parameter can be used if the smallest value of R allowedbyeq.(2) is still too large to meet cost requirements. Finally, given the results obtained, we compare the effectiveness of pure shared buffering with respect to pure input buffering. For this purpose, we will consider an input-buffered node, with D max = 8T and R = 0, and a pure shared-buffered node with D max = 0, the same maximum delay and the same buffer capacity (i.e. the number of packets which can be concurrently buffered) as the input-buffered solution. So, since in the pure input-buffered structure one packet in each time slot can be buffered at each node input, the buffer capacity is NW. Since in the pure shared-buffered architecture, RW/P packets can be buffered in each time slot, we set the

10 74 A. Pattavina / Optical Switching and Networking 1 (2005) Fig. 15. The packet loss probability of pure input-buffered and pure shared-buffered node architectures. Fig. 16. The average packet delay of pure input-buffered and pure shared-buffered node architectures. following constraint: R/P = N. (3) In order to obtain the best node performance, we set R = 4 and therefore P = 2, since N = 2. As far as the recirculation delay is concerned, since our aim is to obtain a maximum achievable delay of 8T,the value of D rec will vary in the set {T, 2T, 4T, 8T } and the maximum number of loops r max, correspondingly, in {8, 4, 2, 1}, sod rec r max = 8T. Figs. 15 and 16 show, respectively, the packet loss probability and the average packet delay of these node configurations. As can be seen, the node performances are quite similar in all the cases considered. The different behavior given by input buffers compared to shared buffers is observed mostly in packet delays: at low loads similar delays are experienced, whereas the sharedbuffered architecture gives smaller delays under heavy traffic conditions. This behavior can be expected from any multiple-server system that shares resources among all users. Furthermore, it can be observed that the delay performance degrades as the recirculation line becomes longer, even if fewer recirculations are allowed. Apparently, less delay can be experienced whenever the real number of recirculations is smaller than the maximum one (recall that D rec r max is constant). For example, one recirculation with D rec = 8T implies eight slots of delay, whereas only eight recirculations of a packet with D rec = T match that delay value. Any other smaller number of recirculations for this latter case determines a smaller packet delay. These observations are based on a comparison between two configurations, pure input queueing and pure shared queueing, having the same buffer capacity. It is worth remarking that different conclusions could be drawn if the constant parameter is buffering complexity. With input queueing the complexity could be expressed as the number of FDLs on the input side, that is NW. On the other hand R/P = N FDL lines are needed with shared queueing. 3 Thus shared queueing is to be preferred over input queueing as there is a smaller performance degradation of the former compared to the latter, but shared queueing is much less complex than input queueing. 5. Conclusions In this paper an OPS node architecture has been described that fully exploits the AWG properties and allows the implementation of a shared buffer in addition to traditional input buffers. It has been shown how the implementation of these recirculation lines can lead to a smaller loss probability. The number of recirculation lines, however, should not be set to a large value, since this would reduce the node capability of resolving contentions in the wavelength domain. 3 The TWC are the same for the two structures and multiplexing devices are disregarded.

11 A. Pattavina / Optical Switching and Networking 1 (2005) Moreover, the performance of different configurations with the same overall buffer capacity has been compared for a pure input-buffered node and for a pure shared-buffered node. While the packet loss probabilities obtained are quite similar, different behaviors can be observed as far as packet delay is concerned. References [1] M. Yoo, C. Qiao, Just-enough-time (JET): a high speed protocol for bursty traffic in optical networks. in: Proc. IEE/LEOS Tech. for a Global Info Infrastructure, August 1997, pp [2] C. Qiao, Labeled optical burst switching for IP-over-WDM integration, IEEE Communications Magazine 38 (9) (2000) [3] C. Guillemot et al., Transparent optical packet switching: the European ACTS KEOPS project approach, IEEE Journal of Lightwave Technology 16 (12) (1998) [4] L. Dittman et al., The European IST project DAVID: a viable approach toward optical packet switching, Architecture and performance of AWG-based optical switching nodes for IP networks, Journal on Selected Areas in Communications 21 (7) (2003) [5] A. Carena, M.D. Vaughn, R. Gaudino, M. Shell, D.J. Blumenthal, An optical packet experimental routing architecture with label swapping capability, IEEE Journal of Lightwave Technology 16 (12) (1998) [6] D.K. Hunter, K.M. Guild, J.D. Bainbridge, WASPNET: a wavelength switched packet network, IEEE Communications Magazine 37 (3) (1999) [7] M.C. Chia, D.K. Hunter, I. Andonovic, P. Ball, S.P. Ferguson, K.M. Guild, M.J. O Mahony, Packet loss and delay performance of feedback and feed-forward arrayedwaveguide grating-based optical packet switches with WDM inputs outputs, IEEE Journal of Lightwave Technology 19 (9) (2001) [8] S. Bregni, A. Pattavina, G. Vegetti, Architecture and performance of AWG-based optical switching nodes for IP networks, Journal on Selected Areas in Communications 21 (7) (2003) [9] M. Nord, Waveband based multi-plane optical packet switch with partially shared wavelength converters, in: Proceedings of 8th Working Conference on Optical Network Design and Modeling (ONDM), Ghent, [10] F. Dorgeuille, B. Mersali, M. Feuillade, S. Sainson, S. Slempkès, M. Fouche, Novel approach for simple fabrication of high-performance InP-switch matrix based on laser amplifier gates, IEEE Photonics Technology Letters 8 (1996) [11] S. Bregni, G. Guerra, A. Pattavina, Optical packet switching of IP traffic, in: Proceedings of 6th Working Conference on Optical Network Design and Modeling (ONDM), Turin, [12] A. Tzanakaki, M.J. O Mahony, Analysis of tunable wavelength converters based on cross-gain modulation in semiconductor optical amplifiers operating in the counter propagating mode, IEE Proceedings Optoelectronics 147 (2000) [13] M.W.K. Mak, H.K. Tsang, Polarization-insensitive widely tunable wavelength converter using a single semiconductor optical amplifier, IEE Electronics Letters 36 (2000) [14] C. Parker, S.D. Walker, Design of arrayed-waveguide gratings using hybrid Fourier Fresnel transform techniques, IEE Journal on Selected Topics in Quantum Electronics 5 (1999) [15] A. Stavdas, Architectures, technology, and strategy for gracefully evolving optical packet switching networks, Optical Networks Magazine 4 (3) (2003) [16] Y. Cheyns, E. Van Breusegem, C. Develder, D. Colle, M. Pickavet, P. Demesteer, Evaluating cost functions for OPS node architectures, in: Proceedings of 8th Working Conference on Optical Network Design and Modeling (ONDM), Ghent, [17] K. Thompson, G.J. Miller, R. Wilder, Wide-area Internet traffic patterns and characteristics, IEEE Network 11 (6) (1997) [18] S. Bregni, A. Pattavina, G. Vegetti, Traffic performance of buffering strategies in all-optical nodes for IP networks, in: Proceedings of High Performance Switching and Routing Conference (HPSR), Turin, 2003.