INT 1011 TCP Offload Engine (Full Offload)

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1 INT 1011 TCP Offload Engine (Full Offload) Product brief, features and benefits summary Provides lowest Latency and highest bandwidth. Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx or Altera FPGAs. FPGA Development Board available INT 1011 is highly flexible that is customizable for layer-3, layer-4, layer-5 network infrastructure and network security systems applications. It is recommended for use in, among others, high performance Servers, NICs, SAN/NAS and data center applications. It provides the key IP building block for a single high performance Giga bit Ethernet ASIC/ASSP/FPGA. INT 1011 provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others INT 1011 can process TCP/IP, for in-line network security appliances, sessions in both directions, simultaneously, at full G-bit rate. This relieves the host CPU from costly TCP/IP buffer stack execution and maintenance tasks. INT 1011 can process TCP/IP sessions and has the capability to process other relevant protocols such as FTP, UDP, ICMP, TFTP etc on all inbound as well as outbound traffic simultaneously without compromising performance at sustained Gigabit speeds. Ideal for high performance and mid performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications Less than 8000 Xilinx slices, Altera ALMs or 150,000 ASIC gates + on-chip memory Fully integrated 100 M bit/1-g bit high performance GEMAC. Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance. Hardware implementation of TCP/IP stacks control plane and data plane. Hardware implementation of ARP protocol. ARP Protocol in Hardware; table creation, deletion. Customizable for IP-protocol only. Capture, filter, store and monitor TCP- Ports (optional) Capture, filter, store and monitor all IP addresses (opt) Santa Clara, CA Ph: , Fax:

2 On-chip DDR or SSRAM memory controller which can address from 4K Bytes to 4 MB Bytes on chip or 256 MB off chip memories (User customizable, optional) User FIFO interface for application data storage Many trade-offs for some functions performed in hardware or software Configurable Packet buffers, session table buffers On-chip or Off-chip memories, attached DDR I/II interface. Depending on system, performance, ASIC/FPGA size requirements-> User Customizable, (optional) Interfaces directly to GMII, RGMII, MII external 10/100/ 1000 Mbit Phy interfaces Architecture can be scaled up to 10-G bits Customizable to handle jumbo frames AMBA 2.0 bus interface for Local Processor control. PPC, MIPS and other CPU interfaces available User programmable/ prioritize-able interrupts Performs all connection/ session management tasks Monitors, Stores, Maintains and processes more than 1024 live TCP sessions. Customizable, depending upon on-chip memory availability. Extendable to 4K TCP sessions. Internal Memory dependent. Wire-speed 2-Gbps performance at full duplex Can be expanded to process up to 64K connections per sec. TCP + IP check sum generation and check performed in hardware in less than 6 clks (30 ns at 200 MHz) vs 1-2 us by typical software TCP-stack Connection set up and tear down/termination User programmable Session table parameters Dedicated set of hardware Timers for each TCP/IP session or customizable for sharing stale sessions. Multiple slot storage for fragmented packets. More slots allocated when more Onchip Memory available. Self-checking available memory logic. (optional) Out of sequence packet detection/storage and Reassembly/Segmentation (optional) Direct Data placement in Applications buffer at full wire speed without CPU-> reduces CPU s buffer copy time and utilization by 95% Adheres to RFCs; 793, 1500, 1700, 813, 791, 2001 Sliding Window mechanism implemented in hardware allowing total Flow Control Slow start transfer control in hardware Future Proof- Flexible implementation of TCP Offload Accommodates future Specifications changes. Santa Clara, CA Ph: , Fax:

3 Basic mini API available GEMAC GMII GMII Filters Blk (opt) Rx-I/F Tx-I/F Hdr/Flgs Processing Protocol Processor Rx/Tx -Pkt Sequence/Slot Que- Mgr Ext Mem 16/32/64 M Or FIFO 32/64/128K User Data Bus 32/64 bit Session Processor 4/8 RDMA Engines SRAM Ctl Ext Mem Ctl DDRx (opt) Packet Mem 32/64/128 K ea. Regs Block AMBA 2.0 Flash/ EEPROM Ext.(opt) User Control Bus. AMBA 2.0 Simplified Block Diagram Santa Clara, CA Ph: , Fax:

4 Specifications brief: Functionality Proven in multiple IDS/IPS appliances Complete header and flag processing of TCP/IP sessions in hardware accelerates by 10x 20x TCP Offload Engine- 2G b/s Wire-speed performance Scalable to 10 G b/s TCP + IP check sum- hardware TCP segmentation/reassembly in hardware(opt) Multiple slot storage for fragmented packets Out of sequence packet detection/storage/reassembly(opt) TCP port address tracking (Opt) Automatic DMA MAC Address search logic/filter (optional) IP address search logic/filter (optional) Accelerate security processing, Storage Networking- TCP RDMA- Data placement in Applications buffer -> reduces CPU utilization by 90 % Future Proof- Flexible implementation of TCP Offload Accommodates future Specifications changes. AMBA features; Basic transfers Various Transfer types Master/slave Bus Arbitration (optional) AHB bus slave transactions AHB bus master transactions (optional) AHB address decoder AHB arbiter (optional) System Endianness: Little-Endian Deliverables: - Verilog source code or NetList. - Verilog models for various components e.g. TCP/IP (transaction model) EMAC, memory interface etc. (opt) - TCP Model (opt) - Verification suite (opt) - Test packet-traffic suite (opt) Detailed specs available under NDA Santa Clara, CA Ph: , Fax:

5 Example boards: Xilinx Altera TOE - FPGA Altera Stratix III, IV, V Stratix; 2 Or ALE ~7456 ~3256 ~ Verilog /Altera Quatus 8.1 Quatus 8.1 Santa Clara, CA Ph: , Fax: