Accurate Synchronization of EtherCAT Systems Using Distributed Clocks

Transcription

1 Accurate Synchronization of EtherCAT Systems Using Distributed Clocks Joseph E Stubbs, PE EtherCAT Technology Group 12/2010 EtherCAT Technology Group (1)

2 Purpose of this presentation Gain a basic understanding of how the Distributed Clocks (DC) synchronization method of EtherCAT works. Understand how devices designed with EtherCAT DCs can benefit the user. 12/2010 EtherCAT Technology Group (2)

3 Agenda Distributed Clocks definition Important EtherCAT functional principles Overview of DC functionality How it works Propagation delay measurement Setting of Reference Clock Setting of Slave Clocks Drift compensation Master compensation (shift time) Practical applications of DCs in slave devices 12/2010 EtherCAT Technology Group (3)

4 DCs definition Distributed Clocks (DCs) refers to a logical network of synchronized, distributed local clocks in the EtherCAT fieldbus system. By using distributed clocks, EtherCAT, the real-time Ethernet protocol, is able to synchronize the time in all local bus devices within a very narrow tolerance range, typically below 100ns. The controller is a software stack on an industrial PC, using a standard Ethernet NIC. No special card required. 12/2010 EtherCAT Technology Group (4)

5 Why Synchronize a Network? Common time value in all devices allows synchronous gathering of input data from devices Example -- When device 1 was at position X, device 2 was at position Z. Cyclic behavior with tight temporal tolerances Example position control of a drive. Exact position input for each time slice produces tighter coordinated motion or speed. Example data acquisition at high data rates Response to external event Example -- Exact time alarm when received can be used to reject bad product downstream with respect to conveyor speed with little loss of good product Example -- Seeing events that would be missed in classical scanning of I/O systems Act at exact future time Example -- All drives begin execution of new command at exact time Example -- Simultaneous outputs for devices separated by long distances in same network 12/2010 EtherCAT Technology Group (5)

6 Functional Principles EtherCAT utilizes several important operating principles allowing DCs to be implemented efficiently and elegantly Processing On the Fly Protocol processed in hardware Fixed frame path for all frames in network in a given topology Latching of receive times in slave ports and logical processing unit Instruction set that lends itself to distributing times and offsets easily A DC unit built-in to the EtherCAT Slave Controller (ESC), which facilitates many of the functions in hardware External interfaces from the DC unit 12/2010 EtherCAT Technology Group (6)

7 Functional Principle: Ethernet on the Fly Slave Device Slave Device EtherCAT Slave Controller EtherCAT Slave Controller Process data is extracted and inserted on the fly Compilation of process data can change in each cycle, e.g. ultra short cycle time for axis, and longer cycles for I/O update possible In addition asynchronous, event triggered communication Up to 65,535 devices on one EtherCAT network 12/2010 EtherCAT Technology Group (7)

8 Frame Processing Order on the System EtherCAT Segment Master Cable EtherCAT Frame Path 12/2010 EtherCAT Technology Group (8)

9 Important things to keep in mind Only the EtherCAT master (controller) can create a frame Slaves can only modify the frame(s) The frame is not actively routed to a particular node. The frame travels through the entire network regardless of which node is addressed within the frame. One frame can service an entire network. Multiple frames can be sent out back-to-back to service larger networks which exceed 1500 bytes in process data length. 12/2010 EtherCAT Technology Group (9)

10 Distributed Clocks Unit SPI / µc parallel Digital I/O IRQ Sync1 / Latch1 Sync0 / Latch0 EtherCAT Address Space Process Data Interface (PDI) FMMU n Sync / Latch Unit SyncMan DC Control Offset EtherCAT Processing Unit and Auto-Forwarder with Loop Back Port 0 Port 1 Port 2 Port 3 System Time Delay Distributed Clocks EtherCAT Slave Controller (ESC) RJ45 Mag PHY PHY Mag RJ45 12/2010 EtherCAT Technology Group (10)

11 Distributed Clocks Features Definition of a System Time Beginning on January, 1 st 2000 at 0:00h on power-up Base unit is 1 ns 64 bit value (enough for more than 500 years) Lower 32 bits spans over 4.2 seconds Normally enough for communication and time stamping Definition of a Reference Clock One EtherCAT Slave will be used as a Reference Clock Reference Clock distributes its Clock cyclically Reference Clock adjustable from a global Reference Clock IEEE /2010 EtherCAT Technology Group (11)

12 DC Propagation Delay Measurement EtherCAT Node measures time difference between leaving and returning frame EtherCAT Frame Processing Direction EtherCAT Frame Forwarding Direction 12/2010 EtherCAT Technology Group (12)

13 Propagation Delay Measurement Registers: Receive Time Port 0 (ADO: 0x0900:0x0903) Receive Time Port 1 (ADO: 0x0904:0x0907) Receive Time Port 2 (ADO: 0x0908:0x090B) Receive Time Port 3 (ADO: 0x090C:0x090F) System Time Delay (ADO: 0x0928:0x092B) Write access to Receive Time Port 0 activates latch Latch local time of SOF (Start of Frame) At EOF (End of Frame) SOF time is copied to Receive Time Port X Receive Time Port X in local clock units (controlled) SOF time of all frames are latched on all ports internally Master reads all time stamps and calculates the delay times with respect to the topology. Individual delay time is written to register System Time Delay 12/2010 EtherCAT Technology Group (13)

14 DC Propagation Delay Measurement EtherCAT Node measures time difference between leaving and returning frame IPC 12/2010 EtherCAT Technology Group (14)

15 Propagation Delay Measurement The differences between the Reference Clock and each DC slave In port is Propagation Delay, called System Time Delay. Ref This value is distributed by the master stored in the slave for drift compensation calculations later. IPC t S S S S S S S 12/2010 EtherCAT Technology Group (15)

16 Binding Reference Clock to RTC Registers: System Time Offset (ADO: 0x0920:0x927, small systems 0x0920:0x0923) Difference between the Master RTC and Reference Clock is calculated by the master. This time is written to register System Time Offset of the Reference Clock only. 12/2010 EtherCAT Technology Group (16)

17 Binding Reference Clock to RTC Master sets Reference clock to RTC (or other source) RTC IPC Ref S S S S S S S 12/2010 EtherCAT Technology Group (17)

18 Offset Compensation Registers: System Time Offset (ADO: 0x0920:0x927, small systems 0x0920:0x0923) Difference between the Reference Clock and every slave device's clock is calculated by the master. The offset time is written to register System Time Offset Each slave calculates its local copy of the System time using its local time and the local offset value: t Local copy of System Time = t Local time + t Offset 12/2010 EtherCAT Technology Group (18)

19 Setting individual slaves to Reference Clock Master calculates offset between Ref Clock and individual local clocks. This value is distributed by the master and written to each slave in order to bring all local times to the same exact time. IPC Ref S S S S S S S 12/2010 EtherCAT Technology Group (19)

20 Drift Compensation DC Control RMW command (read multiple write) allows the master to read System Time of the reference clock and write it to all slave clocks within a single frame using the same frame route and therefore the same propagation delay as the initial measurement. DC Control Write access to System Time compares received Time with local time t = (t Local time + t Offset - t PropagationDelay ) t Received System Time If ( t > 0) then decelerate local clock (each tick counts as less time) else if ( t < 0) accelerate local clock (each tick counts as more time) 12/2010 EtherCAT Technology Group (20)

21 Drift Compensation The frequency of issuing the RMW command determines the amount of drift allowed in the system clocks Master commands the Reference clock to distribute its local time to all nodes occasionally. IPC Ref S S S S S S S 12/2010 EtherCAT Technology Group (21)

22 Drift Compensation DC Control Because the RMW instruction distributes the reference clock time each time the instruction is called and because the propagation delay of the system does not change we do not need to have jitter-free frames to have a jitter free system! Therefore, no special master card is required, the master can be a software stack even for the most tightly synchronized applications. 12/2010 EtherCAT Technology Group (22)

23 Long Term Scope View of Two Separated Devices 300 Nodes in between, 120m Cable Length Interrupt Node 1 Simultaneousness: ~15 ns Jitter: ~ +/-20ns Interrupt Node /2010 EtherCAT Technology Group (23)

24 Example features of EtherCAT DCs Clock synchronization between the EtherCAT slaves and the master Synchronous generation of local output signals (Sync signals) Precise time stamping of input signals (Latch signals) Generation of synchronous interrupts to local microprocessors (IRQ signals) 12/2010 EtherCAT Technology Group (24)

25 Action based on specified time: Sync 0/1 The distributed clock unit in the ESC usually features 2 pins that can be triggered time-controlled. SYNC0 and SYNC1. In this case the compare unit in the ESC would be active: If the local distributed clock time matches a user-defined enable time the ESC triggers the associated Sync pin(s). This behaviour can be set up to be single shot or cyclic, with or without an acknowledge. DC Control Delay PDI IRQ Offset System Time Sync0 Sync Unit Latch Unit Sync1 Distributed Clocks 12/2010 EtherCAT Technology Group (25)

26 Reaction to an external signal - Latch 0/1 If an ESC is configured accordingly it can store the current local time if an external event occurs, i.e. it can place it into a buffer without delay using a capture unit. Can be configured for rising and/or falling edge, and single event or continuous latch Examples for such external events are edge on a dedicated pin of the ESC (Latch 0/1), arrival of the EtherCAT frame, end of the EtherCAT frame, communication with a connected microcontroller, and a wide range of other options. DC Control Delay Offset System Time Latch0 Sync Unit Latch Unit Latch1 Distributed Clocks 12/2010 EtherCAT Technology Group (26)

27 Example of Latch and Sync Use 1 + Tx 1 +Ty 1 + Tz IN Latch Timestamp 1 + T1 1 +T2 1 + T3 Constant OUT Timestamp? OUT Classical Controls Constant 12/2010 EtherCAT Technology Group (27)

28 Connection to an External Logic - IRQ An ESC can not only be used as a standalone unit, it also has interfaces for communicating with other electronic units such as a microcontroller or other driver circuitry. Communication via these interfaces can also be controlled via distributed clocks in order to ensure synchronous, highprecision sampling of input parameters, or cyclic interrupts based on a multiple of the base scan rate. Examples for this use include interfacing to a microprocessor controlling a power drive, electronic shaft encoder analyzer, or data acquisition slaves for condition monitoring. DC Control Delay PDI IRQ Offset System Time Sync0 Sync Unit Latch Unit Sync1 Distributed Clocks 12/2010 EtherCAT Technology Group (28)

29 Example of IRQ Use with a µc -- Oversamplin Oversampling fast measurements Measurement cycle Fast signal sampling Analog value recording (input) Analog value generation (output) Base Network cycle Base Network cycle /2010 EtherCAT Technology Group (29)

30 Summary Tight clock synchronization between the EtherCAT slaves and the master is possible without the use of a special fieldbus card The DC features of devices are enabled by both the unique communication principles of EtherCAT and built-in features of the ESCs. Some of the common behaviors built in to devices are: Synchronous reading of input signals Precise time stamping of input signals (Latch signals) Generation of synchronous interrupts to local microprocessors (IRQ signals) For more information about how EtherCAT works, please see 12/2010 EtherCAT Technology Group (30)

31 Please visit for more information EtherCAT Technology Group Headquarters Ostendstraße Nuremberg, Germany Phone: EtherCAT Technology Group North America PO Box 1305 Port Orchard, WA Phone: /2010 EtherCAT Technology Group (31)