ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures. Introduc1on. Prof. Natalie Enright Jerger

Transcription

1 ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures Introduc1on Prof. Natalie Enright Jerger Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 1

2 Interconnec1on Networks Introduc1on How to connect individual devices together into a community of communica1ng devices? Device: Component within a computer Single computer System of computers End Node End Node End Node End Node Device Device Device Device Link Link Link SW Interface SW Interface SW Interface SW Interface HW Interface HW Interface HW Interface HW Interface Link Types of elements: Interconnec(on Network end nodes (device + interface) links interconnec1on network Internetworking: interconnec1on of mul1ple networks Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 2 Slide courtesy Timothy Mark Pinkston and José Duato

3 Interconnec1on Networks Introduc1on Interconnection networks should be designed to transfer the maximum amount of information within the least amount of time (and cost, power constraints) so as not to bottleneck the system Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 3

4 Why study interconnects? They provide external connec1vity from system to outside world Also, connec1vity within a single computer system at many levels I/O units, boards, chips, modules and blocks inside chips Trends: high demand on communica1on bandwidth increased compu1ng power and storage capacity switched networks are replacing buses Computer architects/engineers must understand interconnect problems and solu7ons in order to more effec7vely design and evaluate systems Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 4 Slide courtesy Timothy Mark Pinkston and José Duato

5 Types of Interconnec1on Networks Interconnec1on networks can be grouped into four domains Depending on number and proximity of devices to be connected On- Chip networks (OCNs or NoCs) Devices include microarchitectural elements (func1onal units, register files), caches, directories, processors Current designs: small number of devices Ex: IBM Cell, Sun s Niagara Projected systems: dozens, hundreds of devices Ex: Intel TeraFLOPS research prototypes cores Proximity: millimeters Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 6 Slide courtesy Timothy Mark Pinkston and José Duato

6 System/Storage Area Networks (SANs) Mul1processor and mul1computer systems Interprocessor and processor- memory interconnec1ons Server and data center environments Storage and I/O components Hundreds to thousands of devices interconnected IBM Blue Gene/L supercomputer (64K nodes, each with 2 processors) Maximum interconnect distance tens of meters (typical) a few hundred meters (some) InfiniBand: 120 Gbps over a distance of 300 m Examples (standards and proprietary) InfiniBand, Myrinet, Quadrics, Advanced Switching Interconnect Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 7 Slide courtesy Timothy Mark Pinkston and José Duato

7 Local Area Network (LANs) Interconnect autonomous computer systems Machine room or throughout a building or campus Hundreds of devices interconnected (1,000s with bridging) Maximum interconnect distance few kilometers few tens of kilometers (some) Example (most popular): Ethernet, with 10 Gbps over 40Km Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 8 Slide courtesy Timothy Mark Pinkston and José Duato

8 Wide Area Networks (WANs) Interconnect systems distributed across the globe Internetworking support is required Many millions of devices interconnected Maximum interconnect distance many thousands of kilometers Example: ATM (asynchronous transfer mode) Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 9 Slide courtesy Timothy Mark Pinkston and José Duato

9 Interconnec1on Network Domains Distance (meters) 5 x x x 10 0 LANs SANs WANs 5 x 10-3 OCNs ,000 10,000 >100,000 Number of devices interconnected Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 10 Slide courtesy Timothy Mark Pinkston and José Duato

10 Course Overview Focus on On- Chip Networks Two aspects: Interconnec1on network basics Lectures covering: topology, rou1ng, flow control and router microarchitecture Second part: Mix in current OCN research with each lecture topic Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 11

11 Moore s Law: Double the number of transistors on chip every 2 years Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 12 Chart courtesy Intel Corp.

12 What is Tera- scale? TIPs of compute power opera1ng on Tera- bytes of data Entertainment TIPS Source: electronic visualiza1on lab University of Illinois Learning & Travel Performance GIPS MIPS 3D & Video Multi- Media RMS Personal Media Crea(on and Management KIPS Text Health Kilobytes Megabytes Gigabytes Terabytes Dataset Size Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 13 hip://techresearch.intel.com/ar1cles/tera- Scale/1421.htm [Ack. Jim Held, Intel Fellow]

13 Performance Scaling Challenges Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 14 [Ack. Jim Held, Intel Fellow]

14 Processor power skyrocke1ng Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 15 [Ack: Fred Pollack, Intel Fellow, 1996]

15 Mul1- core chips the answer to the power problem Cache Large Core Power 4 3 Performance 2 2 Small 1 1 Core Power = 1/4 Performance = 1/2 1 1 C1 C3 Cache C2 C Mul1- Core: Power efficient Beier power and thermal management Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 16 [Ack. Shekhar Borkar, Intel Fellow]

16 Tera- scale Research Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 17 [Ack. Jim Held, Intel Fellow]

17 On- Chip Networks (OCN or NoCs) Why On- Chip Network? Ad- hoc wiring does not scale beyond a small number of cores Prohibi1ve area Long latency OCN offers scalability efficient mul1plexing of communica1on onen modular in nature (ease verifica1on) Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 19

18 Differences between on- chip and off- chip networks Significant research in mul1- chassis interconnec1on networks (off- chip) Supercomputers Clusters of worksta1ons Internet routers Leverage research and insight but Constraints are different Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 20

19 Off- chip vs. on- chip Off- chip: I/O boilenecks Pin- limited bandwidth Inherent overheads of off- chip I/O transmission On- chip Wiring constraints Metal layer limita1ons Horizontal and ver1cal layout Short, fixed length Repeater inser1on limits rou1ng of wires Avoid rou1ng over dense logic Impact wiring density Power Consume 10-15% or more of die power budget Latency Different order of magnitude Routers consume significant frac1on of latency Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 21

20 On- Chip Network Evolu1on Ad hoc wiring Small number of nodes Buses and Crossbars Simplest variant of on- chip networks Low core counts Like tradi1onal mul1processors Bus traffic quickly saturates with a modest number of cores Crossbars: higher bandwidth Poor area and power scaling Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 22

21 Mul1core Examples (1) XBAR Sun Niagara Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 23

22 Mul1core Examples (2) RING Element Interconnect Bus 12 elements 4 unidirec1onal rings 16 Bytes wide Operate at 1.6 GHz IBM Cell Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 24

23 Many Core Example 2D MESH Intel TeraFLOPS 80 core prototype 5 GHz Each 1le: Processing engine + on- chip network router Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger)

24 Many- Core: Intel SCC Intel s Single- chip Cloud Computer (SCC) uses a 2D mesh with state of the art routers Will discuss in detail later in lecture Poten1al plaqorm for project Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 26

25 Performance and Cost Latency (sec) Zero load latency Offered Traffic (bits/sec) Performance: latency and throughput Cost: area and power Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 27 Satura1on throughput

26 Course Informa1on Website: index.html Lecture: Wed 10-12, BA 4164 Contact Informa1on: Office: 374A Prai Stop by or send me for appointment Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 28

27 Course Format ~5 weeks of lecture Covering material from book: On- Chip Networks Available for free download (within UofT) Remaining weeks: Presenta1on of research papers by you Should be interac1ve/foster discussion Cri1ques (1 page) iden1fy one idea in paper that is major contribu1on or major limita1on describe new idea (of yours) that builds on paper Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 29

28 Course Marking Scheme Evalua1on Scheme: Presenta1on: 20% Cri1ques: 35% Project: 45% Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 30

29 Course Project Propose your own topic Topics do not need to be limited to OCN Look for ways to relate OCN to your research Re- evaluate recent paper (or compare 2 papers) Can use a paper from class Or see bibliographic notes in book for ideas Or check out recent conferences: ISCA, MICRO, HPCA, NOCS etc. Can work in groups of 2 Project must be sized accordingly Enrolled in 1755? Parallel Computer Architecture and Programming Do one larger project that spans both classes Must get approval from Prof. Steffan as well See website for details Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 31

30 Next Time Look at Topology Discuss various poten1al projects Not too early to start thinking about your project and bring ques1ons Send me e- mail/stop by if you want to discuss your project early Project should Reinforce/enhance class material Add value to your research publish at conference/ workshop? Winter 2011 ECE 1749H: Interconnec1on Networks (Enright Jerger) 32