ECSE 425 Lecture 1: Course Introduc5on Bre9 H. Meyer

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1 ECSE 425 Lecture 1: Course Introduc5on 2011 Bre9 H. Meyer

ca Phone: 514-398- 4210 Office: McConnell 525 OHs: M 14h00-15h00; R

2 Staff Instructor: Bre9 H. Meyer, Professor of ECE bre9 dot meyer at mcgill.ca Phone: Office: McConnell 525 OHs: M 14h00-15h00; R 11h00-12h00; or, by appointment Teaching Assistant: Alexandre Raymond alexandre dot raymond at mail.mcgill.ca 2011 B. H. Meyer 2

3 What ECSE 425 is A course on the architecture of modern, high- performance computers What is computer architecture? The art and science of selec5ng and interconnec5ng hardware components to create a computer that sa5sfies applica5on requirements What we ll learn How to organize a processor for performance How other constraints (e.g., cost, power, etc.) influence computer design How to judge the resul5ng trade- offs quan%ta%vely 2011 B. H. Meyer 3

4 What ECSE 425 isn t [Credit: xkcd.com] 2011 B. H. Meyer 4

Semiconductor industry relies on constant improvement Architects must take growing resources and

5 Why is Architecture Interes5ng? Comp. architecture is the heart of comp. engineering Bigger, stronger, faster! Semiconductor industry relies on constant improvement Architects must take growing resources and deliver! UltraSPARC T2, 64 threads, 342 mm2 Clever design and organiza5on Remarkable insights and algorithms [Source: Sun; IBM] ECSE 425, Fall 2011, Lecture B. H. Meyer Power7, 32 threads, 576 mm2 5

t just make chips do more in the same 5me Reliability: must ensure chips do things right The effects of

6 Why is Architecture Challenging? Constraints conspire to make con5nual improvement difficult Cost: can t just make chips bigger Power: can t just make chips do more in the same 5me Reliability: must ensure chips do things right The effects of new architectural features are complex Evalua5on is complex, too! A good idea isn t enough: Implementable? Used enough to change metrics? [Source: IBM; AnandTech] 2011 B. H. Meyer 6

7 In This Course Fundamentals of computer design Pipelining Instruc5on- level parallelism (ILP) Memory hierarchy Mul5processor architecture and thread- level parallelism (TLP) Material based on H&P, 4 th edi%on 2011 B. H. Meyer 7

8 Grading 6 homework assignments (10%) Pencil and paper, some programming 1 project (30%) Evaluate architectural effects using SimpleScalar Significant C/C++ programming 2 midterm exams (30%) In class, closed book, 1 page of notes allowed 1 final exam (30%) Closed book, 2 pages of notes allowed 2011 B. H. Meyer 8

9 Homework Distributed on the course website h9p:// Due at the beginning of class No credit for late work! Without prior permission, of course And 2011 B. H. Meyer 9

10 Project Simulate the effect of architectural changes to a superscalar, out- of- order processor Simula5on framework SimpleScalar Wri9en in C Evalua5on using real benchmarks Work in pairs; consider early who to work with! Proposal Implementa5on Evalua5on Presenta5on Report 2011 B. H. Meyer 10

11 Historical perspec5ves on processors Late 1970s: Birth of microprocessor Single- chip processor, programmable controllers The decade of 1980s: Instruc%on set architecture RISC (Reduced Instruc5on Set Computer) Instruc5on pipelining, cache memories, compliers Worksta5ons The decade of 1990s: Instruc%on level parallelism Superscalar, specula5ve micro- architectures Low- cost desktop (super)computers The decade of 2000s: Mul%- core era Mul5- core architectures, power constrained designs Mobile/portable compu5ng, large servers / data centers Source: Stanford EE382a course slides by Prof. Christos Kozyrakis 2011 B. H. Meyer 11

12 Fundamentals of Computer Design Three principles Make the common case fast (Amdahl s law) Exploit parallelism (at all levels) Exploit locality (caches / memory hierarchy) How should performance be measured? What other factors affect an architecture? Latency Cost Power Reliability 2011 B. H. Meyer 12

13 Pipelining Just like an assembly line Ideally: one instruc5on per clock cycle Reality: overheads; hazards, dependencies stalls! 2011 B. H. Meyer 13

14 Instruc5on- Level Parallelism (ILP) Goal: exploit instruc5on independence to improve performance Challenge: hazards, dependencies stalls Branch predic5on: guess which execu5on path Instruc5on scheduling: reorder instruc5ons Specula5ve instruc5on execu5on Superscalar instruc5on execu5on: allow more than one instruc5on to complete at a 5me 2011 B. H. Meyer 14

15 Memory Hierarchy Maintaining the illusion of fast, infinite memory Mul5ple- level memory system Cache performance and op5miza5on Size, internal organiza5on, behavior, etc. Virtual memory organiza5on 2011 B. H. Meyer 15

16 Mul5processor Architecture ILP has limits; boost performance with thread- level parallelism! (TLP) Mul5ple- instruc5on, mul5ple- data machines (MIMD) Concurrently execute mul5ple threads in parallel New overheads: communica5on, synchroniza5on Two classes (physical memory structure) centralized memory mul5processors physically distributed- memory mul5processors Two models (memory architecture and communica5ons) shared memory mul5processors message- passing mul5processors 2011 B. H. Meyer 16

17 Next Time Fundamentals of Computer Design Read Chapter 1! No class Monday First homework out on Wednesday First tutorial the end of next week 2011 B. H. Meyer 17

ECSE 425 Lecture 25: Mul1- threading

ECSE 425 Lecture 25: Mul1- threading H&P Chapter 3 Last Time Theore1cal and prac1cal limits of ILP Instruc1on window Branch predic1on Register renaming 2 Today Mul1- threading Chapter 3.5 Summary of ILP: