Christophe HURIAUX. Embedded Reconfigurable Hardware Accelerators with Efficient Dynamic Reconfiguration
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1 Mid-term Evaluation March 19 th, 2015 Christophe HURIAUX Embedded Reconfigurable Hardware Accelerators with Efficient Dynamic Reconfiguration Accélérateurs matériels reconfigurables embarqués avec reconfiguration dynamique efficace 1 Christophe Huriaux Mid-term Evaluation March 19 th,
2 Outline Introduction Thesis context: FlexTiles in a nutshell Relocation: State of the Art Challenges Contributions Hardware Architecture CAD tools Side Activities Conclusion & Ongoing Work 2 Christophe Huriaux Mid-term Evaluation March 19 th,
3 Context: FlexTiles in a nutshell FlexTiles: Self adaptive heterogeneous manycore based on Flexible Tiles Provide a heterogeneous many-core architecture offering Large flexibility High-performance, energy efficiency Raised programming efficiency Self-adaptation through virtualization 3 Christophe Huriaux Mid-term Evaluation March 19 th,
4 Context: FlexTiles in a nutshell 3D-Stacked Heterogeneous manycore General Purpose Processors (GPP) for flexibility and programming homogeneity Network On Chip Dedicated hardware accelerators mapped at run-time on a reconfigurable layer Reconfigurable layer with seamless task migration capabilities Virtualization layer to provide an abstraction of the manycore and self adaptive services Tool-chain for parallelization and compilation 4 Christophe Huriaux Mid-term Evaluation March 19 th,
5 3D interface to the NoC DSP blocks Memory blocks 5 Christophe Huriaux Mid-term Evaluation March 19th,
6 State of the Art: Industry Predefined reconfigurable regions [Altera2010][Xilinx2013] Bit-stream depends on task location Use LUTs as interfaces with static logic I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O HW Accelerator #1 BS #1 HW Accelerator #1 BS #2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 6 Christophe Huriaux Mid-term Evaluation March 19 th,
7 State of the Art: Academic Online Rewrite of parts of the bit-stream [Horta2001] [Kalte2006] Time consuming, limited flexibility Offline calculations of possible differences [Touiza2012] [Beckhoff2014] Memory consuming Online place and route [Lysecky2004] Time and memory consuming No work on heterogeneous relocation! 7 Christophe Huriaux Mid-term Evaluation March 19 th,
8 Challenges Position-independent tasks Simple algorithms No predefined configuration domains Cope with the heterogeneity Resource sharing/distribution easiness How to move a task around the logic fabric? Dedicated CAD tool-flow Needed to validate the other contributions 8 Christophe Huriaux Mid-term Evaluation March 19 th,
9 Contributions Routing Reconf. Mem. Placement Routing Hardware Logic array Arch. model CAD efpga Bitstream RTL generation Architecture Controller Reconf. Algorithm Virtual Bit-Stream 9 Christophe Huriaux Mid-term Evaluation March 19 th,
10 Contributions: Hardware Homogeneous case No constraint on task placement Regular routing architecture Cope with heterogeneity RAM, DSP, 3D I/Os Migration is limited vertically to the same column to the next column containing same complex blocks Logic Element (LE) Configured LE Task 10 Christophe Huriaux Mid-term Evaluation March 19 th,
11 Contributions: Hardware Heterogeneous blocks routing is abstracted from logic routing Long lines allow a trade-off between placement flexibility and routing complexity A two-level routing is performed at runtime: Logic routing (as in the homogeneous case) Heterogeneous block routing through long lines 11 Christophe Huriaux Mid-term Evaluation March 19 th,
12 Contributions: Hardware Increase the flexibility of a task placement Implemented in a modified version of Versatile Place & Route (VPR) Evaluation on critical path delay and required routing resources: Only 2% delay increase in average 1.8x routing resources increase (need specialized routing algorithm for a more fair use) Dissemination FPL 14 [Huriaux2014] 12 Christophe Huriaux Mid-term Evaluation March 19 th,
13 Contributions: Architecture A task is synthesized, placed & routed into a Virtual Bit-Stream (VBS) Independent from task physical location in the fabric No predefined configuration domains A reconfiguration controller generates final BS at run-time Christophe Huriaux Mid-term Evaluation March 19 th,
14 Contributions: Architecture Island-style FPGA Logic grid Mesh routing lines Switch boxes Interconnect The VBS encode each island separately 14 Christophe Huriaux Mid-term Evaluation March 19 th,
15 Contributions: Architecture Each routing node is 6 or 3 transistors The bitstream is the state of each transistor bits in this example Christophe Huriaux Mid-term Evaluation March 19 th,
16 Contributions: Architecture The VBS abstracts the inner details of the routing The routes are encoded as a list of connections: (20 ; 8) (1 ; 9) (5 ; 18) Christophe Huriaux Mid-term Evaluation March 19 th,
17 Contributions: Architecture The VBS encoding is position independent The final bit-stream can be calculated from the VBS for differently routed network The online decoding algorithm is simple since the global routing has been determined offline The resulting VBS is 2.5x smaller than the equivalent raw bit-stream Up to 10x smaller using clusters of islands Dissemination: DATE 15 [Huriaux2015] Patent [Sentieys2014] 17 Christophe Huriaux Mid-term Evaluation March 19 th,
18 Contributions: CAD tools Based on the Verilog-To-Routing (VTR) framework Allows to describe any island-style architecture and perform place and route operations Uses Versatile Place and Route Widely used for academic FPGA architecture research A custom backend reads the placement and routing data to generate Virtual Bit-Streams 18 Christophe Huriaux Mid-term Evaluation March 19 th,
19 Contributions: CAD tools High-level task description Mapped logic netlist High-level Synthesis Placer Router HDL task description RTL task description Placement data Routing data Arch. netlist HDL Synthesis Bitstream generation Flat logic netlist Arch. description Virtual bit-stream Technology mapping 19 Christophe Huriaux Mid-term Evaluation March 19 th,
20 Side Activities Teaching 64h IUT (analog electronics, computer engineering) 64h+64h ENSSAT (analog electronics, digital systems) Courses Scientific: 96h General: 46h 3 month mobility at University of Amherst (USA) with Pr. Russell Tessier (Summer 2014) Publication on FPGAs Trojans [Swierczynski2015] 20 Christophe Huriaux Mid-term Evaluation March 19 th,
21 Conclusion & Ongoing Work Summary Proposed a routing architecture to provide more flexibility for heterogeneous relocation Introduced the concept of a position-independent and compressed task bit-stream: the Virtual Bit-Stream (VBS) Developped the associated tool-flow to generate the VBS Elaborated an RTL model of the whole architecture Ongoing work Enhance the configuration method Dissemination on the CAD tools (ICCAD) Journal extension(s) 21 Christophe Huriaux Mid-term Evaluation March 19 th,
22 Q&A Thank you J Questions? 22 Christophe Huriaux Mid-term Evaluation March 19 th,
23 References [Altera2010] Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs, Altera Corporation, [Beckhoff2014] C. Beckhoff, D. Koch, and J. Torresen, Portable Module Relocation and Bitstream Compression for Xilinx FPGAs, in the Proceedings of the 24th conference of Field Programmable Logic, pp [Horta2001] E. Horta, J. W. Lockwood. PARBIT: a tool to transform bitfiles to implement partial reconfiguration of field pro- grammable gate arrays (FPGAs), Tech. Rep. WUCS-01-13, Washington University, [Huriaux2014] C. Huriaux, O. Sentieys, and R. Tessier, FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams, in the Proceedings of the 24th conference of Field Programmable Logic, pp [Huriaux2015] C. Huriaux, A. Courtay, O. Sentieys, Design Flow and Run-Time Management for Compressed FPGA Configurations, in the Proceedings of the 18 th DATE conference, to appear. [Kalte2006] H. Kalte and M. Porrmann, REPLICA2Pro: Task Relocation by Bit- stream Manipulation in Virtex-II/Pro FPGAs, in the Proceedings of the 3rd conference on computing frontiers (CF). ACM, 2006, pp [Lysecky2004] R. Lysecky, F. Vahid, and S. X.-D. Tan, Dynamic FPGA routing for just-in-time FPGA compilation, in the Proceedings of the 41th Design Automation Conference, 2004, pp [Sentieys2014] O. Sentieys, A. Courtay, C. Huriaux and S. Pillement, Method and Device for Programming an FPGA, EU Patent, filed on Jan Christophe Huriaux Mid-term Evaluation March 19 th,
24 References [Swierczynski2015] P. Swierczynski, M. Fybriak, and C. Paar, C. Huriaux, and R. Tessier, Protecting against Cryptographic Trojans in FPGAs, in the Proceedings of the 23rd IEEE International Symposium on Field- Programmable Custom Computing Machines, 2015, to appear. [Touiza2012] M. Touiza, G. Ochoa-Ruiz, E.-B. Bourennane, A. Guessoum, and K. Messaoudi, A novel methodology for accelerating bitstream relocation in partially reconfigurable systems, Microprocessors and Microsystems, vol. 37, no. 3, pp , [Xilinx2013] Partial Reconfiguration User Guide, UG702, Xilinx, Inc., Christophe Huriaux Mid-term Evaluation March 19 th,
25 FPL 14: Results Architecture based on a simplified Stratix IV with: Dual-port 144k memories Fracturable 36x36 multipliers Evaluation on two criteria Delay of the critical path Minimum channel width Number of tracks in the homogeneous routing channels Minimum channel width determined by VPR Not directly related to silicon area 25 C. Huriaux, O. Sentieys and R. Tessier September 3 rd,
26 FPL 14: Results Benchmark set: VTR framework circuits [1] Circuit # Mem # Mult # LB bgm ,174 boundtop 1 0 2,977 ch_intrinsics diffeq diffeq LU8PEEng mkdelayworker32b mkpktmerge mksmadapter4b or raygentop stereovision [1] Rose, Jonathan, Luu, Jason, Yu, Chi Wai, et al. The VTR project: architecture and CAD for FPGAs from verilog to routing. In Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays. ACM, p C. Huriaux, O. Sentieys and R. Tessier September 3 rd,
27 FPL 14: Results: Delay Estimation of the worst case delay Impossible to predict where connections to long lines will be done Some channels crossing fixed-function blocks are longer 27 C. Huriaux, O. Sentieys and R. Tessier September 3 rd,
28 FPL 14: Results: Delay ns 160,00 140,00 120,00 100,00 proposed/classic 1,2 1 0,8 80,00 60,00 40,00 20,00 0,00 0,6 0,4 0,2 0 Crit. Path (classic) Crit. Path. (enhanced) Crit. Path. (ratio) Only 2% delay increase (in average) 28 C. Huriaux, O. Sentieys and R. Tessier September 3 rd,
29 FPL 14: Results: Min. Channel Width # tracks 160,00 140,00 120,00 100,00 80,00 60,00 40,00 20,00 0,00 proposed/classic 4,5 4 3,5 3 2,5 2 1,5 1 0,5 0 min W (classic) min W (enhanced) min W (ratio) 1.8X channel width increase on average Need for specific routing algorithms to deal with the heterogeneous interconnection network 29 C. Huriaux, O. Sentieys and R. Tessier September 3 rd,
30 DATE 15: Results Benchmark 20 biggest MCNC designs Avg. Compression ratio: 40% Size (Kbit) Bit-stream size comparison BS VBS Ratio VBS/BS 100 % 80 % 60 % 40 % 20 % Compression ratio 100 tseng spla seq s s38417 s298 pdc misex3 frisc ex5p ex1010 elliptic dsip diffeq des clma bigkey apex4 apex2 0 % Circuit 30 Christophe Huriaux Mid-term Evaluation March 19 th,
31 DATE 15: Results Up to 10% compression using clusters VBS size (Kbit) Size (min/max) Size (avg) Compression (avg) 100 % 80 % 60 % 40 % Compression ratio % Cluster size 0 % 31 Christophe Huriaux Mid-term Evaluation March 19 th,
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