Development of tools supporting. MEANDER Design Framework
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- Phillip Hodges
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1 Development of tools supporting FPGA reconfigurable hardware MEANDER Design Framework
2 Presentation Outline Current state of academic design tools Proposed design flow Proposed graphical user interface Comparison results Conclusions 2
3 Motivation Lack of complete academic design flow (RTL- VHDL Bit stream) Lack of open source code synthesizer Lack of open source code tool for bit-stream generation Existing incomplete design flows are in text mode (no GUI) Lack of manuals for the most of the existing tools Most of the tools are designed for different operating systems (SUN OS, Linux, BSD, ) 3
4 Design Flow Development Design flow based on open-source code CAD tools Linux Operating System C/C++ language Input format: RT VHDL, Structural VHDL, EDIF, BLIF Output: Configuration Stream Technology Independent Portability (e.g. x486, SPARC) Run on a local machine or through the Internet/Intranet Modularity: each tool can run as a standalone tool Graphical User Interface (GUI) Performance, Area and Power Consumption Minimum requirements: x486, 64 MB RAM, 30 MB HD 4
5 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 5
6 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Circuit description in VHDL Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 6
7 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Performs syntax checking and simulation Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 7
8 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Synthesizes the VHDL circuit to EDIF format Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 8
9 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Modifies the EDIF file in order to be compatible to our design flow Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 9
10 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Translates the EDIF to BLIF format Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 10
11 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Performs logic Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) optimization i tio and technology mapping to LUTs & F/Fs Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 11
12 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Packs LUTs/FFs into BLEs and Clusters Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 12
13 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Describes the FPGA architecture Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 13
14 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Performs placement Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) and routing. Also extracts power estimation results Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 14
15 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Modification of.edif files (DRUID) Performs circuit it power estimation Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 15
16 Design Flow Circuit Syntax check (VHDL Parser) & Simulation (FreeHDL) Synthesis (DIVINER/LEONARDO) Configures the FPGA Modification of.edif files (DRUID) Translation to.blif (E2FMT) Logic Optimization & Technology Mapping (SIS) S) Architecture (DUTYS) Generation of BLEs/Cluster (T-VPack) Placement/Routing (EX-VPR) FPGA Configuration (DAGGER) Legend Existing tool Modified & Extended New tool 16
17 VHDL Parser THIS TOOL WAS NOT MODIFIED JAVA based tool Checks VHDL file for syntax errors In case of error, a message locating it is displayed In addition there are some suggestions to correct it A manual for the tool has been written 17
18 FreeHDL THIS TOOL WAS NOT MODIFIED Is a VHDL simulation tool running on Linux It is part from the FreeHDL Project Is capable to show in graphic mode the signal transactions Supports the VHDL-93 standard Is similar to many commercial tools, like V- System A manual for the tool has been written 18
19 DIVINER NEW TOOL Goal: Synthesizes circuit descriptions from VHDL to EDIF There is no other available academic synthesizer Current Status: Supports a subset of VHDL- described components The circuits should consists of logic and F/Fs A manual for the tool is prepared 19
20 DRUID NEW TOOL Goal: Modification of EDIF file to another EDIF file compatible with the remaining tools of the design flow Automatically generates basic modules not supported by E2FMT libraries (arithmetic units, MUXs, decoders, comparators) in gate level. Renames component instances, signal and port names and libraries accordingly No other existing academic tool makes those modifications Tool manual prepared 20
21 DRUID OPERATION (1/2) (instance modgen _ add_ 0 (viewref INTERFACE (cellref add_ zu_ zu_ zu_ 0 (libraryref OPERATORS ))) (instance modgen_add_0 _ (viewref rtl (cellref adder_gen_z _ (libraryref USER_LIB )))) (port (array (rename output3 "output3(2:0)") 3 ) (direction OUTPUT)) (port output3_0 (direction i OUTPUT)) (port output3_1 (direction OUTPUT)) (port output3_2 (direction OUTPUT)) (portref (member output3 x) (instanceref reg2 )) (portref output3_x (instanceref reg2 )) 21
22 DRUID OPERATION (2/2) (cell add_zu_zu_zu_0 (celltype GENERIC) (property (rename a0 "$GENERIC") (string"add")) (property (rename a1 "$size") (string "z")) (property (rename a2 "$signed") (string "false")) (view INTERFACE (viewtype NETLIST) (interface (port cin (direction INPUT)) (port (array (rename a "a(z-1:0)") z )(direction INPUT)) (port (array (rename b "b(z-1:0)") z )(direction INPUT)) (port (array (rename d "d(z-1:0) 1:0)") ) z)(direction OUTPUT)) (port cout (direction OUTPUT))))) (cell adder_gen_z (celltype GENERIC) (view rtl_adder (viewtype NETLIST) (interface for(i=0; i=i+1; i=z-1) { (port a_"i" (direction INPUT)) } (contents (instance inv_i0_addz (viewref INTERFACE (cellref INV (libraryref PRIMITIVES )))) for(i=0; i=i+1; i="z-1") { (net b_i_adder_gen_z (joined (portref b_ "z-i-1" ) (portref in1 (instanceref and2_"i"_adderz_1 )) } 22
23 E2FMT MODIFIED TOOL Goal: Translation of netlist from EDIF to BLIF format Features: BLIF format is required from the existing academic tools Better than existing EDIF2BLIF tool, since it can handle morecomplex EDIF files The translation is based on the IWLS 93 library The technology library has been extended in order to support more complex components The source code was modified to embody PowerModel tool within the design flow Tool manual prepared 23
24 T-VPack MODIFIED TOOL Groups the lookup-table and the F/F to BLE or to Cluster Advantages: The size of the LUT can be specified It is easy to modify the source code, in order to handle more complex structures Disadvantage: Any modification i to BLE types must be compatible with ih the placement and routing tool We determined the way that this tool could handle user-specified structures of BLEs Tool manual prepared 24
25 DUTYS NEW TOOL Goal: Generates the architecture file of the target fine-grain reconfigurable hardware to be used by VPR tool Features: Description of I/O pads Description of Relative Channel Widths Logic Block Description Detailed Routing Architecture Description: switch box, connection box, segment Description of timing analysis parameters Tool manual prepared 25
26 EX-VPR MODIFIED TOOL Goal: Places and routes the circuit Combined with PowerModel, it extracts information about the power consumption of the circuit The source code has been modified in order to support extra features A model that estimates 2 device area in mm was added for 0.18μm STM Tool manual prepared 26
27 Power Model MODIFIED TOOL It estimates t the dynamic, the short-circuit, it and the leakage power consumption of an island-style FPGA It is integrated to the proposed design flow, after porting from Solaris-OS to Linux Tool manual prepared Circuit Architecture File VPR (Placement and routing) Activity Estimator Detailed power model for area and delay Estimation about area / speed / power consumption 27
28 DAGGER NEW TOOL It is the first academic open source bit-stream generation tool Input from: DUTYS, T-VPack, VPR, and PowerModel Novel configuration algorithm was developed The DAGGER tool can support partial reconfiguration (if hardware supports it) It can be used with the same way for programming BLEs or clusters It can used for a variety of FPGA architectures Supports FPGA arrays with ihlargesize The bit-stream is in encrypted binary format Tool manual prepared 28
29 Configuration Bitstream Generator: Structure of DAGGER Files Array EA Admissible connection point to routing channel Admissible connection point to switch box Prohibited connection point 29
30 Example of DAGGER output LUT PROGRAMMING ============================================ Input pad: p_1gat_0 pos_x = 0 pos_y=5 Input pad: p_6gat_3 pos_x = 6 pos_y=4 Input pad: p_7gat_4 pos_x = 6 pos_y=5 Input pad: p_2gat_1 pos_x = 0 pos_y=3 Input pad: p_3gat_2 pos_x = 4 pos_y=6 Output pad: out:p_2 pos_x = 3 pos_y=6 Output pad: out:p_2 pos_x = 4 pos_y=0 CLB: n_n14 pos_x = 4 pos_y=5 LOGIC = use f/f = 0 CLB: n_n5 pos_x = 4 pos_y=4 LOGIC = use f/f = 0 CLB: n_n13 pos_x = 5 pos_y=4 LOGIC = use f/f = 0 CLB: n_n9 pos_x = 4 pos_y=3 LOGIC = use f/f = 0 CLB: n_n2 pos_x = 2 pos_y=3 LOGIC = use f/f = 0 CLB: n_n6 pos_x = 2 pos_y=2 LOGIC = use f/f = 0 CLB: n_n1 pos_x = 3 pos_y=2 LOGIC = use f/f = 0 CLB: n_n3 pos_x = 5 pos_y=3 LOGIC = use f/f = 0 CLB: n_n10 pos_x = 3 pos_y=1 LOGIC = use f/f = 0 CLB: n_n7 pos_x = 4 pos_y=2 LOGIC = use f/f = 0 CLB: p_23gat_9_ pos_x = 4 pos_y=1 LOGIC = use f/f = 0 CLB: n_n0 pos_x = 3 pos_y=3 LOGIC = use f/f = 0 CLB: n_n11 pos_x = 3 pos_y=4 LOGIC = use f/f = 0 CLB: p_22gat_10_ pos_x = 3 pos_y=5 LOGIC = use f/f = 0 CLB: n_n15 pos_x = 1 pos_y=3 LOGIC = use f/f = 0 CLB: n_n12 pos_x = 5 pos_y=5 LOGIC = use f/f = 0 CLB: n_n8n8 pos_x = 2 pos_y=4 LOGIC = use f/f = 0 CLB: n_n4 pos_x = 2 pos_y=5 LOGIC = use f/f = 0 CLB: n_n16 pos_x = 1 pos_y=5 LOGIC = use f/f = 0 30
31 Example of placement and routing (EX-VPR) ISCAS Benchmark: C17 Initial placement of logic blocks Final placement of logic blocks Circuit after the finish of routing stage Zoom-in to the architecture of an FPGA Circuit fully routed 31
32 Graphical User Interface 32
33 Graphical User Interface It integrates most of the tools that are described previously There is no other academic implementation of such a complete graphical design chain Advantages of GUI: The GUI is friendly for the non-experienced designer The end-user does not need to know Linux It is possible to run it from local PC or through Internet / Intranet The source code can be modified (extended) in order to add more tools This interface can run from the local PC as well as though the Internet. In both situations it runs on the web- browser Can program the FPGA that is attached to the user s PC It is not needed to use all the tools of the design chain Manual prepared 33
34 Qualitative comparisons FEATURE AMDREL XILINX Univ. TORONTO ALLIANCE Data Input Format VHDL/ VERILOG VHDL/ VERILOG BLIF Synthesizer Format Translation - Architecture Description Place & Route Bitstream Generation Back annotation Power Estimation Area Estimation - GUI Remote Access to GUI VHDL User Manual SOLARIS/ O/S LINUX WINDOWS/ LINUX SOLARIS LINUX : supported : not supported -: not required 34
35 Presentation Outline Current state of academic design tools Proposed design flow Proposed graphical user interface Comparison results Conclusions 35
36 Quantitative Results: Frequency Maximum Frequency AMDREL XILINX MHz Benchmark 36
37 Quantitative Results: # LUTs Number of LUTs AMDREL XILINX LUTs Benchmark 37
38 Quantitative Results: Combinational circuit 38
39 Quantitative Results: Sequential circuit 39
40 AMDREL Power Analysis 4% 0% 35% Routing Power CLB Power Clock Power Leakage Power 61% 40
41 AMDREL Power Analysis Total Power Total Power with Low-swing uw Watt b01 b02 b03 b04 b06 b07 b09 b10 b11 b13 b14 b20 b20 0_1 b21 b21 1_1 mac c32 Benchmarks 41
42 AMDREL Power Analysis 42
43 Comparison of Configuration Bitstream sizes AMDREL XILINX Device Config. bits LUTS/FFs Device Config. bits LUTS/FFs , /320 XCS05 53, /360 XCS10 95, / , /1620 XC2S50 559, / ,649, /3645 XC2S150 1,040, / ,331, /5780 XCV300 1,751, / ,748, /7605 XCV400 2,546, / ,984, /1045 XCV600 3,607, / ,024, /11520 XCV800 4,715, / ,435,763, 17405/17405 XCV1000 6,127,744, 24576/
44 Conclusions Complete Design Flow: Input VHDL Output Bitstream The single only complete design flow in academia based on open-source tools and running on Linux Promising comparisons results with commercial design flow 44
45 More info: AMDREL website: ee duth gr/amdrel AMDREL website:
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