An FPGA Design And Implementation Framework Combined With Commercial VLSI CADs

Transcription

1 An FPGA Design And Implementation Framework Combined With Commercial VLSI CADs ReCoSoC 2013 Qian Zhao Motoki Amagasaki Masahiro Iida Morihiro Kuga Toshinori Sueyoshi (, Japan)

2 Background FPGA IP core development Make SoC programmable Requirements: Synthesizable Architecture exploration Scalability Other features (3D, dependability,etc) MCU ADC Mem. FPGA IP System-On-a-Chip Traditional academic flows are not applicable FPGA IP design framework is required Efficiently evaluate & implement various arch. Connect to commercial VLSI design flow 1

3 Goal of this research Goal: Develop an FPGA IP design framework Method: Develop novel routing tool EasyRouter New features: Implement new architectures easily C#(Mono) Platform (Linux/Windows) C# script based Arch. definition Arch. Exploration -> HDL & Bitstream generation Same arch. exploration functions as traditional tools Generate HDL & BitStream with simple templates Performance analysis with commercial VLSI flow 2

4 Compare with VPR VPR is the main academic placement & routing tool VPR6.0 (current version) Not for synthesizable FPGA Delay model is not suitable for standard cells based design Only support Island style FPGA Arch. is defined with XML&C Hard to implement new architectures Novel EasyRouter HDL & Bitstream generation High accuracy analysis with VLSI CADs C# language Script based arch. definition 3

5 VPR: XML based Arch. definition Only support Island Style FPGA Parameters can be changed in XML based Arch. File Example of making Switch box VPR void MakeSB(type, fs) { } Arch. File(XML based) type= Wilton fs="3" Only small changes can be made for the supposed Arch. For unsupported Arch., need to modify the source code 4

6 R H C VPR: Delay model L W ρ Wire model Routing delay C cb_to_lb L : calc. from LB area (length of segment wire) W, ρ,h : determined by process R=ρ L/H W C wire C from_switch Elmore delay model C to_switch C cb_from_lb Logic delay Logic Block Verilog Synthesis HDL(Gate) &.sdc Layout HDL(Gate) &.spef Static Timing Analysis Write delay info. to Arch. file Critical path delay (Composed with different delay model) 5

7 EasyRouter blocks Breadth_first & Timing_driven routing algorithm (same with VPR) EasyRouter Clustered netlist Placement result RRGraph building block Routing block FPGA architecture script file Arch. & physical parameters setup Netlist & placement files import RRGraph build HDL templates HDL & Bitstream Generation with routed info. Report Generation block HDL codes Generation block BitStream Generation block Mapped netlist Arch. Scrip File HDL templates Reports RRGraph: Routing-resource graph FPGA HDL codes Bitstream 6

8 Script based Arch. definition Implement FPGA Arch. in a script file Dynamic compiled during execution Contains both Arch. Implement codes and parameters Any architecture can be implemented in low cost Example of making Switch box EasyRouter Arch. Script load switch block object from c# script int Fs=3; Public switchbox makesb() { } Structure can be modified freely 7

9 Verilog & BitStream generation VerilogHDL Logic block Prepared in template Routing Generated according to Channel width / CB,SB topology Chip :Top level module according to array size BitStream Routing & Local connection block Generated according to routed info. Logic block Technology mapping results CB: Connection Block SB: Switch Box 8

10 FPGA design flow based on EasyRouter HDL or Blif file Clustered Netlist Placement result HDL Template Fixed Channel Width & Array Size VTR Project (ODIN II, ABC, VPR) EasyRouter (evaluation mode) HDL Codes (RTL) BitStream Clustered Netlists Placement results FPGA CADs EasyRouter (CW exploring mode) Formal Verification Formal Verification VLSI CADs Function Verification Synthesis HDL(Gate) &.sdc Layout HDL(Gate) &.spef Static Timing Analysis Minimum Channel Width ArraySize GDS Timing Report Standard Cell Library Device scale exploration Device implementation 9

11 Fast evaluation with EasyRouter The fast evaluation with EasyRouter can be used when VLSI analysis is too slow (big chip) No available VLSI flow(3d-fpga) Tile HDL code Clustered Netlists (.blif) Placement results Tile physical information Fixed Channel Width & Array Size Synthesis Layout STA Tile physical information EasyRouter (Fast performance analysis) Netlist & placement reading block RRGraph building block Routing block Report generation block Chip area & timing report (a) Tile info. (b) Fast evaluation with EasyRouter 10

12 Evaluation : EasyRouter Device structure Island style FPGA Item Logic cluster value 4-LUT 4 # of LB inputs 10 SB CB Channel Wilton(Fs=3) Fc_in=0.5, Fc_out=1.0 Single lines MCNC Benchmarks Evaluation items Minimum channel width for routability evaluation Execution time for tool efficiency evaluation 11

13 Minimum channel width (Routability) Channel width VPR EasyRouter Benchmarks EasyRouter has almost the same routability with VPR Minor differences are from different routing orders 12

14 Execution time (CPU time) Execution time normalized by VPR Benchmarks EasyRouter is 8 times slower than VPR on average Big circuits are about 5 times slower 13

15 Evaluation for proposed design flow Process:e-Shuttle 65nm Device parameters Item value Array size Logic cluster 4-LUT 4 # of LB inputs 10 SB CB IOB Wilton(Fs=3) Fc_in=0.5, Fc_out=1.0 Fc=1.0 # of routing tracks(single line) 50/channel MCNC Benchmarks Evaluation items Critical path delay on average(10 placement seeds) 14

16 Device architecture for evaluation IOB IOB IOB IOB CB_X SB IOB IOB Tile Tile Tile Tile Tile Tile Tile Tile IOB IOB Local Connection BLE_0 CB_Y IOB Tile Tile Tile Tile IOB BLE_1 IOB Tile Tile Tile Tile IOB BLE_2 IOB IOB IOB IOB LB BLE_3 Homogeneous FPGA Tile structure 15

17 Critical path delay results 250 Full FPGA STA Critical path delay (ns) EasyRouter VPR 0 s298 elliptic diffeq alu4 misex3 apex4 Benchmarks Delay from VPR is about 10x worse than STA results Delay from EasyRouter is about 1.5x worse then STA results 16

18 Conclusions EasyRouter Simple:New arch. can be implemented in low cost High accuracy:link academic FPGA tools with commercial VLSI CADs Other works with the proposed flow 3D-FPGA(VLSI-SoC2013) Three-Dimensional Stacking FPGA Architecture Using Face-to- Face Integration Hierarchy routing FPGA(FPL2013) Defect-Robust FPGA Architectures For Intellectual Property Cores In System LSI 17

19 Thank you for your attention.

20 VPR(MIN-MAX-AVG. value from 10 seeds results) Critical path delay (ns) ns 0.0 misex3 alu4 apex4 diffeq elliptic s298 Benchmarks Change range of delay results of VPR is large when placement seed value changes 19

21 EasyRouter(MIN-MAX-AVG. value from 10 seeds results) Critical path delay (ns) Benchmarks 4.17ns misex3 alu4 apex4 diffeq elliptic s298 Change range of delay results of STA results are smaller than VPR when placement seed changes 20