Routing Path Reuse Maximization for Efficient NV-FPGA Reconfiguration

Transcription

1 Routing Path Reuse Maximization for Efficient NV-FPGA Reconfiguration Yuan Xue, Patrick ronin, hengmo Yang and Jingtong Hu 01/27/2016

2 Outline Introduction NV-FPGA benefits and challenges Routing optimization strategy Proposed Routing Reuse Optimizations Experimental Evaluation onclusion 1

3 Self adaptive systems FPGA offers reconfigurability, flexibility, and low design cost to various embedded systems such as control, signal processing and many other applications areas. 2

4 Drawbacks of traditional FPGAs Unfortunately, traditional SRAM-based FPGAs cannot meet increasing design requirements: Low scalability High leakage power Prone to soft error Volatile 3

5 NVM-based FPGA Non volatile Memories (NVMs) use physical characteristics to represent logic states, such as: Phase hange Memory (PM) Ferroelectric RAM (FRAM) Spin Transfer Torque Magnetic RAM (STT-MRAM) STT-MRAM PM FRAM 4

6 Overcome SRAM limitations? NVM High density Near-zero leakage power Strong error resistance Near-zero power-on delay SRAM Low scalability High leakage power Prone to soft error Volatile However, no rose is without a thorn! 5

7 Any issues or challenges? OMPARISON OF SRAM AND VARIOUS NVM ELLS Type Area (F 2 ) Read time(ns) Write time(ns) Write cycles SRAM PM 4 12 STT-MRAM NOR Flash However, no rose is without a thorn! Two major issues of NVM FPGA: Slow Writes make the reconfiguration time non-trivial! Short Endurance limits device lifetime! 6

8 How to solve? asic scheme: reduce writes and increase reuse with a bitlevel read-before-write (RW) strategy New data compare read write NVM cells NVM cells Why this works for NVM? For PM Without RW 4 writes 400ns With RW 4 reads+ 148ns 1 write Great Improvement! Type For SRAM Read time(ns) Write time(ns) SRAM Without RW PM writes No benefit! 0.8ns With RW 4 reads+ 1ns 1 write 7

9 M NV-FPGA NV-FPGA: Use NVMs as on-chip memories and configurable block units on FPGA. Main blocks include: onfigurable logic blocks (s) onnection blocks (s) Switch box (s) LOK AREA POWER DELAY 90% 85% 80% M M (a) Structure General Input Full rossar (b) Structure arry in Fracturable LE[0] arry out General... Output Fracturable LE[9] LUT arry in FF FF arry out (c)asic Logic Element out1 out2 + 10% 15% 20% All can be NVMs! nv nv nv nv nv nv nv nv nv M NVM based Programmable locks Architecture (d) Structure (e)bidirectional pass switch We target s the dominating blocks on the FPGA 8

10 Three categories: Related work on routing optimization Hierarchical routing match & preserve Idea: onstruct cluster routing graph, match and preserve route hierarchically Related work: M.M Ozdal IAD 09, hing-yu hin IAD 14 Proposed work differs from them in: Single Path level routing optimization oarse-grained partial reconfiguration Idea: Partition bitstream into dynamic and static parts, reuse static parts under partial reconfiguration framework. Related work: E. Vansteenkiste FPL 12,. Al Farisi FPL 13 Fine-grained bit level reuse, require no partial reconfiguration support Incremental design routing reuse Idea: At engineering change order(eo) stage, compare netlists to find possible reusable metal wire sections, and preserve these metal layer wires. Related work: Yun-Ru Wu VLSI-DAT 10, Hsi-An hien ASP-DA 14 an be applied to both highly-similar and dissimilar designs. 8

11 Overview Our goal Minimize bit-flips when reconfiguring on NVM-based FPGA Strategy Maximize bit-level reuse of switch boxes during routing Questions to be addressed How to model reconfiguration cost? What types of flexibilities can be exploited to maximize reuse? How to perform reuse-aware routing while preserving circuit timing? 10

12 Outline Introduction Proposed Routing Reuse Optimizations Modeling routing reconfiguration cost Identifying & Maximizing reusable path Proposed reuse-aware routing algorithm Proposed AD flow Experimental Evaluation onclusion 11

13 Reconfiguration cost Wilton Switch type l k a b c d e switch On/ off l a 1 j b 1 c e 1 switch On/ off 3 changed switches l a 0 j b 0 c e 1 l k a b c d e j i h g Existing configuration f h f 1 k i 0 connected switch Nold=4 Reused switch: R=2 h f 1 k i 1 connected switch Nnew=3 j i h g New configuration f Single reconfig cost: RR =N old + N new 2R NUM RR i Total reconfig cost: ost reconfig = i=1 12

14 Outline Introduction Proposed Routing Reuse Optimizations Modeling routing reconfiguration cost Identifying & Maximizing reusable path Proposed reuse-aware routing algorithm Proposed AD flow Experimental Evaluation onclusion 13

15 Path Definition and haracterization Definition: Path is a single source-to-sink connection. s locally connect s to s, can be omitted in our structure model FPGA hip 14

16 Path Definition and haracterization Definition: Path is a single source-to-sink connection. haracterization: Path P={(i,j),( first last )}. P consists of two sets: set: (i,j) starting point i, ending point j set: ( first last ) all s that P passes through Path reuse could efficiently translate to reuse! Path P FPGA hip 15

17 Two types of Reusable Paths Full reuse: P shares both starting and ending s with P. Partial reuse: P shares starting and last with P. Full Reuse Old Path P New Path P Partial Reuse FPGA hip 16

18 Reusable Path Maximization However, the same starting cannot guarantee path reuse. LUT-to-LE mapping will result in different path reuse and reconfiguration costs. Suppose LUT1 1 and LUT2 3. If LUT1 LE1, path can be reused Otherwise, path can not be reused ross bar LE1 LEn 1 n LUT1 2 Pin1 6 New design LUT Old Path P New Path P FPGA hip 17

19 To maximize path reuse, we exploit LUT-to-LE mapping flexibilities. Assume n LEs in each, the problem can be translated to bipartite graph matching. Weight of edge i j represents the number of reusable switches. For example, LUT1 LE1 Edge 11 =2 LUT1 Reusable Path Maximization 1 2 Pin1 3 Optimal mapping=? mapping! 3 LEa Reuse= LE 1-n LUT 1-n Maximal reuse! LUT2 LEb LUT3 LEc One in new design One block on FPGA Optimal mapping can be identified with Kuhn-Munkras Algorithm. H. Kuhn, The Hungarian method for the assignment problem, in NRLQ, Mar. 1955, pp

20 Outline Introduction Proposed Routing Reuse Optimizations Modeling routing reconfiguration cost Identifying & Maximizing reusable path Proposed reuse-aware routing algorithm Proposed AD flow Experimental Evaluation onclusion 19

21 Reuse-aware Routing Algorithm asic routing: Select routing resources to finish connection in each net. source Net: single source to multiple sinks connection. Each net contains several paths with the same starting point. sink Routing resources pool Iteratively, exist if no congestion Proposed three-stage routing algorithm Fix reusable paths in each net Route other paths Relax reusable path with bad timing Divide resource into two types: general (used for all nets) and dedicated (used by specified net) Rank nets by their sink count, route nets with maximum sinks first When relax, release related dedicated resources 20

22 Stage 1: fix reusable path Stage 2: route other paths Stage 3: relax related paths Repeat 2,3 if congesting Input: Netlist, Placement, Reusable paths, Relax threshold ɛ Output: Routing results Mark all routing resources rr_node:type = general; for (i = 0;i<NUM_reuse_path;i++) { for (n= 0;i<NUM_net;i++) { if (rr_path[i] Nets[n]) { Mark its corresponding rr_node:type = n; Mark rr_path[i] Trace[n]; } } } Sort (nets, unrouted sinks); for (loop = 0;loop<Iteration_limit;loop++) { for (i=0;i<num_net;i++) { n = Order[i]; for (j = 0;j<sink_num[n];j++) { if (path[n][j] reusable path) { if (rr_node:type == (general n) rr_node andidate_set; Pathnder(Trace[n],path[n][j],andidate_set); } } Perform timing analysis and update path criticality values; for (i = 0;i<NUM_reuse_path;i++) } { if (T_rrpath[i] > (1-ɛ) T_critical_path) { rr node:type = general; Remove rr_path[i] from the reuse list; } } if (no congestion exist) Exit ; 21

23 Outline Introduction Proposed Routing Reuse Optimizations Modeling routing reconfiguration cost Identifying & Maximizing reusable path Proposed reuse-aware routing algorithm Proposed AD flow Experimental Evaluation onclusion 22

24 Original AD flow Design Description (HDL) Synthesis and technology map lustering and packing level placement Routing Estimate performance 23

25 Proposed AD flow New Design Design Description (HDL) Retrieve on-chip information Existing Design Synthesis and technology map lustering and packing level placement Phase 1 Generate inner (LUT to LE) placement mapping Phase 2 Path-reuse aware routing Evaluate performance Phase 3 24

26 Outline Introduction Proposed Routing Reuse Optimizations Experimental Evaluation onclusion 25

27 Methodology FPGA architecture: Altera Stratix IV AD toolkit: VTR 7.0 Schemes Read-beforewrite Strategy Experimental configuration Reusable Path Identification Reusable Path Maximization Reuse-aware Routing aseline DIR (ɛ=1%) Proposed (ɛ=1%) DIR: Proposed scheme without reuse maximization ɛ: Threshold for reusable path relaxation, path timing within ɛ=1% of critical path will be relaxed. 26

28 Methodology 10 MN benchmarks, 9 test pairs TP1 TP9 No enchmark # LUT# Net# Track Width 1 bigkey s frisc elliptic spla pdc ex s s clma

29 Results 1/3 Path reuse Full path reuse rate Partial path reuse rate 12.0% 30.0% 10.0% 25.0% 8.0% 20.0% 6.0% 15.0% 4.0% 10.0% 2.0% 5.0% 0.0% TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 0.0% TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 DIR full reuse Proposed full reuse DIR partial reuse Proposed partial reuse Average DIR = 1.7%, Proposed = 3.9%. Average DIR = 4.3%, Proposed = 15.8%. Full + Partial = 40.0% 30.0% 20.0% 10.0% Total path reuse rate 0.0% TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 DIR total reuse Proposed total reuse Average DIR = 6%, Proposed = 19.7%. 28

30 Results 2/3 reconfiguration cost reduction 35.0% 30.0% 25.0% 20.0% 15.0% 10.0% 5.0% 0.0% reconfiguration cost = reconfiguration writes (in bits) reconfiguration cost reduction TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 DIR Reduction Proposed Reduction Average DIR = 9.8%, Proposed = 24.5%. Reconfiguration cost reduction is strongly correlated with reuse rate but not exactly the same, since paths contain different numbers of s. 40.0% 30.0% 20.0% 10.0% 0.0% Total path reuse rate TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 DIR total reuse Proposed total reuse 29

31 Results 3/3 Performances with different ɛ 1.1 ɛ=%1 has the best 1 overall performance. 0.9 Average performance of all test pairs ɛ=0% ɛ=1% ɛ=2% ɛ=3% ɛ=5% ɛ=10% ɛ: threshold to control reusable path relaxation reconfiguration cost(normalized) ritical path delay(normalized) Geomean the smaller, the better

32 Outline Introduction Proposed Routing Reuse Optimizations Experimental Evaluation onclusion 31

33 hallenges: onclusion NVM-based FPGAs are promising to self-adaptive applications, but slow writes and short endurance of NVMs need to be addressed Our goal: Minimize reconfiguration costs of switch boxes through reuse-aware routing Our approaches: Model reconfiguration cost and identify two types of reusable paths Maximize path reuse through exploiting LUT-to-LE mapping flexibilities Enhance VTR AD flow with a reuse-aware routing algorithm Results Summary: Proposed schemes deliver as much as 40% path reuse and 34% reduction in reconfiguration cost, within 3.5% overhead in critical path delay. 32

34 THE END Questions are welcome.