A Routing Approach to Reduce Glitches in Low Power FPGAs
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1 A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin Wong Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign This research was supported by Altera and NSF
2 Outline Introduction Background Routing Approach Path-Finding Algorithm Results
3 Dynamic Power and Glitch Dynamic Power 67% of total power (Stratix II FPGAs) Glitch Up to 60% of total dynamic power Glitch Reduction Lower Dynamic Power
4 Related Works High-Level Logic decomposition [Monteiro et al., 1998] RTL synthesis [Raghunathan et al., 1999] Not applicable to FPGA Gate freezing [Benini et al., 2000] Delay insertion [Raghunathan et al., 1999] FPGA specific GlitchMap [Cheng et al., 2007] GlitchLess [Jamoureux et al., 2007]
5 FPGA Interconnect Island-Style FPGA Interconnect delay is more significant than logic delay Programmable interconnects with fixed delays Rich, under-used interconnect resource [Betz et al., 1999]
6 Routing Approach Reduce Glitches by balancing input arrival times By routing through paths with desired delays Lengthen paths of early-arriving inputs No Architectural Modification Applied to existing FPGAs Do not affect critical path delay
7 FPGA Routing Architecture [Betz et al., 1999] Routing resource graph Assumption: Buffered Switches True for commercial FPGAs (boost performance) Linear delay model for paths
8 Algorithm Overview Get an valid routing solution (VPR router) Reduce Glitches by Balancing certain sourcesink pairs Selection and Ordering of pairs Rip-up and re-route each pair Reroute with Path-Finding Algorithm Find path with desired delay
9 Selection Criteria Power overhead due to longer path More capacitance, more buffers Balance only beneficial inputs Switching Reduction Capacitance Increase 0.4 Heuristic: Balancing inputs 0.2 of 1 st 0 -level clusters 1st Level 2nd Level All
10 Ordering Criteria LUT Input Weighting Likelihood of glitch generation Signal probability of Boolean difference Balancing overhead Prefer small increase delays over large increase Path ranking
11 Path-Finding Algorithm Inputs: Routing-resource graph (V, E) with delay information Source-sink pair (s, t) Desired delay range d±δ Output: Path from s to t with desired delay Not always has a solution s t
12 Motivation Try every paths: exponential complexity Heuristic: Select a manageable subset of paths Polynomial complexity Still provide reasonable quality of results Wide range of path lengths
13 Motivation Efficient path algorithm: shortest path Find only path with smallest delay d Detour Combine shortest paths Increase path delay s t
14 Motivation Efficient path algorithm: shortest path Find only path with smallest delay d Detour Combine shortest paths Increase path delay s t Problem: overlapping
15 Candidate Paths Set S s t' s Set T t Set S: vertices closer to s Set T: vertices closer to t (s, t ): direct connection (edge) Guarantee no overlapping
16 Glitch-Reducing Framework Run timing-driven VPR router to get a routing solution for each 1-st level CLB input get desired balanced delay compute path rank end Sort these inputs by their rank for each input rip-up current path use path-finding algorithm to find a path with the desired delay if can not find such a path restore the ripped-up path end end
17 Experiment Settings 20 largest circuits from MCNC and ISCAS89 Timing-driven place and route by VPR 4-LUT, cluster size 4 Power simulator fpgaeva-lp2 [Li et al., 2005] Dynamic power Glitch power Switching activity
18 Results average C C C C C C C C C C spla seq pdc misex exp5p ex des apex apex alu4 with without with without Runtime (seconds) Impr. (%) Dynamic Power (mw) Circuits
19 Results average C C C C C C C C C C spla seq pdc misex exp5p ex des apex apex alu4 Increase in Wire Length (%) Reduction in Switching Activity (%) Reduction in Glitch Power (%) Circuits
20 Conclusions Glitch reduction in FPGA through routing CAD approach, not require architectural modification 9.8% average of dynamic power reduction Efficient Path-finding algorithm A small, efficient subset of possible paths Can be combined with other techniques GlitchMap GlitchLess
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