A Tuneable Software Cache Coherence Protocol for Heterogeneous MPSoCs. Marco Bekooij & Frank Ophelders

Transcription

1 A Tuneable Software Cache Coherence Protocol for Heterogeneous MPSoCs Marco Bekooij & Frank Ophelders Outline Context What is cache coherence Addressed challenge Short overview of related work Related issue: memory consistency Proposed software cache coherence protocol Performance evaluation results Concluding remarks 1

2 Multi-stream car-entertainment system Car-radio IC of NXP Accelerators Cordic Cordic FIR Peripherals IF IN 1x SRC Keyed AGC 1x Radio 8*fs In + out PCM I/f Audio ADC 4x Audio DAC 4x Ext SPDIF-in Host Host/ext IIS-in 2x IIS-out 2x IIS-out 1x Ext IIS-in 3x Digital In Out (DIO) Switch Tile 0 Tile 1 DSP EPICS AHB if Tile 2 DSP EPICS ITC Tile 3 DSP EPICS AHB if ITC DSP EPICS AHB if ITC AHB if ITC Inter Tile Communication (ITC) Multi-layer AHB bus (3 layer) Controller DMA ARM SPI CD Block Dec. ARM based subsystem AHB2VPB AHB2VPB AHB2VPB VPB VPB VPB Domain 2 Domain 1 Domain 0 Unsuitable for general purpose applications (e.g. Pthread) 2

3 Developed experimental embedded multiprocessor system Instruction Memory PE1 ARM926EJ-S PE1 ARM926EJ-S PE2 $ I D D I $ Instruction Memory PE2 $ $ Peripherals RS232 Display Touchscreen Audio in/out Video in/out Timers Æthereal network-on-chip TDM TDM RR SDRAM 256 MB Processors communicate through shared memory Processors have private caches Cache coherence problem! Shared Memory 1 8 MB Shared Memory 2 8 MB Virtex 4 Cache coherence problem X: 10 3 P1 P2 Read returns 3!!! $ $ X: 3 Shared memory X: 10 3 A cache coherency protocol ensures that eventually s become visible to all processors 3

4 Addressed challenge Define a cache coherence protocol that is suitable for real-time embedded systems with a NoC and with off-the-shelf processors Related work on cache coherency Hardware cache coherency protocols Snooping based protocols: Requires processors to observe all memory accesses Does not match well with a NoC: preferably point-2-point communication instead of broadcasting Directory based protocols Significant overhead as a result of accessing the directory Transactional memory Relies on speculation: suitable for real-time systems? > Remark: most embedded processors do not support a hardware cache coherency protocol Software cache coherency protocols Require a specific programming style: explicit coupling between each synchronization operation and data-structure it protects Prevent cache coherency issues: put shared data in uncached address range Low efficiency 4

5 Issues in sharing cache lines Cache operations often operate on lines P1 A B P2 A B A B A B A B Related issue: memory consistency A = 1 flag = 1 P1 P2 while ( flag!= 1 ); print A Memory accesses reordering by Memory system Processor Compiler We need a memory consistency model Defines constraints on the order in which memory operations become visible to other processors Enables programmers to reason about outcome 5

6 Sequential Memory Consistency P1 P2 P3 A=1 while (A!=1); B = 1 Network-on-chip while (B!=1); Print A All s must be seen in one single order by all processors ( atomicity) Likely to be inefficient in combination with a NoC P1 P2 P3 read lock read unlock 6

7 Proposed software cache coherence protocol Tuneable software cache coherence protocol Proposed software cache coherence protocol Minimal hardware requirements Suitable for heterogeneous MPSoCs with a NoC Off-the-shelf processors and caches are supported Should support cache maintenance operations (clean, invalidate) Sufficient for POSIX threads (Pthreads) explicit synchronization operations Tuneable Separate shared and private data Shared in -through and private in -back cache region Minimize unnecessary invalidations Putting shared data in a specific cache way Suitable for real-time systems Bounded protocol overhead, WCET is independent of accesses other processors 7

8 Release Consistency Ensuring sequential consistency efficiently is (too) costly apple support release consistency Acquire Guarantees reading most recent data from memory Release Makes s visible to other processors Cache coherence operations only required on acquire and release read acquire(s) read release(s) SWCC protocol in POSIX threads POSIX threads No two threads can access data at the same memory location simultaneously while at least one of the threads is modifying the location... Pthread_mutex_lock (acquire) Obtain lock Clean & invalidate Dcache Pthread_mutex_unlock (release) Clean Dcache Release lock Pthread_mutex_lock(S) (exclusive access to shared data) Pthread_mutex_unlock(S) 8

9 Tuning the protocol Place shared and private data in different address ranges Private data does not need to become visible to other processors Private data in -back region of the cache Shared data solve the sharing problem Shared data in -through region of the cache Execution time FFT Memory accesses FFT Experiments Embedded the software cache coherence operations in POSIX threads calls Clean and invalidate entire shared address range on each synchronization Entire cache Way with shared data Address range (MVA) Executed Splash2 applications ARM926EJ-S PE1 I D ARM926EJ-S PE2 D I Low latency 4 cycles / word Each processor gets equal budget TDM arbitration on memory port $ $ $ $ Instruction Memory PE1 TDM Instruction Memory PE2 Peripherals RS232 Display Touchscreen Audio in/out Video in/out Timers Shared Memory 16 MB 9

10 Cost of cache coherence operations Two cost types: cost of the cache maintenance operation cost of unnecessary invalidations Speedup Splash2 applications Speedup between 1.89 and

11 Increase of memory accesses Protocol does not increase number of memory accesses significantly Conclusion Presented a cache coherence protocol that is suitable for real-time systems with a NoC and with off-the-shelf processors Most important optimization is separation shared and private data Experimental results Speedup between 1.89 and 2.01 Higher synchronization/computation ratio (e.g. hardware floating point support) lower speed-up? Protocol does not significantly increase memory bandwidth requirements Suitable for real-time systems because software cache coherency protocol overhead is predictable 11

12 Questions? Backup slides 12

13 SWCC protocol in POSIX threads P1 Pthread_mutex_lock(S) P2 Pthread_mutex_lock (acquire) Obtain lock Clean and invalidate Pthread_mutex_unlock (release) Clean Release lock (exclusive access to shared data) Pthread_mutex_unlock(S) Pthread_mutex_lock(S) (exclusive access to shared data) P1 NoC P2 Pthread_mutex_unlock(S) Memory Existing cache coherence protocols Transactional Memory multiprocessor systems are based on speculation Suitable for real-time systems? Hardware protocols Snooping in a NoC Requires processors to observe all memory accesses Writes to one location are serialized P 1... P n $ $ Bus snoop Shared Memory Cache to Memory transaction 13

14 Existing cache coherence protocols Hardware protocols Directories in a NoC A directory is consulted on memory accesses Increase in memory access latency P 1... P n $ $ Interconnect Shared Memory Directory Hardware protocols require support from processors Supported by off-the-shelf processors? Existing cache coherence protocols Software protocols Explicitly coupling between synchronization and data structure Conditional invalidation [Tartalja, HICSS 1992] Shared regions [Sandhu, ACM SIGPLAN 1993] Enter critical region (D) 1) Check administration 2) Invalidate? Access D Exit critical region (D) Clean if -back Private data cached, shared data not cached In [Petrot, DSD 2006] 14