Design of a Web Switch in a Reconfigurable Platform

Transcription

1 ANCS 2006 ACM/IEEE Symposium on Architectures for Networking and Communications Systems December 4-5, 2006 San Jose, California, USA Design of a Web Switch in a Reconfigurable Platform Christoforos Kachris Stamatis Vassiliadis

2 Definition of a Web Switch Clients Optimization of cluster-based servers cgi Application Server Farm Web Switch gif, jpg Image Server Farm 2

3 Definition of a Web Switch Clients /news/* Server Farm Web Switch /download/* Server Farm 3

4 Benefits & Types of Web Switches Benefits Scalability and acceleration of application Persistent user session on a server Content customization (eg regional based) Faster response Types URL-based load balancing (directory/application) Cookie-based load balancing [Source: Cisco Layer 7 Load Balancing and Content Customization] 4

5 TCP Gateway Client Web switch Server L5-7 TCP IP L1-2 L5-7 TCP IP L1-2 L5-7 TCP IP L1-2 5

6 TCP Splicing Client Web switch Server L5-7 TCP IP L1-2 L5-7 TCP IP L1-2 L5-7 TCP IP L1-2 6

7 Web switch with TCP Splicing Client Web switch Server SYN, ACK SYN ACK, Data SYN, ACK SYN ACK, Data Simple header modifications 7

8 Implementation of Web Switches Software(Yang 99) High flexibility Low performance ASIC(Apostolopoulos 00) High performance Low flexibility Network Processors (Zhao,Bhuyan 05) High performance High flexibility High power 8

9 FPGA-based Web Switch High flexibility using RISC processors Not vendor specific language High throughput using co-processors Reconfigure co-processors based on the type of web switch Low Power 9

10 Architecture 32-bit RISC Processors Check sum Check sum FSL Barrel shifter Pattern compare FSL Barrel shifter Pattern compare Data MicroBlaze 32-bit RISC Inst Data MicroBlaze 32-bit RISC Inst Connection Manager URL Parsing Module HTTP Requests Buffer Client Buffer Server Buffer Connection B URL B Client GMAC Server GMAC Co-processors DMA Engine 10

11 Connection Manager IP address, TCP Port 48 HASH 10 B 1k x 128 B 1k x 128 IP, TCP Compare Compare Write (IP, TCP, SIP, state, Client SEQ, Server SEQ) return 0; Search (IP, TCP) return SIP, state, Client SEQ, Server SEQ; Delete (IP, TCP) return 0; B 1k x 128 Compare B 1k x 128 Compare SIP, State, CSEQ, SSEQ CAM 128x48 7 B 128 x

12 Collision probability Number of Bs Collision Probability 128CAM 256CAM 18% 15% 11% 8% 4% 1% 0% 0% Using the UC Berkeley-home IP traces (Nov 17) 12

13 URL Parsing Co-processor Char Table (32 bits) c0 c1 c2 c3 Address Table (32 bits) a0 a1 a2 a3 Bus Controller URL Controller Control Table (12 bits) L SC V LC 13

14 URL Co-processor example URL /news/* /news/msc/ /news/phd/ Server IP news/ msc/ phd/ *

15 URL Co-processor example URL Server IP 1 n e w s /news/* 16 2 / /news/msc/ 17 3 m p * /news/phd/ 18 4 s c / * news/ m p * sc/ hd/ 5 h 3 4 Char Table d / 5 16 * Address Table

16 Performance of URL Co-processor 1-4 chars/cc Most of the URLs are <28 char for the first two strings of the directory (based on the San Diego Super Computing Center Web Traces (wwwwebcachingcom)) ~11cc per URL 16

17 Packet Processing Latency Packet Type Reconf Latency (us) IXP2400[3] Linux[3] Control Packet SYN ACK/Req SYN/ACK Data Packet Data ACK

18 Performance Evaluation Sustained throughput for several Request packet sizes Performance Bandwidth (Mbps) KB 2KB 4KB 16KB 64KB Request Packet Size 1Microblaze 2Microblazes 18

19 Bus Utilization Bus Utilization 80 Utilization (%) KB 2KB 4KB 16KB 64KB Request Packet Size (bytes) 1Microblaze 2Microblazes Bottleneck In the first case (1 processor) is the processing power In the second case (2 processors) the bottleneck is the bandwidth of the bus 19

20 Area Allocation ~10000 FPGA slices in Xilinx Virtex4 (~300K gates) Area Allocation by Module Misc 12% Microblaze0 11% Microblaze1 11% CAM 31% Conn Module 9% URL Module 10% GMAC1 8% GMAC0 8% 20

21 Power Evaluation Overall FPGA based: <1W NP based : ~10W Power Distribution by Module (mw) GMAC0 13% GMAC1 13% Microblaze0 20% Misc 34% Microblaze1 20% 21

22 Scalability 32-bit Check sum Check sum FSL Barrel shifter Pattern compare FSL Barrel shifter Data MicroBlaze Inst Data MicroBlaze Connection Manager URL Parsing Module HTTP Requests Buffer Client Buffer Connection B URL B Client GMAC Pattern compare Inst Server Buffer Server GMAC DMA Engine 22

23 Check sum Check sum FSL Barrel shifter Pattern compare FSL Barrel shifter Pattern compare Data MicroBlaze Inst Data MicroBlaze Inst Scalability 32-bit Connection Manager URL Parsing Module HTTP Requests Buffer Client Buffer Server Buffer Cookie-based Co-processor Connection B URL B Client GMAC Server GMAC The co-processors can be dynamically reconfigured to meet the application requirements DMA Engine 23

24 Scalability 32-bit The co-processors can be dynamically reconfigured to meet the application requirements Check sum Check sum FSL Barrel shifter Pattern compare FSL Barrel shifter Data MicroBlaze Inst Data MicroBlaze Connection Manager URL Parsing Module HTTP Requests Buffer Client Buffer Cookie-based Co-processor Connection B URL B Client GMAC Pattern compare Inst Server Buffer Server GMAC Encryption Co-processor DMA Engine 24

25 Conclusions Until now FPGA are used for Framer/Interfaces Current FPGA are SoCs that can be used for the network systems (Lower cost, lower power) Less $ per packet Less W per packet Network IF FPGA NP/ Processors FPGA Network IF/ Fabric Switch Network IF FPGA Network IF/ Fabric Switch 25

26 Thank you! Questions? 26