Using DSPs for PSTN-ISDN Access

Transcription

1 Using DSPs for PSTN-ISDN Access Chris H.C. Ng, Ivan S.P. Chui and Lawrence K.W. Law Motorola Semiconductors Hong Kong Ltd. Abstract This paper presents a novel versatile Digital Signal Processor (DSP) modem architecture for 56Kbps Public Switch Telephony Network (PSTN) access and 64/ 128Kbps Integrated Services Digital Network (ISDN) access. A single Motorola s DSP56303 ([1], [2]) 24-bit digital signal processor is designed as a base 56K passive modem card, and the ISDN transceiver is made as a small add-on interface which will be attached to the base modem card for ISDN access. In case of 56K PSTN access, the DSP is dedicated for 56K modem data pump operations such as line probing, modulation/demodulation, echo cancellation etc. In case of ISDN access, a soft HDLC controller is implemented with DSP code to handle the layer-2 HDLC framing/ deframing. By using this architecture, the cost and the size of hardware for PSTN or ISDN access is reduced significantly; while it also provides a great flexibility and cost-effective upgradability for future network technologies. 1. Introduction Figure 1 shows this versatile DSP architecture for 56K modem and ISDN access : Figure 1 - Versatile DSP Architecture to Access Different Networks The base modem card acts like a typical passive modem that provides 56K data transfer over PSTN. To add flexibility for accessing ISDN, DSP56303 s second Enhanced Synchronous Serial Interface (ESSI) is reserved for interfacing the ISDN layer-1 transceiver; while the layer- 2 HDLC framing/deframing is implemented by the DSP code. This solution takes the advantages of passive modem design to reduce the size and cost of addon ISDN interfacing unit and to reuse the hardware in the base modem card effectively. In fact, this architecture is not limited to PSTN-ISDN access. For example, when the next generation remote access such as G. Lite is available, ESSI may connect the G. Lite interface and it becomes V.90/G. Lite hybrid modem without any hardware change of the base modem card. 2. Passive Hybrid Modem Model In the proposed passive modem model, the 56K modem data pump is performed by the DSP core while modem control code is implemented by host computer. During ISDN access, the DSP is then used to control the ISDN transceiver and perform HDLC framing/deframing so as to reduce CPU loading of host computer which, on the other hand, is responsible for ISDN control code. Figure 2 shows the system block diagram of the model. Passive model provides a low cost modem solution with insignificant consumption of the host system resources. For a 200Mhz Pentium PC, only 5-10% of CPU resources is dedicated for execution of control code. Passive modem also allows DSP code to be uploaded upon demand and therefore; the host computer can select either PSTN or ISDN access by loading appropriate DSP code and control stack. To minimize the hardware cost of ISDN add-on interface, the DSP imitates the functions of hardware HDLC protocol controller. Definitely, DSP is very suitable to accomplish such functions with its specially designed architecture and powerful instruction set. This passive hybrid model can extend to other network access. As ESSI is highly programmable to adapt serial link of other controllers and transceivers, the hybrid design is ready for communicating with hardware interface for other network accesses. Besides, the on-board DSP is a perfect piece of hardware to Figure 2 - Passive ISDN Plus 56K Hybrid Modem Model 104 International IC 99 Conference Proceedings

2 implement higher layer network protocols especially for those new or developing protocols, as the hardware controllers or decoders are usually not available in the early stage. In case the DSP is not capable to accomplish all necessary protocol layers, the host computer may contribute some of its computational power. This makes the base modem card more adaptable and applicable to future network access. 3. Implementation of passive hybrid modem using digital signal processor In this section, we present a passive hybrid modem design using Motorola s DSP bit Advanced Digital Signal Processor and MC ISDN-S/T transceiver [3]. The passive hybrid modem is a PCI-based internal ISDN/PSTN modem, which performs V.34/56K data pump and HDLC framing/deframing, while the modem control code and the ISDN control stack are executed by the host computer. Figure 3 shows the block diagram of the passive hybrid modem system for reference. D channel between the network termination (NT) and terminal equipment (TE). It features the interchip digital link which can connect gluelessly to DSP56303 s ESSI port. Then, the DSP performs layer-2 HDLC protocol and the host PC is responsible to ISDN control. 4. Implementation of HDLC controller with digital signal processor In traditional ISDN passive design, HDLC controller chip is required to drive the layer-1 transceiver and to handle the functions of ISDN data link layer. In the proposed hybrid design, such hardware chip is not necessary because the DSP, which is situated in the base mo- Table 1 summarizes the memory requirement and worst-case computational complexity of three major functions using DSP The DSP may handle more HDLC channels. For instance, it requires about 24 MIPs for one ISDN (2B+D) line and therefore, an 80Mhz DSP56303 can manage two ISDN lines. Figure 4: ISDN Software Structure of Passive Hybrid Model Figure 3 - Block Diagram of Passive Hybrid Modem Using Digital Signal Processor The passive ISDN plus 56K hybrid modem has three main sub-system blocks : System Interface Block, DSP System Block and Telecommunication Block. The host computer interfaces to the DSP through the System Interface Block while the DSP system block processes the host data and routes the modulated data to/ from the Telecommunication Block. The Telecommunication Interface Block provides connections from the DSP System Block to the PSTN and ISDN environments. The PSTN interface includes a Telephony CODEC interface, a Direct Access Arrangement (DAA) interface and an acoustic interface for full voice functionality. On the other hand, the ISDN interface should feature the European or North American ISDN line protocols. The MC provides layer 1 interface for the transportation of two 64 kbps B channels and one 16 kbps dem card, is capable to perform the functionality of HDLC controller with its superior processing power. Figure 4 describes the layered software structure and Figure 5 further shows the data flow diagram of HDLC encoder and decoder inside the DSP. It is noteworthy that the HDLC framing (or deframing) of B1, B2 and D channels needs not to be operated simultaneously by using data buffering. Therefore, the framing (or deframing) module can serve all three channels. Each channel instance has a data structure to store its state variables so as to allow the operation to be switched among channels. Figure 5: Data Flow of HDLC Encoder and Decoder 5. Conclusions A passive hybrid modem design is presented. It is based on a typical passive modem design with optional interface for other networks. In this paper, we illustrated the implementation of PSTN-ISDN hybrid modem model. ISDN transceiver and interface is made as an add-on unit which will be connected to the base modem card via the optional interface. To minimize the hardware cost and size, the DSP implements the layer-2 ISDN pro- International IC 99 Conference Proceedings 105

3 Table 1: Memory Requirement and Complexity of Major Functions of HDLC tocol and the ISDN control stack is situated in the host computer. Also, dynamic uploading of DSP code from host computer not only provides easy software upgradability but also enables smart switching between modem and ISDN functions. In general, the proposed model is not limited to ISDN access. It is also applicable to other emerging networks such as G. Lite and ADSL without hardware change of the base modem design. 6. References [1] DSP bit digital signal processor family manual, Motorola. [2] DSP56303 user s manual, Motorola. [3] MC ISDN S/T-Interface Transceiver, Motorola. Authors contact details Chris H. C. Ng Ivan S. P. Chui and Lawrence K. W. Law Motorola Semiconductors Hong Kong Ltd. Silicon Harbour Center, 2 Dai King Street, Taipo Industrial Estate, Tai Po, N.T., Hong Kong. Tel : (852) Fax : (852) r40121@ .sps.mot.com Presentation Materials Board 106 International IC 99 Conference Proceedings

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