Dillon M. Collins, Brendan S. Surrusco, Sven G. Bilén, Charles C. Croskey The Pennsylvania State University

Transcription

1 Implementation of a Modern Internet Protocol-Based Communications System and Error Detection and Correction System for Commercial Memory within a Radiation Hardened FPGA for a Low-Earth-Orbit Satellite Dillon M. Collins, Brendan S. Surrusco, Sven G. Bilén, Charles C. Croskey The Pennsylvania State University Small Satellite Conference 8-11 August 2005 Logan, Utah

2 Driving Mission: Penn State LionSat Project Mission Statement The LionSat mission will investigate the local ambient and perturbed plasma environments surrounding a small satellite in the Earth s ionosphere. LionSat will measure the ambient plasma environment and the satellite s ram and wake regions using a novel hybrid plasma probe instrument. LionSat will test a miniature RF ion thruster system that will augment the satellite spin, which is necessary for mapping the plasma environment surrounding the satellite. Technology Demonstration LionSat will demonstrate the Hybrid Plasma Probe as a plasma diagnostic instrument. LionSat will also test in situ a miniature RF Ion Thruster as a satellite spin control device. Science Mission Goals Primary Objectives: P1. To map the ram and wake plasma structure surrounding a small satellite P2. To collect data on ionospheric plasma in a variety of geophysically interesting locations in low Earth orbit P3. To test, on orbit, a miniature RF ion thruster Secondary Objective: S1. To test IP communications for uplink and downlink to a spacecraft in low Earth orbit

3 Spacecraft Technical Data Orbit Low Earth mission in 2006/07 6 months to 1 year lifespan Dimensions Diameter: inches Length: 18.5 inches Shape: Octagon Mass Budget 30 kg maximum Power Budget 26.2 W V bus depending on load

4 Communications System Requirements Overview Through-put, Encoding, and Synchronization System Resource Requirements Design Software Uplink Downlink

5 Communications System: Requirements Overview Satellite will interface with ground station like an internet node Primary applications for end-user access to spacecraft will be FTP, Telnet, and/or web browser Flight computer will act as mediator between enduser and spacecraft instruments Automatic store and forward system for spacecraft data will be included in the communications system IP based communications system

6 Communications System: Throughput, Encoding, and Synchronization Analysis shows need for 200kbps downlink and 9.6kbps uplink Uplink data will be mission profiles in text file format and user commands Guaranteed high rate not critical Downlink will be science data and spacecraft operations reports Requires greater guarantee of high throughput More realistic single node operation as well as throughput guarantee requires standardizing packet format Small to minimize data loss Easy to inject into terrestrial network with commercial hardware Easy to transmit over the space-ground link Maintain link when data for transmit not available Avoid loss of bit sync.

7 Communications System: System Resource Requirements Up- and downlink hardware must interface with the flight computer using available resources Standard serial bus protocols (RS-232, SPI, etc.) Simple custom interface involving general purpose I/O lines Communications software Capable of accomplishing the desired IP packetization Capable of deconstruction of packets, without loss of data due to delay Operate on a 200-MHz flight computer running Linux OS

8 Communications System: Software 5/6/7 - Application SCP/SSH MDP - NTP 4 - Transport TCP UDP 3 - Network IP 2 - Data Link PPP / HDLC 1 - Physical RF

9 Communications System: Uplink Pair of Chipcon CC2400DBK transceiver modules Contain RF and digital hardware necessary to create the desired wireless link using simple RS- 232 interface Provide sufficient throughput Accept and produce data in byte form Adjusted to the desired frequency band with simple RF front-end hardware

10 Communications System: Downlink Bit-Sync. Manager

11 Memory Protection System Requirements Single Event Effects Mitigation in High-Speed Memory Design Data Corruption Latchup/Over-current Protection A Simple SDRAM ECC Design An SDRAM ECC Design with Back-up Memory

12 Memory Protection: Single Event Effects Mitigation in High-Speed Memory Over long periods total accumulated dose can lead to device breakdown Short term concerns Corruption of information in high speed commercialquality SDRAM Bit flips Latchup Over-current events Ultimate goal is to extend the time between necessary computer resets to as long as possible

13 Memory Protection: A Simple SDRAM ECC Design FPGA-based error correcting circuit (ECC) that can correct up to 8 independent bit errors and warn of additional errors in a 32-bit data SDRAM word Accomplished using a simple 7,4 Hamming-code circuit 32-bit SDRAM flight computer data bus routed to an Aeroflex Eclipse FPGA where it is divided into 4-bit chunks On a write to RAM each 4-bit piece is passed through a separate 7,4 Hamming encoder Output is original 4 data bits plus 3 check bits (24 total check bits) Requires eight additional SDRAM chips, four per bank, to store the 56- bit encoded data word (each 7-bit set is routed to a separate chip) Read passes a 56-bit word from the RAM data bus to FPGA, where it is decoded Each 7-bit unit protected against a single bit error

14 Memory Protection: An SDRAM ECC Design with Back-up Memory Break 32-bit RAM bus into 4-bit chunks and apply 7,4 Hamming code to each chunk 24 check bits 6 additional SDRAM chips (3 per bank) to store check bits Encoding can correct up to 8 bit errors, errors reported to PC Mixing of check/data bits among RAM chips allows loss of one entire RAM chip to be tolerable Smart power switches in tandem to enable back-up RAM Fuses can be arranged in linked pairs switching between each other if fault occurs Implement encoder/decoder in rad-hard Aeroflex ECLIPSE FPGA

15 Conclusion Communications system design and simple memory error correcting code design have been successfully created in VHDL and simulated Communications system design has been implemented in hardware Combined total resource requirements for both systems uses less than 45% of the logic cells available in an Aeroflex Eclipse FPGA Future work will involve the implementation and testing of both circuits in separate units followed by testing of a combined implementation in one FPGA

16 Memory ECC