Caches. Parallel Systems. Caches - Finding blocks - Caches. Parallel Systems. Parallel Systems. Lecture 3 1. Lecture 3 2

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1 Parallel ystems Parallel ystems Parallel ystems Outline for lecture 3 s (a quick review) hared memory multiprocessors hierarchies coherence nooping protocols» nvalidation protocols (, )» Update protocol (Dragon) Protocol tradeoffs Block no. Direct mapped s Block placement Fully associative et et associative Direct mapped: (block address) OD (number of blocks in the cache) Fully associative: Blocks can go anywhere et associative: (block address) OD (number of sets in the cache) s s memories are small, fast buffers that are used to temporarily hold Recently used information nformation that might be needed in the near future Principle of locality Programs access a relatively small portion of their address space at any instant of time Temporal locality (locality in time): f an item is referenced, it will tend to be referenced again soon. patial locality (locality in space): f an item is referenced, items whose addresses are close by will tend to be referenced soon Q1: Where can a block be placed in a cache? Q2: How is a block found? Q3: What block is replaced on a miss? Q4: How are writes handled? Address s Finding blocks V Tag Data V Tag Data V Tag Data V Tag Data = = = = Hit Lecture 3 1 Lecture 3 2

2 Parallel ystems Parallel ystems s Block replacement and write policies Block replacement Direct mapped caches: Block can only go in one place et and fully associative caches: ust choose block to replace» Random» Leastrecently used Write policies Write through (store through)» Data is written to both the cache and to the memory Write back (copy back)» Data is only written to the cache. The modified data is written back to memory only when it is replaced. Further reading Computer Architecture A Quantitative Approach (Hennessy, Patterson) Computer Organization and Design (Patterson, Hennessy) Dancehall approach Hierarchies [cont.] nterconnect is a scalable pointtopoint network rather than a bus is divided into many logical modules All main memory is uniformly far away from all processors (UA) Drawback: leads to several hops in the interconnect Distributed memory Not symmetric ach node has its own local portion of the global main memory ost attractive approach for scalable multiprocessors (>1 processors) nterconnection network em em nterconnection network Hierarchies Hierarchies [cont.] hared cache Can be used to connect a small number of processors (28) nterconnect between the processors and the shared cache is a critical path id8s: connecting a few processors on a board Today: one strategy for multiprocessorsonachip Busbased shared memory Widely used for small to medium scale (23 processors) caling limit comes from the limited bandwidth on the bus witch (interleaved) ain (interleaved) Bus s reduces the bandwidth demand placed on the shared interconnect Use of several private caches rises a challenge of cache coherence Approaches nterconnect is visible to all processors => snooping technique Decentralized interconnect => directory based technique Fundamental property of memories A set of locations that hold values A read should return the latest value written to that location Lecture 3 3 Lecture 3 4

3 Parallel ystems Parallel ystems ome definitions Coherence operations: ingle read, write, or readmodifywrite access to a memory location A memory operation issues when it leaves the processor and is presented to the memory system A multiprocessor memory system is coherent if» Operations issued by any process occur in the order in which they were issued to the memory system by that process» The value returned by each read operation is the value written by the last write to that location in the serial order Two properties follows by the definitions Write propagation: writes become visible to other processes Write serialization: all writes to a location are seen in the same order by all processes nooping Protocols Basic definitions [cont.] noopy protocols ties together bus transs and the state transition diagram associated with a cache block Bus transs arbitration, command (read&write), and data transfer tate transition diagram ach cache block has a state associated with it, along with the tag and data (e.g., valid or invalid) tate changes is the same for all blocks and all caches, but the current state of a block in different caches may be different Two inputs to cache controller» requests issued by the processor» The bus snooper informs about bus transs nooping Protocols Basic definitions Coherence is maintained by having all cache controllers snoop on the bus and monitor the transs Key properties of a bus that supports coherence All trans that appear on the bus are visible to all cache controllers All transs are visible in the same order implest approach ingle level write through caches» This was the approach used in the first commercial busbased P s Coherence protocols nvalidationbased Updatebased nooping Protocols A twostate writethrough invalidation protocol Notation A / B means f trans A is observed, then trans B is generated Writethrough Writes are serialized by the order in which they appear on the shared bus Drawback: very store consumes bandwidth on the shared bus => Poor scalability PrRd / PrRd / PrWr / BusWr V PrWr / BusWr BusWr / Lecture 3 5 Lecture 3 6

4 Parallel ystems Parallel ystems nooping Protocols A threestate writeback invalidation protocol nooping Protocols A threestate writeback invalidation protocol [cont.] Writeback caches Processors can write in their local caches without any bus transs Actions on a write miss» Read block from memory» Update block» Retain block in modified (dirty) state so it can be written back to memory upon replacement Owner: The cache must supply the data upon a request for that block xclusive copy: This is the only cache with a valid copy of the block tates used:» odified () Only this cache has a valid copy of the block. ain memory may or may not have a valid copy» hared () Block is present in an unmodified state. Other caches may also have an copy» nvalid () xample Processor P3 reads U P3 writes U P2 reads U tate in P1 tate in P2 tate in P3 Bus X Data supplied by P3 cache nooping Protocols A threestate writeback invalidation protocol [cont.] Transs Bus Read ()» Generated by a PrRd that misses in the cache Bus Read xclusive PrWr / X (X)» Generated by a PrWr to a block that is Not in the cache, or PrWr / X n the cache, but not in the modified state» All other caches are invalidated Bus Write Back (BusWB) PrRd /» Generated by the cache controller on a write back PrRd / PrWr / PrRd / / / Flush X / Flush X / nooping Protocols A fourstate writeback invalidation protocol Four states are used () llinois protocol odified () xclusive ()» Only this cache has a copy of the block and it is not modified hared () nvalid () A new signal must be available on the interconnect hared: Determine (on ) if other caches holds a copy of this block Problem with threestate () protocol: Two bus transs are generated when the processor reads in and modifies a data item (even though there are never any sharers) xercise: Write a state transition diagram for the protocol. Lecture 3 7 Lecture 3 8

5 Parallel ystems Parallel ystems nooping Protocols A fourstate writeback update protocol Four states xclusiveclean ()» ame meaning as in haredclean (c)» everal caches may have a copy of this block haredmodified (m)» everal caches may have a copy of this block, and it is this cache s responsibility to update the main memory when the block is replaced from the cache odified ()» ame meaning as in Transs No invalid state => two more request types: PrRdiss, PrWriss New trans BusUpd: Broadcast the updated value on the bus so that all other caches can update themselves xample Processor P3 reads U P3 writes U P2 reads U nooping Protocols A fourstate writeback update protocol [cont.] tate in P1 c c c c tate in P2 c tate in P3 c m m m Bus BusUpd Data supplied by P3 cache P3 cache nooping Protocols A fourstate writeback update protocol [cont.] PrRdiss / (!) PrWriss / (); BusUpd PrRd / m PrWr / BusUpd / Update / / Flush PrWr / BusUpd(!) PrRd / PrWr / BusUpd() / Flush PrRd / BusUpd / Update c PrWr / BusUpd() PrRd / PrWr / PrRdiss / () PrWr / BusUpd(!) PrWriss / (!) The coherence protocol is a crucial design issue for a multiprocessor Protocol class (invalidation or update) Protocol states and s Protocol decisions interact with other design issues (e.g., latency and bandwidth demand on the interconnect) Goals: eet a costperformance target Have a well balanced system (no bottlenecks) Use simulation results to evaluate effect of protocol choices Lecture 3 9 Lecture 3 1

6 Parallel ystems Parallel ystems Fro m tate transitions per 1 data references Barnes Hut Raytrace Fro m,21,29,13,242,8664 1,1181,559,213,1,375,1 To,11,1,153 1, ,2.362,1856,2 97,1712,1277,1549,343, ,95,297,35,1,1, ,78 2,26,175, ,1 misses [cont.] Coherence misses: Occurs when blocks of data are shared among multiple caches True sharing: A data word produced (written) by one processor is used (read or written) by another.» The miss truly communicates newly defined data values False sharing: ndependent data words accessed by different processors happen to be placed in the same memory (cache) block» False sharing is an example of artifactual communication» ncreases with larger block size misses misses in uniprocessor context Compulsory (cold start) misses» First reference to a memory block by a processor Capacity misses:» All blocks that are referenced by a processor during the execution of a program do not fit in the cache Conflict (collision) misses:» Occurs when the collection of blocks referenced by a program maps to a single cache set does not fit in the set Tradeoff examples» Conflict misses can be reduced by reducing the block size» Cold start misses can be reduced by increasing the block size ummary hierarchies and cache coherence problem coherence through snooping protocols nvalidationbased protocols» imple protocol for writethrough caches» & for writeback caches Updatebased protocol Coherence protocol tradeoffs Frequency analysis of state transitions Tradeoffs in cache block sizes Lecture 3 11 Lecture 3 12