COVERAGE ANALYSIS IN VERIFICATION OF TOTAL ZERO DECODER OF H.264 CAVLD

Transcription

1 COVERAGE ANALYSIS IN VERIFICATION OF TOTAL ZERO DECODER OF H.264 CAVLD Akhilesh Kumar and Mahesh Kumar Jha Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India ABSTRACT H.264 video standard is used to achieve high quality video and high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile.the H.264 bitstream consist of zeros and ones.at one of the decoding stages of contextbased adptive variable length decoder (CAVLD), Total Zeros decoder is used to calculate the total zeros, which is the number of zeros before the last non-zero coefficient.h.264 specifies different lookup table to decode total zero, which is chosen depending on the number of non zero coefficients.in this paper the coverage analysis in verification of Total Zeros decoder of the CAVLD ASIC using open verification methodology (OVM) is proposed. KEYWORDS: H.264, CAVLC/CAVLD, OVM I. INTRODUCTION Today the verification engineer have outnumbered the design engineers for the most complex designs.studies revealed that about 70% of all respin of Ics are due to functional errors.verification has become the bottleneck in project's time-to-profit goal [1]. According to the International Technology Roadmap for Semiconductors (ITRS), in many application domains the verification of the design has become the predominant component of a project's development in terms of time,cost, and the human resorces dedicated to it [2]. H.264 is jointly developed by the ITU and ISO/IEC.It has better compression efficiency than previous coding standards,and it is also network-friendly,which makes it suitable for many kinds of network [3].This paper is just about the verification of VLSI design of Total Zero Decoder of H.264 CAVLD decoder.in this paper, the verification using OVM is built by developing verification components using SystemVerilog and OVM class library, which provides the suitable building block to design the test environment.ovm is an open source verification methodology library intended to run on multiple platforms and be supported by multiple EDA vendors. OVM is used for functional verification using System Verilog, inclusive with a following library of System Verilog code [4]. The test benches in OVM are composed of reusable verification components that are absolute verification environments. The method does not depend on vendor and can be interoperated with several languages and simulators. The methodology is completely open, and includes a strong class library and source code [4]. The work embodied in this paper presents the Verification of RTL Total Zero Decoder of CAVLD using OVM.Coverage analysis is a vital part of the verification process; it gives idea that to what degree the source code of the DUT(Design Under Test) has been tested.the design and analysis is carried out in QuestaSim from Mentor Graphics using QuestaSim-6.6b. II. PROPOSED INTERFACE DIAGRAM OF TOTAL ZERO DECODER 2.1 Interface Diagram The proposed interface diagram of total zero decoder is shown in Figure Vol. 1, Issue 5, pp

2 Figure 1. Interface diagram of total zero decoder Inputs to this process are bit stream, total coefficients and maximum number of coefficients. This process calculates the number of total zeros using the total coefficients, maximum number of coefficients and the bit stream. Total zeros are the number of zeros before the last quantized coefficient of the block. This process is basically a probability model where total zeros are derived from the bit stream by VLC models, which are separated by using the total coefficients and maximum number of coefficients in the standard. Maximum number of coefficients and total coefficients is used to select the model used to derive the coefficient token. After decoding the coefficient token, total zeros are derived from the look up tables (H.264 standard table 9.7, table 9.8 table9.9) [5] provided in the ROM. Output of this process is total zeros. 2.2 Port Description The port description of the proposed interface diagram of Total Zero Decoder is described in Table 1. Table 1.Port Description Signal Name I/O Bit Width Description Allowable Values System I/F clk1 I 1 Operative clock (dedicated to CAVLC) NA nreset I 1 Asynchronous Reset 0 Reset 1 No Reset sreset I 1 Synchronous Reset 1 Reset 0 No Reset Decode sequence control I/F dec_brk I 1 Request IP to stop the decoding process 0 IP continue decoding 1 IP stops decoding Bit stream parser I/F bitstream_i I 9 Input Bit stream from Getbits. 0 (2^9-1) TCTO I/F 198 Vol. 1, Issue 5, pp

3 tcoeff_i I 5 Tcoeff of 4x4 Block tcoeff_vld_i I 1 Valid signal for Tcoeff of 4x4 Block. 0 Not valid 1 - Valid Level Decoder I/F start_tz_i I 1 Start signal from controller 0 Wait 1- Start total zeros module Slice Dec Controller I/F cavld_ceb_i I 1 Valid signal read clock enable to ROM 0 Don t enable clock 1 Enable clock CAVLD Controller I/F maxcoeff_i I 5 Maximum coefficients of the block 0-16 shift_length_t z_o O 4 No of bits to be skipped. 0 9 shift_en_tz_o O 1 Valid signal for skip length 0 Disable 1 Enable Run before decoder I/F tz_valid_o O 1 Valid signal for Total Zeros 0 Not valid 1 valid total_zeros_o O 4 Total Zeros of 4x4 block Micro Architecture The Micro-Architecture of the Decoder is shown in Figure 2.The architecture of Total zero decoder is explained as follows: 1. Pipeline Stage 1: The value of maximum coefficients of a block is taken as input. Based on the value of maximum number of coefficients and the total coefficients the value of ROM address from which the total zero value of that particular block is found is calculated. The ROM table is designed as follows: For Chroma DC values address ranges from 0x00h to 0x17h 2. Pipeline Stage 2: For chroma 422 and where tc = 1 address ranges from 0x18h to 0x20h For chroma 422 and where tc > 1 address ranges from 0x21h to 0x58h For luma values where tc = 1 address ranges from 0x59h to 0x68h For luma values where tc > 1 address ranges from 0x69h to 0x427h In this stage the value of total zero is read from the TZ Rom and registered and sent as output along with tz_end. 2.3 Timing Diagram The timing diagram of Total Zero Decoder is shown in Figure Vol. 1, Issue 5, pp

4 Figure 2. Total zeros decoder Architecture Diagram 2.4 Applying OVM to Total Zero Decoder Figure 3.Timing Diagram of Total Zero Decoder A verifocation plan is developed to verify the Total Zero Decoder in the OVM environment.the suggested decoder is taken as DUT and then it was interfaced with the OVM environment.the suggested DUT was written using verilog coding.the open verification environment is created by joining different components written in SystemVerilog coding, those componet are Transaction, Sequence, Sequencer, Driver, Coverage, Assertion, Interface, Monitor, Scoreboard, Agent, 200 Vol. 1, Issue 5, pp

5 Environment and finally Top module.the Clock signal for the DUT is generated in top module.the top module contains the typical HDL construct and SystemVerilog interfaces. In the top module the DUT is connected to the test environment through the interface.the compilation and verification analysis is carried out in QuestaSim 6.6b form Mentor Graphics. III. SIMULATION RESULTS To measure the coverage of the decoder the code was compiled and then simulated to get the encoded output. The simulated output is shown in Figure 4 and Figure 5. Figure 4. Simulation result when Figure 5.Simulation result when maxcoeff_i is 8 maxcoeff_i is 16 IV. COVERAGE ANALYSIS The Coverage Summary and Coverage Report gives the details of the functional coverage when complete Analysis was done for the decoder and coverage report as shown in Figure 6 was generated it is found that the coverage is less than 100%. Figure 6.Coverage results Figure 7.Coverage results V. CONCLUSION AND FUTURE SCOPE H.264/AVC is a public and open standard. Every manufacturer can build encoders and decoders in a competitive market. This will bring prices down quickly, making this technology affordable to 201 Vol. 1, Issue 5, pp

6 everybody. There is no dependency on proprietary formats, as on the Internet today, which is of almost importance for the broadcast community. OVM is clearly simulation-oriented. The test benches in OVM are composed of reusable verification components that are absolute verification environments. The method does not depend on vendor and can be interoperated with several languages and simulators. The methodology is completely open, and includes a strong class library and source code. In this work OVM based Total Zero Decoder VIP (Verification intellectual property) is developed. The decoder is subjected to various analyses. The decoder is verified for functional coverage using QuestaSim. It is observed after compilation and simulation that the verification environment is responding accurately with no errors. The Coverage Report of Total Zero Decoder is 100%. This work can be extended to verify the various IP in the OVM environment and minimize the bugs generated, basically in the corner cases, thus reducing the verification time of a design. ACKNOWLEDGEMENT This work was supported by TATA ELXSI, Bangalore. REFERENCES [1] J.Bergeron, What is verification? in Writing Test benches: Functional Verification of HDL Models, 2 nd ed. New York: Springer Science, 2003, ch.1, pp [2] International Technology Roadmap for Semiconductors [Online]. Available: [3] R. Schafer, T. Wiegand and H. Schwarz, "EBU TECHNICAL REVIEW of the emerging H.264/AVC standard, Heinrich Hertz Institute, Berlin, Germany,January 2003 [4] [5] ITU-T Rec. H.264, ITU-T Study Group, March 2009,Available: /rec/t-rec-h s/en. [6] [7] Chris Spear, SystemVerilog for Verification, New York : Springer, [8] OVM User Guide,Vers. 2.1,OVM world,december 2009, Available: www. ovmworld.org. [9] Iain E. Richardson, The H.264 Advanced Video Compression Standard,2 nd ed.uk : Wiley, 2010, pp [10] "VLSI Design of H.264 CAVLC Decoder", China-Papers, February 16,2010, [Online]. Available: [11] "The Algorithm Study on CAVLC Based on H.264/AVC and Its VLSI Implementation", China- Papers, May 31,2010, [Online].Available: [12] "Design of CAVLC Codec for H.264",China-Papers, March 24, 2010, [Online]. Available: [13] Wu Di, Gao Wen, Hu Mingzeng and JiZhenzhou, A VLSI architecture design of CAVLC decoder, ASIC,2003. [14] Tien-Ying Kuo and Chen-Hung Chan, Fast Macroblock Partition Prediction for H.264/AVC, in IEEE International Conference on Multimedia and Expo (ICME2004), pp , [15] Y.L. Lee, KH. Han, and G.J. Sullivan, Improved lossless intra coding for H.264/MPEG-4 AVC, IEEE Trans. Image Processing, vol. 15, no. 9, pp , Sept [16] [17] OVM Golden Reference Guide,Vers. 2.0, DOULOS, september 2008, Available: [18] Mythri Alle, J Biswas and S. K. Nandy, "High performance VLSI architecture design for H.264 CAVLC Decoder",in Proceedings of Application-specific Systems, Architectures and Processors,2006 [19] "An Introduction to SystemVerilog",Asic,[Online].Available: /Index_files/tutorials/SystemVerilog_veriflcation.ppt [20] N. Keshaveni, S. Ramachandran and K.S. Gurumurthy "Implementation of Context Adaptive Variable Length Coder for H.264 Video Encoder",International Journal of Recent Trends in Engineering, Vol 2, No. 5, pp , November [21] Mihaela E.Radhu and Shannon M.Sexton, Integrating Extensive Functional Verification into digital design Education, IEEE Trans. Educ., vol. 51, no. 3, pp , Aug [22] Donghoon Yeo and Hyunchul Shin, "High Throughput Parallel Decoding Method for H.264/AVC CAVLC",ETRI Journal, Vol. 31, no. 5, pp , October Vol. 1, Issue 5, pp

7 Authors Akhilesh Kumar received B.Tech degree from Bhagalpur University, Bihar, India in 1986 and M.Tech degree from Ranchi University, Bihar, India in He has been working in teaching and research profession since He is now working as H.O.D. in Department of Electronics and Communication Engineering at N.I.T. Jamshedpur, Jharkhand, India. His interested field of research is analog circuit and VLSI design. Mahesh Kumar Jha received B.Tech. Degree from Biju Patnaik University of Technology, Orissa, India in He is now pursuing M. Tech in Department of Electronics and Communication Engineering at N.I.T. Jamshedpur, Jharkhand, India. His interested field of research is VLSI Design. 203 Vol. 1, Issue 5, pp