On the Implementation of Long LDPC Codes for Optical Communications

Transcription

1 On the Implementation of Long LDPC Codes for Optical Communications Andrew J Wong Department of Electrical and Computer Engineering McGill University Montréal, Québec October 2009 A thesis submitted to McGill University in partial fulfilment of the requirements of the degree of Master of Engineering c Andrew J Wong, 2009

2 ACKNOWLEDGEMENTS I would like to thank Prof Warren Gross for the opportunity to conduct my studies and research with him and the members of the Integrated Circuits and Systems laboratory His enthusiasm, his inspiration, and his great desire to improve current technologies taught me many things throughout these two years I would also like to thank Dr Saied Hemati for his support and advice throughout my research His role as a mentor helped me develop the ideas presented in this work I would also like to thank François Leduc-Primeau for the use of his simulator; it helped when I needed to get some quick results and was pressed for time Finally, I d like to thank my family and friends for their support throughout my studies I couldn t have done it without them - ii -

3 ABSTRACT Very powerful long low-density parity-check (LDPC) codes, such as the ITU G9751 Standard (32643, 30592) LDPC Code [1], have been considered for optical communications Traditional implementations of such long codes result in circuits requiring millions of interconnections, which are not affordable This thesis investigates the performance of the hard-decision differential decoding with binary message-passing (DD-BMP) algorithm [2], a low-complexity algorithm requiring a minimal number of wires due to its binary messages Our simulation results for the ITU G9751 standard demonstrate that hard-decision DD-BMP algorithm outperforms the results provided in the standard, and that the gap between the decoding performance of hard-decision DD-BMP and hard-decision sum-product is small at high signal-to-noise ratios (SNR) We also present a novel design methodology for implementing a soft-decision decoder by exploiting the code s structure An implementation-efficient architecture is presented using a partially-parallel adaptation of the min-sum algorithm known as the line-passing algorithm The line-passing algorithm makes soft-decision decoding available while requiring a minimal number of interconnections, which is attractive for long-haul optical communication systems - iii -

4 ABRÉGÉ Les télécommunications optiques ont souvent besoin de codes de correction longues et efficaces tel le standard LDPC du ITU G9751 (32643, 30592) [1] Les réalisations traditionnelles de ce code exigent des millions de fils et ne sont pas économiques Cette thèse présente l étude du décodage de l algorithme différentiel avec un passage de message binaire (DD-BMP) [2] avec décision-dur Lorsqu il s agit d un algorithme bas-complexité avec des messages binaire, un nombre minimal de fil est exigé Nos résultats de simulations pour ce code montre que le DD-BMP avec décision-dur a une meilleure exécution que celui du standard, et que la différence entre le DD-BMP avec décision-dur et l agorithme sum-product (SP) avec décision-dur est petite aux rapports de signal-bruit (SNR) élevés Cette thèse présente aussi une méthodologie originale pour la réalisation d un algorithme de décodage avec décisiondoux en exploitant leur structure Une architecture d exécution-efficient est présentée utilisant une approche partiel-parallèle avec l agorithme line-passing, une modification de l agorithme min-sum (MS) Cette architecture permet à l information de doux-décision d être employée tout en exigeant un nombre minimal de fils qui serait intéressante pour des systèmes de télécommunication optique de long-courrier - iv -

5 TABLE OF CONTENTS ACKNOWLEDGEMENTS ii ABSTRACT iii ABRÉGÉ LIST OF TABLES iv vii LIST OF FIGURES viii 1 Introduction 1 11 Optical Communications 1 12 Contributions & Thesis Structure 4 2 Low-Density Parity-Check (LDPC) Codes and Iterative Decoding Algorithms 6 21 Low-Density Parity Check (LDPC) Codes Tanner Graphs Iterative Decoding Algorithms Soft-Decision Versus Hard-Decision Receivers 9 22 Iterative Decoding Algorithms Sum-Product Algorithm (SPA) Min-Sum Algorithm (MS) Low-Complexity Algorithms Gallager A & B Decoding (GA & GB) Differential-Decoding with Binary Message Passing (DD- BMP) Performance Comparison Summary 18 3 Hard-Decision Differential-Decoding with Binary Message-Passing (DD- BMP) 19 - v -

6 31 Hard-Decision Differential-Decoding with Binary Message-Passing for the ITU G9751 Standard (32643, 30592) LDPC Code Optimization & Simulations Results Estimated Throughput & Algorithm Modification Architecture Check Node Variable Node Summary 28 4 Efficient Implementation of the Min-Sum (MS) Algorithm The Min-Sum Algorithm for the ITU G9751 Standard (32643, 30592) LDPC Code ITU G9751 Standard (32643, 30592) LDPC Code Connectivity Matrix Address Calculation Line-Passing Algorithm Proposed Algorithm Possible Implementation Considerations Scheme 1 - One Line, Two Passes Scheme 2 - One Line, One Pass Scheme 3 - Pipeline Scheme 4 - Seven Lines Scheme 5 - Cyclic Shift Scheme Scheme 6 - Split Matrix Cyclic Shift Scheme Estimated Throughput Summary of Hardware Costs Architecture Simple Line-Passing Implementation for the Min-Sum Algorithm (Scheme 1) Line-Passing Implementation for the Cyclic Shift Scheme with Fixed Interconnect (Scheme 5B) Line-Passing Implementation for the Split Matrix Cyclic Shift Scheme with Fixed Interconnect (Scheme 6) Implementation Synthesis Results Summary 74 5 Conclusion 76 References 78 - vi -

7 Table LIST OF TABLES page 3 1 Hardware requirements for a variable node Hardware requirements for a processing node (Type-1) in Scheme Hardware requirements for a memory node (Type-1) in Scheme Hardware requirements for a center node (Type-1) in Scheme Hardware requirements for a center node (Type-2) in Scheme Hardware requirements for a processing node (Type-2) in Scheme Hardware requirements for a memory node (Type-2) in Scheme Hardware requirements for a message memory (Type-1) in Scheme 5A Hardware requirements for a message memory (Type-2) in Scheme 5B Hardware requirements for a message memory (Type-3) in Scheme Summary of the hardware costs for the presented schemes (* these memory nodes also require an additional adder as part of their structure) Synthesis results for a memory node (Type-2) Synthesis results for a message memory (Type-3) Synthesis results for a processing node (Type-2) Total amount of required components for Scheme 6 with q = Hardware requirements estimate for a processing node (Type-1) from Scheme vii -

8 Figure LIST OF FIGURES page 2 1 A Tanner graph describing a (6, 3) code Performance of the different algorithms using floating-point input Simulation results for hard-decision DD-BMP with varying counter sizes, α = Simulation results for hard-decision DD-BMP with varying α for select counter sizes Overall comparison Check node architecture Variable node architecture Diagram of the connectivity matrix M showing the indices Diagram of M illustrating how the nodes are connected by a line Diagram of M showing the path of one line Diagram of nodes and a portion of their connections between rows Illustration of a node s connections in the connectivity matrix and how it is loaded into hardware Scheme 1 - Basic line-passing implementation Flowchart for Scheme Scheme 2 - Line-passing starting at both ends Flowchart for Scheme Scheme 3 - Pipelined method Scheme 4 - Line-passing with all seven lines implemented 53 - viii -

9 4 12 Message passing example Scheme 5A - Line-passing scheme with cyclic shift memory architecture using shift message memory registers Scheme 5B - Line-passing scheme with cyclic shift memory architecture using a fixed interconnect Flowchart for Scheme Scheme 6 - Line-passing with a split M matrix format Flowchart for Scheme ix -

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11 Chapter 1 Introduction 11 Optical Communications Channel coding has become extremely important and widely used in today s communications systems It has been demonstrated over and over that it can significantly improve the performance of any kind of communications link From cellular telephone networks and computer networks to deep space communications and optical storage devices, error correction codes have been implemented to improve the reliability and performance of a communications or storage system Due to natural noise that can corrupt transferred or stored data, any modern digital communication or optical communication system employs some sort of channel code that maps a sequence of information bits to a sequence of symbols that will allow the receiver to detect and correct errors to a certain degree Forward error correction (FEC) is a common error control scheme in which redundant information is added to the source message to allow the receiver to correct errors without requiring costly data retransmissions This is the greatest advantage of using FEC However, since more redundant data needs to be sent, more bandwidth is necessary - 1 -

12 Chapter 1 Optical communications involve any type of communications channel that uses optical waveguides to transmit information from one point to another [3] Optical fiber, for example, is one of the most common types of channel available and has played a major role in the development of recent technologies [4] This technology allows transmission over longer distances at higher bandwidths than other forms of communication, and have largely replaced traditional copper wire communications in today s networks In traditional wireless or radio communication, the demodulated symbols can often be recovered with a certain degree of accuracy In some situations, receivers are only capable of recognizing logical values 0 and 1 This is known as harddecision input In the cases where values in between 0 and 1 are available, it is called soft-decision The use of soft-decision decoders often provide quite an improvement over hard-decision decoders However, this additional information is rarely available and very costly in optical systems, therefore soft-decision decoders are not common in high-speed optical communications [5] At the moment, it is still very difficult to extract soft information from high-speed optical systems, but it is still of great interest as this technology will become more affordable in the future While hard-decision algorithms are inferior to soft-decision algorithms in terms of decoding performance, they are still attractive due to their lower complexity and higher speed Reed-Solomon (RS) codes have the ability to correct burst errors and operate at high speeds while providing good hard-decision performance Unfortunately, the decoding complexity is no longer practical when using very long codes The first FEC systems were implemented in optical systems to help against a form of noise inherent in optical amplifiers known as amplified spontaneous emission 2

13 Chapter 1 (ASE) [6] and were able to provide coding gains of up to 6dB While being successful in combatting the original problem of ASEs, other unwanted effects were introduced by increasing transmission rates A second generation of FEC systems were introduced to aid against unwanted nonlinear effects and dispersion which had coding gains of up to 8dB [7] and transmission rates of 10Gbps The creation and establishment of agile width (40/100Gbps) technologies in optical communications once again provided resources with different requirements than previous technologies In this third generation of FEC systems, known as Super-FEC, optical channels were faced with the removal of optoelectronic conversions in order to conserve optical transparency While the technology for signal-regeneration systems in this era are still being perfected, coding gains of over 10dB have been attained [5], [6] Low-density parity-check (LDPC) codes such as the ITU G9751 Standard (32643,30592) LDPC code are one of the latest technologies applied to this field In recent years, LDPC codes [8] have been studied extensively This class of codes have been shown to include some of the most powerful known capacityapproaching codes [9], and perform very well using iterative decoding algorithms Known as message-passing algorithms, these iterative decoding algorithms have relatively low complexity due to the low density of the parity-check matrix and the associated Tanner graph [10] of the code However, implementations are difficult to realize when dealing with very long codes due to the huge amount of wires required in the circuit In this thesis, we focus on the efficient implementation of long and powerful LDPC codes for optical communication systems and in particular, we consider the ITU G9751 Standard (32643,30592) LDPC code 3

14 Chapter 1 The implementation of long LDPC codes such as the ITU G9751 standard code [1] used in optical communications can be very difficult due to the large number of required interconnections When using an algorithm such as the classic sum-product (SP) algorithm for example, the complexity of the operations adds greatly to the difficulty of implementing such a circuit The (32643, 30592) LDPC code in the ITU G9751 standard has variable nodes of degree 7, resulting in almost edges for the circuit Considering that each edge requires two connections, each consisting of six wires to carry 6-bit messages each, then 276 million wires are required just for the interconnections between the nodes The wiring itself represents a huge challenge In this thesis, we consider this code and propose implementation efficient schemes for a fully parallel configuration using the low-complexity differential-decoding with binary message-passing (DD-BMP) algorithm as well as a partially-parallel solution using the min-sum (MS) algorithm In general, two situations can occur in optical communications: one where soft-decision information is available, and one where only hard-decision information is provided We present an optimized DD-BMP algorithm for use with hard-decision channels and show that while its performance is very close to that of hard-decision MS, it has much lower complexity and a relatively low number of wires For use with soft-decision channels, we consider an adaptation of the MS algorithm based on its performance and compatibility with our novel architecture 12 Contributions & Thesis Structure Chapter 2 will explore existing iterative decoding algorithms and their application for the ITU G9751 Standard LDPC Code General background on LDPC 4

15 Chapter 1 codes as well as a brief overview of some iterative decoding algorithms can be found as well A performance comparison between various algorithms on the ITU G9751 code is presented We will show that the differential-decoding with binary message passing (DD- BMP) is very suitable for use with the ITU G9751 Standard in Chapter 3 when only hard-decision inputs are available We optimize the decoding performance, present a modification to the algorithm to increase throughput, and suggest a potential architecture for the hard-decision DD-BMP decoder In Chapter 4, we exploit the structure of the ITU G9751 code to design an efficient low-complexity partially-parallel min-sum decoder Strategies and analysis of various implementation schemes are also discussed and the line-passing algorithm, an adaptation of MS, is presented for use with these possible architectures Synthesis results for the nodes of the new architecture on a Xilinx Virtex-5 are presented as well The goal of these two chapters is to present a solution to the difficult task of implementing very large LDPC codes, and the discoveries about the code s structure which make it possible Finally, Chapter 5 will discuss potential future work and summarize the material presented in this thesis 5

16 Chapter 2 Low-Density Parity-Check (LDPC) Codes and Iterative Decoding Algorithms 21 Low-Density Parity Check (LDPC) Codes Low-density parity-check codes are a form of linear error correctional codes discovered by Gallager in the early 1960s [8] They are block codes characterized by a sparse parity-check matrix H These codes have been shown to achieve performance very close to the Shannon limit with iterative decoding algorithms [11], [12], but have only recently been rediscovered and studied extensively However, since their rediscovery, they have become a major competitor to turbo codes for error control schemes in many communication systems where high reliability is required [9], [13] Many LDPC codes have even been selected for standards such as the IEEE 8023an standard for use with 10Gigabit Base-T Ethernet [14], the ITU-T Ghn/G9960 standard for networking over power lines, phone lines and coaxial cables [15], the ETSI s DVB-S2 standard for digital video broadcasting [16], and the IEEE 80216e WiMAX standard for microwave communications [17] - 6 -

17 Chapter 2 Each code is defined by a set of (N K) parity-check equations, where N is the length of the entire codeword and K is the length of the source message The associated sparse parity-check matrix H is of size M N The rate R of a code is defined as R = K/N The source messages are encoded by a dense generator matrix G defined by HG T = 0 A codeword c is generated from a source message s by c = sg Obviously, any valid codeword c satisfies ch T = 0 In order to verify if a received message, y, is a valid codeword, yh T is computed and if it is equal to 0, then a valid codeword has been found An LDPC code is also defined by the number of ones in each column or row of its parity-check matrix H The degree of a column d c and degree of a row d v are determined by the number of ones in that particular column or row A (d v, d c ) code is called regular if all of the rows have exactly d c ones and all of the columns have exactly d v ones, otherwise, it is known as an irregular code In general, LDPC decoders employ Tanner graphs and iterative decoding algorithms defined on these graphs that are described in the next section 211 Tanner Graphs Tanner first introduced bipartite graphs to represent different families of codes that were generalizations of Gallager s LDPC codes [10] The graph is used to describe the constraints or equations between independent variables and local functions [18] LDPC codes are defined by a set of information bits tied together by paritycheck equations These graphs are used to illustrate how these relationships and how the variable nodes are connected to the check nodes of the code Figure 2 1 shows and example of how a (6, 3) code could be represented by a Tanner graph Each 7

18 Chapter 2 check node represents one parity check equation, and the variable nodes that are connected to them represent the corresponding codeword bit Check Nodes Variable Nodes Figure 2 1: A Tanner graph describing a (6, 3) code 212 Iterative Decoding Algorithms Iterative decoding algorithms work by passing messages from variable nodes to check nodes, and vice versa, along the edges of a graph In fact, Gallager originally discussed a few different iterative decoding algorithms based on the nodes and edges of a bipartite graph [19] Variable nodes would correspond to the codeword bits, and the check nodes would correspond to the parity-check equations of H In general, 8

19 Chapter 2 the best performing LDPC decoding algorithms work iteratively and information is exchanged between neighboring nodes of the graph by passing messages along the edges Each message along each edge usually represents an estimation of the associated variable node s value and some degree of reliability for that estimate Using this information, a variable node can determine if its own believed value is correct or if it is in fact in error Of course, the steps used in processing these messages depend on the chosen algorithm, and a few key algorithms will be explained in the following sections 213 Soft-Decision Versus Hard-Decision Receivers The information received from the channel is not necessarily represented in the same manner as it was sent from the source This difference is mainly due to the limitations of the channel itself The decision made by the receiver based on the received information is called a hard-decision if the value of a single bit can either be 0 or 1 However, if the receiver is able to distinguish between a set of quantized values between 0 and 1, then it is called a soft-decision receiver Many, if not all, decoding algorithms can benefit from the extra data provided by a soft-decision receiver In optical networks, soft-information is not always readily available Many technological complications related to these very high transmission rates prevent highresolution soft-information channels from being practical, and most decoders will receive a hard-decision or 2 to 3-bit soft information 22 Iterative Decoding Algorithms This section discusses some of the iterative decoding algorithms used in LDPC decoding We consider a binary LDPC code C with its associated parity-check 9

20 Chapter 2 matrix H over a binary-input additive white Gaussian noise (AWGN) channel which is memoryless at the output The noise n i on the channel is a zero-mean Gaussian noise with variance σ 2 Let y i = x i + n i be the received value corresponding to the originally transmitted symbol x i For AWGN channels with a power spectral density of N 0 /2, we have σ 2 = 1/(2RE b /N 0 ) where R denotes the code rate and E b is the energy per information bit Let the current iteration number be denoted by l Each algorithm continues until a maximum number of iterations, l = I MAX, has been reached or a codeword has been found Let m (l) v i c j node c j at iteration l denote the message sent from variable node v i to check 221 Sum-Product Algorithm (SPA) The sum-product algorithm (belief propagation) [20], [21] is the most powerful known iterative decoding algorithm [18], [22] Soft-information is used both at the input and the output of this decoder At the input, a-priori likelihood values corresponding to the received channel values are used while the output is an estimation of the a-posteriori likelihood of each codeword bit For each iteration, the resulting likelihoods for each bit is used as inputs for the next iteration until all parity-check equations have been satisfied or the maximum number of iterations have been met The algorithm can be described as follows: 1) Initialization Each variable node is initialized with the associated likelihood value computed from the received channel values These values are sent as the first round of messages to its neighboring check nodes 2) Check node & variable node updates 10

21 Chapter 2 Each check node c j sends message m cj v i to all of its neighboring nodes This message represents the most likely value of the symbol The variable nodes then send messages m vi c j to each of its connected nodes This message represents the belief of the symbol s value, and includes the information from all of the check messages it received except for c j 3) Codeword check & hard-decision A hard-decision is made for each codeword bit and then it is checked to see if all parity-check equations are satisfied If they are, or if the maximum number of iterations has been reached, the decoding is terminated and the hard-decision is sent as the estimated codeword If not, the algorithm continues from Step 2 This algorithm can be used with different message representations Common representations include using the likelihood ratio, log-likelihood ratio, likelihood difference, and signed log-likelihood difference [18] Each one provides the same result, but the computations required for each node is slightly different In general, the log-likelihood ratio (LLR) is used to represent the messages because it simplifies the operations required by the variable nodes For an LLR implementation, the received channel value y i is converted to the LLR domain and denoted as L i = 4y i /N 0 This value is used to initialize the variable nodes and start the algorithm The check node is updated by Equation 21, and the variable node update rule is given by Equation 22 The conversion to a hard-decision for a codeword bit is determined by the sign of the sum of all of the received messages and its initial received value L i 11

22 Chapter 2 c j v i = 2 tanh 1 m (l) v k N(c j )\v i tanh ( ) m (l 1) v k c j (21) 2 m (l) v i c j = L i + c k N(v i )\c j m (l 1) c k v i (22) It has been shown that the computational complexity for one iteration of SPA is of the order O(4Md v ) [21], [23], [24] While SPA has very good decoding performance, it suffers from complicated circuitry and increased complexity 222 Min-Sum Algorithm (MS) The min-sum algorithm [21] is similar to SPA in that it is also a soft-input/softoutput decoding algorithm which uses likelihood values to estimate each codeword bit The main purpose for the introduction of the min-sum algorithm is that while similar to SPA, it uses an approximation for the check node process so that it is less computationally complex and easier to implement [25], [26] For MS decoding, Equation 21 is replaced by Equation 23 While this is an approximation, MS still provides accuracy close to that of SPA It is known that the check nodes in the MS algorithm overestimate the messages, and that by reducing these messages the decoding performance improves [27] The normalized/offset min-sum [27], [28], algorithm is one such modification It has also been noted that successive relaxation can improve the decoding performance of iterative decoders, and relaxed min-sum [29] has been shown to have better performance than SPA for many codes These 12

23 Chapter 2 variations have been shown to be well-suited for partially-parallel implementations as well m (l) c j v i = m (l 1) min v v k N(c j )\v i c j i v k N(c j )\v i sgn(m (l 1) v i c j ) (23) With this new check node update scheme, it is no longer necessary to have complex operations Instead, all that is necessary are the first and second minimums along with the overall sign of the messages received by the check node as shown in Equation Low-Complexity Algorithms In this section we consider a few low-complexity binary message-passing decoding algorithms and investigate their benefits and limitations for implementing long LDPC codes that have been considered for optical communication systems 231 Gallager A & B Decoding (GA & GB) Gallager introduced a hard-decision decoding algorithm now known as Gallager s Algorithm A as part of his thesis [8] Binary messages are used to pass information between the variable nodes and the check nodes It can be described as follows: 1) Initialization All of the variable nodes send their received values to their neighboring check nodes 2) Check node update The check node messages are calculated by Equation 24 13

24 Chapter 2 m (l) c j v i = v k N(c j )\v i m (l 1) v k c j (24) 3) Variable node update Each variable node sends the following message to associated check node c j : if all incoming messages from the check nodes other than c j are of the same value, then than value is sent Otherwise, it sends the received value from the channel 4) Codeword check & hard-decision Repeat from Step 2 until all parity-check equations are satisfied or the maximum number of iterations has been reached As shown, Gallager s Algorithm A is a very basic and simple decoding algorithm It requires only logical operations and binary messages resulting in much lower complexity than SPA or MS at the expense of its poor decoding performance Gallager s Algorithm B is a slight modification of Algorithm A which renders it more powerful Instead of a variable node only changing its believed value when all of the incoming messages agree, a threshold value is used For example, a node will change its value if 80% of the incoming messages agree It can be seen that Algorithm A is just a special case of Algorithm B with the threshold value set to 100% While the optimal threshold value is dependent on each code and needs to be determined through simulation, it is obvious that this transition towards using received information more efficiently results in better performance [30], [31] In terms of complexity, this is the algorithm with the lowest complexity available The check nodes are only required to perform a simple XOR function while the variable nodes perform a comparison of its incoming messages The obvious drawback 14

25 Chapter 2 is that the algorithm does not take advantage of all the information possible which results in performance loss Each check node must perform d c 2 two-input XOR operations per edge while each variable node requires one comparison per edge 232 Differential-Decoding with Binary Message Passing (DD-BMP) The DD-BMP algorithm [2] is an iterative decoding algorithm that combines the simplicity and low-complexity of bit-flipping algorithms while using soft information to making decisions This dramatically improves the decoding performance without requiring the complex hardware of the SPA or MS algorithms It also keeps the edge count low by using binary messages This is a crucial criteria for choosing a suitable decoding algorithm for long LDPC codes, which is the topic of this work This algorithm requires that the coded bits {0, 1} are mapped to {1, 1} as channel input symbols Received values y i are clipped at a threshold value c th so that they fall in the range of [ c th, c th ] These values are then quantized and denoted as Q(y i ) Each edge of the graph has a memory associated with it, denoted B (l) ij the edge connecting variable node v i and check node c j at iteration l The soft values inside the edge memories represent the node s belief, and allow improved decoding accuracy All messages passed between the nodes are binary with alphabet A = {+1, 1} The algorithm can be described as follows: 1) Initialization The vector z i is used to estimate the current codeword and to check if it is valid The individual elements of z are determined by z i = (1 sgn r (y i ))/2, where sgn r (x) = 1 for x > 0, 1 for x < 0, and either 1 or 1 randomly with equal probability if x = 0 If z satisfies all parity-check equations, then the algorithm is terminated and z represents the estimated codeword If this is not the case, then for 15

26 Chapter 2 all of the edge memories are initialized by their respective quantized received values, Q(y i ) Messages sent from the variable nodes to the check nodes are simply the sign of Q(y i ) 2) Check node update The check node messages are calculated by 3) Variable node update m (l) c j v i = v k N(c j )\v i m (l 1) v k c j (25) Each edge memory of a variable node is updated by adding the sum of the incoming messages on the other edges to itself Outgoing messages are calculated in the same way as before, by taking the sign of each edge memory 4) Codeword check & hard-decision The estimated codeword z is determined by obtaining the sum of the signs of all the edge memories of a node, and including the sign of its received value Let this sum be denoted by D i and z i = 1 sgn(d i), i = 1,, N, if D i 0 If all 2 the parity check equations are satisfied by z or the maximum number of iterations has been reached, then z is sent as the estimated codeword and the decoding ends Otherwise, the algorithm is repeated from Step 2 It has been shown that the DD-BMP algorithm outperforms many other lowcomplexity algorithms [2], and for some LDPC codes it even outperforms min-sum decoding algorithm, all while maintaining simple hardware While it does experience some performance loss compared to SPA, its simple hardware and reduced wiring 16

27 Chapter 2 makes it attractive In terms of complexity, each check node must perform d c 2 twoinput XOR operations per edge However, if the check node operation is performed over all of the incoming messages first, and then exclude the specific edge s message afterwards, the number of operations can be reduced to slightly less than twice the number of edges In terms of the variable nodes, d v 2 two-input binary additions and one two-input integer addition must be performed per edge Once again, the binary additions can be reduced to slightly less than twice the number edges in the same manner as before The final codeword check and hard-decision functions require one two-input integer addition per edge The computational complexity is higher than majority-based algorithms and a q-bit memory is required for each edge in the graph This means that a total of q d v more memory is required compared to purely hard-decision algorithms; however, the complexity is still much lower than SPA and MS 24 Performance Comparison A performance comparison was done using Monte Carlo simulations of the ITU G9751 Standard (32643,30592) LDPC code on an AWGN channel as described earlier For all simulations, the maximum number of iterations is set to 100, and 200 word errors are found for each simulation point Performance results are also compared to the popular RS(255,239) code which has the same rate The performance results for the algorithms mentioned above using floating-point inputs can be seen in Figure 2 2 As can be seen, the performance of the DD-BMP algorithm is comparable to that of MS 17

28 Chapter 2 Figure 2 2: Performance of the different algorithms using floating-point input 25 Summary In this chapter, we introduced LDPC codes, the SPA, MS, Gallager A & B, and DD-BMP algorithms and their implementation complexity We also presented simulation results for these decoders using the ITU G9751 Standard (32643, 30592) LDPC Code The min-sum decoding algorithm and DD-BMP algorithms were found of particular interest for their implementation complexity and thus will be the focus of Chapters 3 and 4 18

29 Chapter 3 Hard-Decision Differential-Decoding with Binary Message-Passing (DD-BMP) 31 Hard-Decision Differential-Decoding with Binary Message- Passing for the ITU G9751 Standard (32643, 30592) LDPC Code As previously stated, one of the main challenges in dealing with large codes is due to the large number of edges required for the interconnections The sheer number of variable nodes make it crucial that each piece of hardware is as simple as possible Low-complexity algorithms are ideal for a situation where such a large designed is required Using binary messages also keeps the number of wires required per edge at a minimum The drawback of most low-complexity algorithms is that they trade performance for their simplified hardware While binary messages allow them to use fewer wires and simpler hardware, the information passed between the nodes is obviously less than the sum-product decoding algorithm The DD-BMP algorithm is especially interesting because it is, at its heart, a lowcomplexity algorithm which uses aspects of more complex soft-decision algorithms

30 Chapter 3 to improve performance It is built on successive relaxation techniques, which have been known to improve performance in many other algorithms such as relaxed MS However, we have noted that DD-BMP also provides very interesting results when used as a hard-decision algorithm Our results show that hard-decision DD-BMP not only beats the results provided in the ITU G9751 Standard, but outperforms Gallager B by 05dB at high SNRs as well as performing very close to MS While it does not perform as well as hard-decision floating-point SPA, it has much lower complexity and uses binary messages, making it an attractive candidate for this large code The rest of this chapter continues with hard-decision DD-BMP, its optimization for the ITU G9751 LDPC code, and an architecture for a fully-parallel implementation 32 Optimization & Simulations Results The DD-BMP algorithm has only been used with soft-information up to this point [2] Here, we tailor the DD-BMP decoding algorithm for hard-inputs Obtaining the best results with only hard-information provided by the channel requires optimizing various parameters to achieve the best decoding performance possible Parameters which were optimized include the counter size q and the value at which these counters are initialized based on the hard-decision input from the channel Monte Carlo simulations were used to analyze the performance on the ITU G9751 code and obtain the best results For all simulations, the maximum number of iterations is set to 100, and 100 word errors are found for each simulation point 20

31 Chapter 3 Figure 3 1: Simulation results for hard-decision DD-BMP with varying counter sizes, α = 1 The bit error rate (BER) curves for different counter sizes are shown in Figure 3 1 Simulation results show that increasing the counter size improves performance until a certain point, after which performance will begin to degrade rapidly The parameter α is used to adjust the magnitude of the initial value in the memory The magnitude of the initial value for each edge memory is determined by α times the maximum value of the memory, and the sign is dependent on the sign of the received value For simulation purposes, α is chosen to have a value of 21

32 Chapter 3 Figure 3 2: Simulation results for hard-decision DD-BMP with varying α for select counter sizes 1, 1, 3, and 1 Figure 3 2 shows the BER curve for the different values of α paired with the best performing q values While the value of α does affect the performance of the algorithm, it can be seen in Figure 3 2 that its effect is not as great as changing the parameter q As such, only four values of α are selected and only the two best performing values of q are used for simulation purposes Even though this does not represent the true optimal point, the chosen parameters represent a close approximation The optimal parameter values have been determined to be q = 8 and α = 1 through simulation 22

33 Chapter 3 Figure 3 3: Overall comparison The hard-decision DD-BMP algorithm also outperforms the (255, 239) RS code [32] of the same rate by 13dB at high SNRs The BER curves can be seen in Figure 3 3 There is a loss of approximately 025dB when comparing to floating-point SPA with hard inputs using 32 iterations; but compared to other algorithms, such as Gallager B for example, hard-decision DD-BMP performs better by 05dB at high SNR values Its performance is also comparable to that of the standard floatingpoint MS algorithm using hard-decision inputs Hard DD-BMP also outperforms the results provided in the ITU G9751 standard [1] by 01dB at high SNRs 23

34 Chapter 3 33 Estimated Throughput & Algorithm Modification On average, 34 iterations are required to decode a codeword at high SNRs Assuming a 500MHz clock is available and each iteration takes 1 clock cycle, the estimated throughput can be calculated in the following manner: ( ) 1 ( ) 1 ( ) information bits iterations cycles cycles = codeword codeword iteration second information bits second (31) Example 31 Using a 500Mhz clock with 34 iterations per codeword: ( ) 1 ( ) 1 ( ) bits 34 iters 1 cycle codeword cycles 450G bits codeword iter second second However, we have noticed that since the edge memories are initialized to the maximum amount, if a received bit was in error, many cycles would be wasted bringing the value of the edge memory to a point where a correction can be made Since the decision is based on whether or not the value of the edge memory is greater or less than 0, if it was initialized to 31 in error, it would require many iterations before the value can be brought down to 1 for a correct result This occurs with all errors One way to reduce the number of these wasted iterations is to give more weight to the change applied to the edge memories in the first iteration Each variable node will be looking at the messages from 6 check nodes, and the range of the edge memories are from 31 to 31 Assume that a certain variable node has received a bit value of 1 that is in error, and that it has mistakenly initialized its edge memories to 31 If all 6 of the other check nodes send a message of 1, it will take 6 iterations before the value of the edge memory drops below 0 for a correct hard-decision of 24

35 Chapter 3 1 However, if you multiply this value by 5 just for the first iteration, the edge memory will change from 31 to 1, and a correct value can be reached in the second iteration While this is an extreme case, it does help in reducing the number of iterations required in decoding At high SNRs, we have found that on average, only 30 iterations are required with this modification, resulting in much higher throughput as can be seen below Example 32 Using a 500Mhz clock with 30 iterations per codeword: ( ) 1 ( ) 1 ( ) bits 30 iters 1 cycle codeword cycles 510G bits codeword iter second second Therefore, hard-decision DD-BMP is suitable for 100Gbps applications Soft-decision DD-BMP with the same improvements requires an average of 9 iterations for decoding to finish at high SNRs The estimated throughput becomes 17Tbps which is very favorable Example 33 Using a 500Mhz clock with 9 iterations per codeword: ( ) 1 ( ) 1 ( ) bits 9 iters 1 cycle codeword cycles 17T bits codeword iter second second In terms of implementation, it would be possible to apply DD-BMP in a fullyparallel configuration Because of its binary messages, the number of wires required is kept at an absolute minimum 25

36 Chapter 3 34 Architecture The DD-BMP algorithm has a computational complexity that is much lower than traditional soft-decision algorithms such as the SP or MS algorithms [2] However, as previously noted, any algorithm which uses multiple bits per message are not a viable solution for fully-parallel implementations due to the extremely high number of interconnections required For example, algorithms with q-bit messages would require q times the number of edges used by the DD-BMP algorithm, resulting in a much higher chip area as well as complicated routing With this algorithm, approximately edges, or wires, are required for the interconnections between the variable and check nodes compared to a potential 276 million wires for 6-bit messages We would also like to mention that a half-broadcast scheme similar to [33] can be applied to hard-decision / soft-decision DD-BMP to reduce the number of interconnections required In comparison to purely hard-decision algorithms such as the ones shown in [34], the computation complexity of DD-BMP is only slightly higher In terms of hardware, its memory requirements are approximately q d v times that of purely hard-decision algorithms However, its check nodes remain simple When coupled with these slightly more complicated variable nodes, a performance increase of 05dB can be obtained and make DD-BMP an ideal choice 341 Check Node A check node for the DD-BMP algorithm consists of a simple XOR gate Each check node has either 111 or 112 connections depending on the node Figure 3 4 illustrates the design for a check node 26

37 Chapter 3 Incoming Messages XOR Outgoing Messages Figure 3 4: Check node architecture 342 Variable Node Each variable node is composed of an adder/update unit which performs the necessary calculations for the DD-BMP algorithm One register stores the received value and one edge memory is required for each outgoing edge Figure 3 5 shows the architecture for one variable node, and Table 3 1 shows its hardware requirements Component # Required 8-Bit Registers 8 Adder/Update Unit 1 Table 3 1: Hardware requirements for a variable node 27

38 Chapter 3 Edge Memory Incoming Messages Edge Memory Edge Memory Adder / Update Unit Edge Memory Outgoing Messages Edge Memory Received Value Register Edge Memory Edge Memory Figure 3 5: Variable node architecture 35 Summary We have optimized and improved hard-decision DD-BMP and shown that it is a viable solution for decoding this code Using this algorithm, we showed that harddecision DD-BMP outperforms the requirement shown in the ITU G9751 standard by 01dB at high SNRs as well as outperforming Reed-Solomon codes of the same rate Hard-decision DD-BMP also outperforms hard-decision decoders such as Gallager B by up to 05dB It is also able to achieve performance close to that of MS while only using binary messages Its low computational complexity as well as simple 28

39 Chapter 3 implementation for very long codes makes it an attractive candidate for high speed applications 29

40 Efficient Implementation of the Min-Sum (MS) Algorithm 41 The Min-Sum Algorithm for the ITU G9751 Standard (32643, 30592) LDPC Code As we pointed out earlier, the largest difficulty encountered when implementing the ITU G9751 Standard (32643, 30592) LDPC code [1] is the sheer number of edges required in the circuit A fully-parallel implementation would require almost edges, or 276 million wires for 6-bit messages, resulting in extremely complicated, if not impossible, routing scenarios While the DD-BMP algorithm excels in a situation where only hard-decision information is available, it is still approximately 06dB worse than SPA when softdecision information is present In terms of an optimal algorithm to use for softdecision application, it is known that MS has lower complexity than SPA, and that variants of the MS algorithm such as offset MS [27] and relaxed MS [29] are able to achieve performance similar to SPA with slight modifications In this section, we

41 present an adaption of the MS algorithm based on its lower complexity and good performance for use with the ITU G9751 code As noted in the previous chapter, the DD-BMP algorithm dramatically reduces the number of required wires due to its binary messages, however, this number may still be too large for certain applications One method to reduce the number of wires is to use a partially-parallel design A fast algorithm must be chosen for partiallyparallel applications because the number of cycles required to complete one iteration doubles by just folding once (ignoring any additional overhead), reducing the throughput by approximately half As shown in the previous chapter, the improved hard-decision DD-BMP requires approximately 30 iterations while soft-decision DD- BMP requires 9 iterations The MS algorithm requires between 3 to 4 iterations at high SNRs From this fact, we can see that MS is a better candidate for use with a partially-parallel design since it will allow for better throughput We have exploited the ITU G9751 code in such a way so that it is possible to create a cell structure of nodes to allow for a partially-parallel implementation to further reduce the number of interconnects in the circuit We present such a method which would greatly simplify and reduce the number of edges required to complete the graph A smaller circuit possessing only local connections implies faster and simpler circuitry as well as smaller size This is the path we choose to explore in face of the difficulty of implementing very large codes To accomplish this task, we begin by analyzing the structure of the matrix in order to find a pattern in the way the nodes are connected which can be extracted and reused such that having the entire graph all at once is not necessary 31

42 42 ITU G9751 Standard (32643, 30592) LDPC Code The ITU G9751 Standard code is a forward error correction (FEC) code for very high bit rate systems Designed for use with 10G and 40G optical systems, it has been shown that this code performs much better than its Reed-Solomon (RS) counterpart It is a systematic binary LDPC code with a length of and information bits The degree of its variable nodes, d v, and the maximum degree of its check nodes, d c, are 7 and 112 respectively Its unique construction is described in detail [1], but the following is a short description of how the code is created Consider the matrix M to be composed of 112 rows and 293 columns indexed by the coordinates (a, b), where 0 a 111 and 0 b 292 as shown in Figure 4 1 Each of the first locations in the matrix represents an information bit, with bits (0, 292 c) where 0 c 172 set to 0 as reserved bits The jth information bit can be found at coordinate (r, 293r q) where q = j and r = q/293 The last 7 rows of the matrix are composed of the 2051 parity-check bits associated with the code Seven slopes are selected to form 7 sets of parallel lines Each location in the matrix is intersected by exactly 7 of these lines, one from each slope set Each one of these lines represents one parity-check equation, and this is how the paritycheck bits determine their value There are an additional 6 redundant bits in the parity check zone which are set to 0 and not transmitted as part of the codeword It is important to note that the codewords produced by this code also have the same format defined by the standard interleaved RS codes 32

43 43 Connectivity Matrix The description of the code structure provided in [1] actually represents M as a connectivity matrix as opposed to a generator or parity-check matrix The connectivity matrix governs how the variable nodes are connected together by the check nodes of the graph Each location of the connectivity matrix M represents a variable node, except for a few reserved locations specified in the standard These reserved locations are required to complete the matrix but are not transmitted as part of the codeword We realized that this structure is particularly interesting as the location of the subsequent node in one line can be easily calculated In our proposed implementation, an address lookup is not even necessary In randomly generated matrices, a memory lookup is required to find the address location of the other nodes and complex overhead hardware is required 431 Address Calculation In order to calculate the addresses on one line which intersects coordinates (0, c) with slope s i where 0 c 292, 0 s i 292, and i = 1, 2,, 7 for the seven lines, the following equation can be used: {(a, b) 0 a 111, b = (as i + c) mod 293} (41) This formula implies that there is exactly one node on each row connected by one line, and that each node is intersected by seven lines Figure 4 2 illustrates how a series of nodes are connected by one line, and Figure 4 3 explains how the line wraps around the M matrix 33