Ant Colony Optimization for Power Efficient Routing in Manhattan and Non-Manhattan VLSI Architectures

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1 Ant Colony Optimization for Power Efficient Routing in Manhattan and Non-Manhattan VLSI Architectures Tamanna Arora * and Melanie E. Moses + Abstract Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. In such complex designs, a primary design goal is to limit the power consumption of the chip. Power consumption depends on capacitance, which depends on the length of wires on the chip and the number of vias which connect wires on different layers of the chip. We use Ant Colony Optimization (ACO) algorithms to minimize wirelength, vias and capacitance. ACO provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision making and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes with minimum capacitance for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We implemented ACO algorithms on both manhattan and non-manhattan routing architectures. The results are compared with several state of the art academic routers. The ACO routing algorithm was able to obtain an overall improvement of 9% in terms of wire-length, 7% in terms of vias and 18% in terms of capacitance. Running times were longer than those routers, but very similar to the other router which is able to route all wires on all benchmark chips. I. INTRODUCTION Rapid advancement in VLSI technology has increased the number of transistors that can be placed on a single chip to about two billion [1]. Such complex chips require power efficient design and advanced manufacturing techniques. One of the ways to minimize power consumption of the chip is to minimize the total wire length used for routing. Given a collection of cells placed on a chip, the routing problem is to connect the terminals of these cells following a given set of design specifications [2]. Such routing problems are NPcomplete [3]; hence there is no deterministic algorithm to find the optimal routing in polynomial time. However, there are many algorithms and techniques that find good solutions in polynomial time [4]. Routing is a complex task that must accommodate large numbers of components that (Paper submitted on January15, 2009) This work is supported by NIH grant P20 RR and Microsoft Research New faculty Fellowship). Tamanna Arora is with the University of New Mexico, Albuquerque, NM 87106, USA ( tarora@cs.unm.edu). Melanie E. Moses is with the University of New Mexico, Albuquerque, NM 87106, USA ( melaniem@cs.unm.edu).. need to be connected and satisfy various performance constraints. Performance driven constraints can be controlled by minimizing total net wire length, number of vias used and net-separation [3]. Vias provide an electrical connection between two adjacent routing layers. Vias have higher capacitance than wires, and since capacitance is directly proportional to power, the use of vias should be minimized. However, vias also serve to reduce wire length, so there is an inherent tradeoff between wire-length and number of vias in minimizing total capacitance and hence, total power consumed by the chip. We formalize this tradeoff in an equation (below) for total capacitance induced on the chip [5]. Routing in VLSI chips has been studied extensively and various routing methods have been proposed [4], including many AI inspired approaches. Joobani [6, 7] suggested a knowledge based approach to routing which utilizes a stored database of routing rules. However, knowledge based approaches are inherently slow because they require an expert to continuously guide the system. Carl [8] uses simulated annealing to simultaneously place components and route interconnects. Simulated annealing achieves good optimization in terms of average interconnection length for the case of random placement of cell circuits. However this optimal performance is obtained at the expense of time as it requires exploration of vast number of states in configuration space. A novel approach is taken by Lienig [9] who uses genetic algorithms for channel and switchbox routing. That work tries to minimize length and number of vias, by running parallel genetic algorithms on a distributed network. Recently, Ant Colony based approaches have been suggested for VLSI routing. Some of these use ACO algorithms to construct Steiner trees: a minimum-weight tree connecting a designated set of vertices, called terminals, in an undirected graph or points in a space. CktSteiner [10] uses numerical model simulation to determine Steiner points. Yu Hu [11] suggests an ACO approach for constructing rectilinear Steiner trees using the heuristic that requires ants to start at each cell to be connected and meet as quickly as possible. This make ants meet soon heuristic, achieves better wire minimization than Luyet s [12] non-rectilinear Steiner tree algorithm which also uses an ACO approach. The limitation with the Steiner tree approaches is that the Steiner trees are limited to routing within a single plane, so they are unable to utilize multiple layers that are available for routing on VLSI chips. There are many other academic routers that have been proposed. Two state of the art academic routers, to which other routers are frequently compared [13, 14, 15, 16] are Labyrinth Router [17] and FastRoute [18]. These routers

2 have two goals. Labyrinth Router uses maze routing to provide accurate routing of all nets and wire length estimation, at the expense of longer running time. FastRoute uses a congestion driven Steiner tree construction to determine good Steiner tree topologies. The main goal of FastRoute is to evaluate different cell placements to determine which placements result in minimum wire-length and congestion levels. FastRoute gives less accurate wire length estimations in very fast running time, allowing it to be repeated for many potential cell placements, so that the best cell placement can be determined early in the design phase. Some benchmark nets are not routable using FastRoute. FastRoute2.0 [19] is an improvement in terms of congestion and wire-length compared to FastRoute, but it requires longer run time. The advantage of FastRoute2.0 is that it is fast enough to use for approximation and accurate enough to route most (but not all) nets, so the same router can be used for approximation and routing in most cases. This makes the approximation much more useful because approximation is much more accurate if the same algorithm is used for approximation and actual routing [19]. The more recent NTHU Router [20] decomposes all multi-pin nets into a set of two pin nets and draws a congestion map, followed by adaptive maze routing, and it is very fast. Thus, all of these routers aim to minimize run time and wire length, but different tradeoffs are accepted by different routers. One shortcoming of all of these routers is that minimizing wire length is only one component of minimizing power consumption of the chip. Our goal is a router that can minimize power consumption by simultaneously minimizing wire length and vias, but with run times comparable to the state of the art routers that only minimize wire length. The approaches taken in [8, 10, 11, 12] try to minimize wire-length, while [9] attempts to minimize the number of vias, but none of these ACO approaches combine these different aspects that are necessary for achieving power efficient design in integrated circuits with multiple layers of wires. Moreover these approaches use manhattan architecture, i.e. all wires route either horizontally or vertically. This leads to reduced routing flexibility compared to non-manhattan routing. To overcome this limitation, a new routing paradigm allowing wires to route at 45 and 135 directions, called X architecture has been proposed [21, 22]. We employ ACO to find solutions that minimize capacitance and wire length, and therefore power consumption. We build on prior work [5] in which we demonstrated that ACO are effective in manhattan grids. In this paper we extend the algorithm to non-manhattan routing, and develop techniques to route previously un-routable nets. We test our algorithm on ISPD98 IBM Standard cell benchmarks [23] and compare our results to state of the art routers. The remaining part of the paper is organized as follows: In section II, we discuss the routing problem and basic Ant Colony Optimization metaheuristic. In Section III and IV, we describe our ACO algorithm for manhattan and diagonal architecture. In Section V, we look at the results obtained, followed by some other possibilities and future work in Section VI. II. THE ROUTING PROBLEM A. Preliminaries An efficient routing algorithm is a crucial part of the automated layout design of VLSI chips. The routing algorithm assumes that the locations of the cells have already been determined. A cell is a simple logic unit stored in cell library. The routing problem is defined as locating a set of paths to route wires that connect all the nets in the net-list [24]. A net is a set of cells (also called terminal nodes) that need to be connected to each other in a predefined manner. These connections are formed using wires which are routed in a fixed routing space called a channel. A set of all the nets to be routed on a chip is called a net-list. Modern VLSI circuits route wires on multiple metal layers. Multiple layers provide tiers of horizontal and vertical routing area, stacked over each other and connected by vias (Fig. 1). Wires on the same layer cannot cross each other, unless they form a connection, whereas wires on different layers can cross each other without connecting unless an explicit connection through a via is established. Multiple layers allow a higher density of components, which shrinks the distances between cells, thus reducing wirelengths. Wires are routed on upper layers to avoid costly routes around obstacles. This is an effective method that reduces wire-lengths, minimizes power utilization [25], and allows nets to be routed that are infeasible to route in a 2D plane. Fig.1. An example of HVHV- Horizontal Vertical Horizontal Vertical layer design where horizontal layer allows laying only a horizontal wire route, whereas a vertical layer allows laying only a vertical wire route with vias providing connections between layers. Manhattan architectures offer easier designs. However, decreasing chip sizes and increasing circuit complexity, require increased routing capacity. The non-manhattan architecture using diagonal routing can increase routing capacity by adding diagonal routing layers to the manhattan architecture. These diagonal routing layers enable the router to exploit all eight possible directions on manhattan layers thereby significantly reducing wire-length, and consequently, power consumption. Our goal is to develop a routing algorithm that minimizes the power consumption of the chip. Active power (P) on a chip is determined by the equation P= acv 2 f [26], where a is an activity factor, V is voltage, f is frequency and C is capacitance. Wires and vias both contribute to capacitance and hence power. Thus we

3 minimize power by minimizing capacitance. This is complicated by the facts that vias have much higher capacitance than wires, but vias can reduce total wire-length. Thus we have to consider capacitance of vias and capacitance of wires simultaneously in order to minimize total capacitance and power. On an average the capacitance of a routing wire is approximately 0.2 ff/µm [27]. Average capacitance of via is about 0.23 pf [28, 29]. Thus, the capacitance minimized by our algorithm uses the following equation: These capacitances are approximations; in reality they will vary according to process size for any particular chip. Moreover the capacitances on a chip vary from layer to layer and the equation can be modified to reflect the capacitance of wires and vias on particular chips and layers. (1) modify the pheromone during the algorithm s execution to reflect their search experience [30, 31 and 32] so that the strength of pheromone on a route at any time is a good approximation of the goodness of that route in the overall solution. The goal of ACO algorithm is to minimize capacitance (C) in Eq. 1. This is achieved by having ants find shortest possible routes and then choose from those routes the one that minimizes capacitance. The ants follow the decision rule make ants meet soon [11], to ensure that ants will take the shortest possible route to connect to other cells, thus minimizing wire-length. In contrast to [11], when an ant meets another ant, these ants do not die, but rather a particular connection is marked as completed. Completing those paths also reduces redundant paths, thereby decreasing the number of vias. The best solution that minimizes capacitance in Eq. 1 is chosen from the routes of all ants. The following gives an overview of the basic ACO algorithm [34]. ALGORITHM 1: ACO (Ant Colony Optimization) Fig.2. An example of diagonal routing. We use IBM 98 benchmark chips [23] in which the number of nets per chip ranges from fourteen thousand to two hundred thousand nets to route. We use these benchmarks to test our ACO algorithm that minimizes wirelength, vias and capacitance (Eq. 1) on manhattan and nonmanhattan architectures. B. Ant Colony Optimization Ant Colony Optimization provides a multi-agent framework for combinatorial optimization problems. This nature inspired metaheuristic originates from the capability of ants to find shortest paths from their nest to food sources. Natural ants achieve this goal through constant coordination and indirect communication through a chemical substance called pheromone [30]. This collective problem solving ability results from a reinforcement process in which ants deposit a pheromone trail as they return from food source to their nest [33]. Since ants following the shortest path can complete their trips in less time, they will make more trips between their nests and the food source, and deposit more pheromone on shorter paths compared to longer paths [30]. The strength of pheromone on each path guides remaining ants to the food sources. In analogy to the biological example, ACO is based on the indirect communication of a colony of simple agents, called artificial ants, mediated by artificial pheromone trails. The pheromone trails in ACO serve as distributed, numerical information which the ants use to probabilistically construct solutions to the problem being solved. Ants continuously 1. Initialize pheromone. 2. While (termination condition is not met) 3. {Route 4. {For ( each ant) 5. {Empty ant s memory. 6. Place ant at some terminal node. 7. Construct a complete tour for ant. 8. {Using the pheromone and heuristic values calculate 9. the probability of yet unvisited nodes. 10. Choose the unvisited node with the highest probability. 11. } Deposit pheromone on the paths taken by the ant. The amount is proportional to the tour length. 12. } Evaporate pheromone on all the paths by some amount ρ. 13. } } III. ACO ALGORITHM FOR MANHATTAN ROUTING In this section we discuss our ACO algorithm for manhattan architecture including underlying assumptions and methods followed for the implementation. This algorithm takes a grid-less approach to routing as it allows arbitrary location of terminals, nets and vias, and arbitrary wire width [35, 36]. Also, we choose a layered HVHV (H- Horizontal, V-Vertical) model allowing two vertical and two horizontal routing layers. The algorithm can be easily extended up to 8 layers which are used in recent VLSI chips. A. Create Grid The first step of the algorithm requires creating a hanan grid from the set of cell coordinates provided in the placement file of each IBM Benchmark chip [23]. A hanan grid is obtained by constructing horizontal and vertical lines, through each coordinate point. We call these coordinate points grid points and store them in a list. This grid contains many other points created by the intersection of constructed horizontal and vertical lines. The coordinates for these intersection points are calculated and also stored in the list. After the coordinates of all the points are calculated, we

4 compute the coordinates of four neighbors of each point and store it in memory. B. Order Nets Once a grid is created, we start routing nets. Small nets are routed first in order to minimize obstruction from bigger nets. Because bigger nets require long wire lengths, they are routed on upper metal layers where capacitance is lower. Net size is determined by the perimeter it engulfs. A net perimeter is calculated as the manhattan distance between the maximum and minimum x and y co-ordinates of a net s components. The manhattan distance is defined as the distance between two points measured along grid axes at right angles. Therefore, before routing, nets are arranged in order; first by degree and then by size. Comparison of net size is only among nets with the same degree. Smaller degree nets are routed first. Fig. 3. The perimeter of above net is given as (A+B). C. Route We route one net at a time. To initialize, a small amount of pheromone is laid on all the paths of the grid. The first net is picked from the ordered list of nets. Ants are randomly placed at each cell position constituting the net. The number of ants is varied in the experiment. We experimented with numbers that are multiples of the degree of the net being routed, and found that 5 ants per degree gave the best results. To move these ants from one node to another, making sure that they follow the shortest path, we use the heuristic suggested by [11] to make ants meet soon. This heuristic acts as a decision function to move the ant from one node to another and is implemented using the following method. D. Decision Rule The probability of choosing any node is a function of the desirability of that path η i,j, and the amount of pheromone on that path τ i,j. The decision rule move ants from its current node to the next node where this probability is highest. This desirability, η, is a function that minimizes the distance between the ant s new state j and all other ants belonging to the same net and is defined as: Where α' is the terminal node from which the current ant started, i is the current node of ant α ', dir is the next node decided by this function, which is not yet already visited. α ' D i, j is the total distance between ant s next node j and all other ants when the previous given node is i. (2) Where M i, a is the manhattan distance between point i and a is the current position for other ants of the net. The probability of any path is defined as: where P i, j is the probability that an ant at node i will move to node j, τ i, j is the amount of pheromone on path (i, j), η i, j is the desirability of any path(i, j), α denotes the parameter to control the influence of τ i, j and β denotes the parameter to control the influence of η i, j. All ants start at terminal nodes. When an ant A meets another ant B, all the intermediate points covered by ant A are added to the route list of ant B, and all the intermediate points covered by ant B are added to the route list of ant A. The paths for ants A and B are marked as completed, which helps reduce the redundant steps taken by ant A to reach the starting point of ant B and vice versa. The algorithm also keeps track of any change in direction (which is a change in layer). A change in layer requires the use of vias. After an ant moves from one node to another, a local pheromone update is applied that reduces the pheromone on path (i, j) by a small evaporation constant (ρ) [34]. This allows an increase in exploration of paths and hence avoids stagnation behavior. After all the ants complete their routes, a global pheromone update is implemented [34]. Global pheromone update reinforces the pheromone of the best ant of the whole iteration. This is implemented by following method. E. Choose Best In our algorithm, we minimize capacitance by choosing the best ant whose route has the lowest capacitance according to Eq. 1. Eq. 1 is beneficial in cases where one ant promises shorter length, and another uses fewer numbers of vias. Although there is always a trade off between the routed wire length and vias used for that route, the reduction in wire length may outweigh the cost of vias [37]. Eq. 1 finds the solution with minimum capacitance. F. Ordering Problem During routing, the nets that are routed later have comparatively fewer options to route compared to nets which are routed earlier. The nets which are routed earlier have all routing channels available to them and can route using fewer vias. The paths used for routing of these nets can not be used for routing any other net, unless shifted to some other routing channel or layer. This is known as the ordering problem as it requires an order to be followed to route different nets. Our algorithm routes one net at a time by the order established above; however it allows rip-up and reroute of previously routed nets to find a better routing solution [17, 18, and 19]. During routing ants are not informed about which paths are used by other routes and which are available for routing. (3) (4)

5 This allows ants to come up with the best possible routing solution for any net. There are cases when ants find a solution that uses a path which is already being used for routing of some other net. The algorithm takes care of such cases in the following manner. First the algorithm calculates the length of the already routed net which overlaps with yet to be routed net. If the only common point is a non-terminal node, the algorithm compares the length for which both the net routes run without changing direction. This is an important aspect for deciding which net is shifted, as change in direction requires use of vias. Thus to minimize the use of vias, the routes which change direction are shifted to alternate routes or layers. Shifting the nets that run without changing direction might lead to unnecessary addition of vias and hence is discouraged by the algorithm. In the second case, the commonality between two nets is not just a point but a common path. Again the number of direction changes is measured. It might be the case that shifting a net route to another layer leads to increased wire-length if an obstacle exists in this new layer. Thus, the third case needs to check that saving vias is not leading to wire-length increase. A final decision of which net is shifted is made after calculating the TCI parameter for both the nets in different layers. G. Un-routable nets In some benchmark circuits the best route chosen for a particular net might be un-routable. This case arises when the chosen path is already used for routing by some other net. The algorithm tries to route such a net by shifting either of the nets to an alternate path. But in few cases none of the layers in the vicinity of the route is available for routing. In such cases the algorithm uses a different strategy to route the nets. The first approach to deal with un-routable nets is to use the second best route found using Eq. 1. If the second best routing solution is unable to route the net, the third, fourth, and fifth best solution is tried. If none of these solutions are able to route the net, we abandon the strategy of routing shortest nets first (described in section B) and randomize the order of routing. Using our original algorithm, results show that out of 18 benchmark circuits, 9 circuits were left with un-routable nets. On an average the number of un-routable nets was very low (0.017%). The alternate strategy used for routing was able to route all un-routable nets. Algorithm 2 provides a brief outline of our ACOrouting approach. ALGORITHM 2: ACO-ROUTE 1. Create Hanan Grid 2. { Order the x and y co-ordinates. 3. Store all possible pairs of x and y coordinates. 4. } Find neighbors. 5. Order nets according to degree and then size. 6. Initialize a small amount of pheromone on the whole grid. 7. While (termination condition is not met) 8. { Route 9. { For ( each ant) 10. {Empty ant s memory. 11. Place ants at some terminal node. 12. Construct a complete tour for ant. 13. {Calculate the probability of unvisited nodes using the heuristic to minimize the distance of ant from other ants and pheromone values. If the ant meets another ant, for both the ants add the routes traveled by one to the route list of the other. 14. } Deposit pheromone on the path taken by ant. 15. } Find the best ant of the iteration using the TCI parameter. 16. Update the global pheromone value. 17. } Find the shortest ant routed solution, and check if any part of this solution interferes With any other solution. 18. } Decide to shift either of the based on TCI parameter. IV. ACO ALGORITHM FOR NON-MANHATTAN ROUTING The ACO algorithm for diagonal routing follows a similar procedure as in manhattan routing with the following variations. A. Create Grid The ACO implementation for non-manhattan (diagonal) routing assumes a symmetrical routing grid formed by the overlap of 4 layers (horizontal, vertical, 45 and 135 diagonal layer). These layers allow routing from node A to its eight possible neighbors (Fig. 3).The diagonal route can achieve a 29% reduction in length. B. Order Nets To gain maximum advantage of diagonal routes, the ordering of nets is tuned such that the nets that span more on either X or Y axis are routed first. To measure their axis span, we calculate the minimum and maximum X and Y coordinate of net s components. Axis span could be measured as: Where Fig. 4. Eight possible neighbors of node A. (5) and (6) (7) Thus the nets are first ordered by degree and than by axis span. C. Route The routing procedure uses the same heuristics as in the case of manhattan routing. The best route is chosen using the same capacitance equation as in manhattan routing. V. EXPERIMENTS AND ANALYSIS This section presents the computational results obtained on various IBM standard ISPD98 benchmarks [23]. Our implementation of ACO routing (ACO-Route and ACO- NMRoute) has been coded in C++ and tested on a 2.2 MHz AMD Athlon Turion 64. The following tables compile results for manhattan and diagonal routing.

6 Fast Route 2.0 (FR) W-Len Time (sec) Labyrinth Router (LR) W-Len Time (sec) NTHU Router (NR) W-Len The manhattan routing uses two horizontal and two vertical routing layers whereas the diagonal routing uses horizontal, 45 diagonal, vertical and 135 diagonal layers in that order. The value of ACO parameters were varied to find the best fit. The parameters are chosen in a manner such that the algorithm is able to maintain a good balance between the focus of the search and exploration of new paths [34]. The ACO parameters for both the algorithms are set as α= 0.6, β= 0.3, ρ= 0.2 and number of ants equals net-degree times five. We compare ACO-Route and ACO-NMRoute with two state-of-the-art academic routers: FastRoute2.0 [19] and Labyrinth Router [17]. We also compare the results with the most recently published academic router NTHU[20] and WRoute[38] which is the only router that gives comparable information about the number of vias in addition to wire length. Table 1 provides a comparison between wire-length and time required by FastRoute 2.0, Labyrinth Router, NTHU Router (as reported in their publications), ACO- Route (manhattan routing) and ACO-NMRoute (diagonal routing). Table 2 reports the number of vias and wirelength by ACO-Route, ACO-NMRoute and WRoute. We also compare the reduction in capacitance obtained by ACO-Route over WRoute and ACO-NMRoute over TABLE 1 WIRE LENGTH COMPARISON Time (sec) ACO-Route (The comparisons have been made for the benchmark results available in [17, 19, 20]. TABLE 2 VIAS AND CAPACITANCE COMPARISON ACO-NM Route W-Len Time W-Len Tim e The comparisons have been made for the benchmark results available in [38]. Improvement (%) ACO ACO- NM Route FR2.0 LR NR ACO Ibm Ibm Ibm Ibm Ibm Ibm Ibm Ibm Ibm Ibm Avg Bench markname Benchmark W-Route ACO-Route ACO-NM-Route % Improvement Name Vias W-Len Vias W-Len Vias W-Len ACO-Route w.r.t W-Route ACO-NMRoute w.r.t ACO-Route Vias Capacitance Vias Capacitance Ibm Ibm Ibm Ibm Ibm Ibm Ibm Ibm Average ACO-Route. The capacitance in Table 2 is calculated using Eq.1. WRoute reports the total routing time for placement and routing but does not report the time required just for routing. As described above, the load capacitance directly influences the power consumption of the chip, and the number of wires and vias directly influence the loadcapacitance. These two parameters--number of wires and vias--can not be minimized together, as the reduction in one parameter raises the number of the other. Thus our algorithm focuses on minimizing the capacitance and computes the wire-length and number of vias that best meets that goal. As seen from the results, although the ant algorithm focuses on minimizing capacitance, it also achieves reduction in wire-length and vias. The ACO- Route algorithm is able to achieve an average improvement of 8.7% in terms of wire-length compared to three routers [17, 19 and 20] and 7.1% in terms of vias compared to WRoute. ACO-NMRoute is able to achieve an additional improvement over ACO-Route of 4.71% in terms of wire-length and 4.6% in terms of vias. From Table 2 we see that the ACO-Route algorithm was able to reduce the capacitance compared to W-Route by 7% whereas ACO-NMRoute reduced it further by 18%. The

7 run time of ACO-Route is much longer than for FastRoute and NMroute, but it is very similar to Labyrinth which is the only other router able to route all nets. More important than the actual running time is the scaling of run time with the number of nets. The scaling exponents for FastRoute2.0, NHTU, Labyrinth, ACO and ACO-NM are 0.83, 1, 1.32, 1.28 and 1.36 respectively. These exponents are significant in terms of predicting the behavior of these algorithms for complex chips with higher net count. The exponents for ACO-Route and ACO-NMRoute are similar to Labyrinth. FastRoute is able to achieve sub linear scaling because it routes nets simultaneously, but it is an approximation that cannot route all nets on the benchmark chips. The ACO routes every net. Moreover, ACO is an agent based algorithm in which every agent practices an independent sequential decision process aimed at constructing a feasible solution using only information local to the current decision step. Thus, our ACO algorithm can be easily parallelized which can substantially reduce run-time and still give the same results. None of the other routers use independent agents that can be easily parallelized. Fig.5. The graph shows the total wire-length computed by the algorithm for the set of ten benchmarks when the average number of ants per node is increased from one to ten. Finally, the run time can be reduced by reducing the number of ants. As shown in Fig. 5, reducing the number of ants below 5 results in longer wire lengths, but it may be desirable to use fewer ants to approximate the wire length and capacitance during placement, and then use more ants to provide a better solution for final routing one the placement is determined. The ACO performs best with an intermediate number of ants. A 16% reduction in total wire-length is achieved when the average number of ants per node per net is increased from one to five (Fig. 5). Additional ants slightly decrease the performance of the algorithm. We hypothesize that the performance with additional ants degrades as additional ants reinforce a solution that is a local minimum and thus can not find the more optimal solution found with fewer ants. It is possible that a different set of ACO parameters would lead to better performance by more ants. VI. CONCLUSION AND FUTURE WORK In this paper we use an Ant Colony Optimization (ACO) algorithm to route complex VLSI chips over both grid-less manhattan architectures and non-manhattan architectures that use diagonal routing. Our algorithm minimizes capacitance, and therefore active power on the chip. Capacitance of a net is the sum of the capacitance of wires and vias, where vias have higher capacitance than wires, but vias can reduce the wire length needed to complete a net. The ACO uses ant agents to find the shortest routes for each net using the heuristic make ants meet soon [11]. From that list of short routes, we choose the solution that minimizes capacitance. The experiments show that this approach performs well in the NP hard problem of routing VLSI chips. The ACO algorithm was tested on ISPD 98 benchmarks [23] with number of nets ranging from fourteen thousand to two hundred thousand. On an average, our ACO achieves wire-length reduction of 8.7% compared to three state of art routers [17, 19 and 20] and 7.1% in terms of vias compared to WRoute [38]. We applied the same ACO to diagonal architectures and obtained a further improvement over manhattan ACO algorithm of 4.7% reduction in wire length and 4.6% reduction in vias. Overall, the diagonal architecture had a 18% reduction of capacitance compared to our manhattan results. We were able to compare running time to the three routers that minimize wire length but not vias. Absolute running time and the scaling of running time with the number of nets is very similar to Labyrinth Router, which is the only router to route all nets in the benchmark chips. FastRoute and NHTU run much faster, particularly with larger net lists but they are unable to route every net. ACO-ROUTE is the only router which minimizes vias and wire length, making it feasible to incorporate power efficiency very early in the design process. Our approach was to minimize power by minimizing capacitance. This approach could be extended to incorporate other routing constraints, either by changing the heuristics of the ants, or by changing the procedure for choosing the best ant to route each net. For example, the mutual capacitance induced when two wires pass near each other could be included in this algorithm. This mutual capacitance could lead to coupling effects or crosstalk [39], which could lead to delay problems and interfere with the functionality of the chip. If we calculate the capacitance induced between wires, and build this as ACO heuristic, ants can find alternate paths that minimize this induced capacitance. More complex selection of the best routes could also seek to minimize delay or resistance induced by wires and vias. We routed shorter nets first, which forces longer nets to use higher metal layers. This serves to reduce overall capacitance because wires on higher layers have lower capacitance, but our calculations do not consider this advantage. For any particular design, more detailed equations that consider capacitance on each layer could be used to better predict and minimize capacitance. The approach also holds promise for routing on other non-manhattan grids that are even less constrained than the X architecture, which are expected to be incorporated in new VLSI designs. Because ants route

8 on graphs rather than grids, ACO algorithms are easier to adapt to non-manhattan grids than other algorithms. Moreover ACO algorithm is a distributed agent based algorithm which has the potential to be parallelized and substantially decrease the run-time. The parallel ACO could be achieved by using multi-core chips and assigning a particular number of ants to each processor. ACO algorithms are successful at the multiple constraint optimization required to minimize power on VLSI chips. They are also applicable to flexible routing architectures. Better or faster results might be obtained by tuning the ACO parameters so that the algorithm works well with more or fewer ants, and the approach could achieve faster run times by taking advantage of multi-core processors to parallelize the independent searches of each ant. Thus, ACO is a promising solution for routing future more complex and flexible VLSI designs. ACKNOWLEDGMENT The authors wish to thank Prof. Alan L. Davis and Mike A. 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