A Multi-Layer Router Utilizing Over-Cell Areas

Transcription

1 A Multi-Layer Router Utilizing Over-Cell Areas Evagelos Katsadas and Edwin h e n Department of Electrical Engineering University of Rochester Rochester, New York ABSTRACT A new methodology is presented for the solution of the multilayer routing problem that has the potential to outperform channel based multi-layer routing algorithms by expanding the routing regions to include areas over the cells. It is assumed that four routing layers are available. Routing is completed in two steps; a selected group of nets is routed in the between-cell areas using existing channel routing algorithms and the first two routing layers. Then the remaining nets are routed over the entire layout area, between-cell and over-cell areas, using a new twodimensional router and the next two routing layers. The router used for over-cell routing recognizes arbitrarily sized obstacles, for example, due to power and ground routing or sensitive circuits in the underlying cells. The proposed router was tested on a number of macro-cell layout examples. Advantages of dedicating two routing layers for over-cell routing is illustrated. Results show a significant reduction in total layout area, wire length and number of vias when compared to results obtained using two-layer or multi-layer channel routing methods. 1. INTRODUCTION The demand for smaller and faster designs and the reality that conventional two-layer routing technologies may have reached their limits have forced designers to consider alternative ways to obtain further improvements in routing. The use of additional routing layers appears to be a promising way to achieve this goal. While a number of algorithms have been suggested, attention has been directed to the use of the additional routing layers in channel areas and the development of modified channel routing algorithms. Chen and Liu [I] presented a three-layer channel router based on the net merging method used by Yoshimura and Kuh [2]. Cong, et QZ [3], allowed the use of three or four layers and resolved vertical constraints by track permutations, local rerouting and the insertion of empty tracks. Bruell and Sun [4] developed a modified greedy channel router for three layers based on the algorithm of Rivest and Fiduccia [5]. Braun, et a1 [6], implemented a multi-layer channel router, Chameleon, based on a strategy of decomposing the multi-layer routing problem into two or three layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. Greenberg and Sangiovanni-Vincentelli [7], presented Mulch, an extension of Chameleon that routes channels with any number of layers and automatically chooses a good assignment of wiring strategies to the different layers. Other multilayer routing algorithms have been proposed by Enbody and Du [8], and Hambrusch [9]. These reported multi-layer channel routing schemes claim reductions in channel width that approach 50% of the number of tracks required by a conventional two-layer channel routing algorithm. However, the reduction in the number of tracks caused by the additional routing layers does not necessarily result to a similar reduction in the channel area due to the design rules imposed by the fabrication process of these layers. As more metal layers are added, the linewidth of the wires and the size of the vias increase; thus, even if a channel can be routed with fewer tracks, the actual routing area may not be significantly smaller from the two layer solution. Channel based multi-layer algorithms also tend to generate wires running parallel, one on top of the other, over relatively long distances, creating capacitive coupling that can cause severe cross-talk problems. The proposed procedure is based upon a different solution to the multi-layer routing problem, one that can exploit more efficiently the freedom offered by the additional routing layers. For descriptive convenience, it is assumed that: (1) metal1 and metal2 layers are used for the interconnections within the macro-cells; and (2) two additional metal layers, metal3 and metal4, are available that can be used to run wire paths over macro-cells without violating the design rules. The proposed router completes the routing of the layout using a two level design process. At the first level, level A, a subset of the interconnections is routed in channel areas using the first two metal layers; global and detailed routing can be performed using existing channel routing packages. Then, at level B, the remaining interconnections are routed over the entire layout area, between-cell and over-cell areas, using metal3 and metal4 layers. An efficient algorithm for the two dimensional routing problem at level B is presented that avoids over-cell regions representing obstacles due to user selection or design rules. For example, if a limited use of metal3 and metal4 is allowed inside the macro-cells, these wire segments become obstacles for the over-cell routing. Obstacles may also represent user specified areas that need to be excluded from over-cell routing to avoid capacitive coupling with sensitive circuits in the underlying macro-cells. The paper is organized as follows. Section 2 discusses net partitioning and level A routing. The differences between level A and level B routing and the proposed algorithm for level B routing are described in Section 3. Section 4 presents experimental results obtained applying the proposed router to three layout examples. Finally, Section 5 contains concluding remarks. 2. NET PARTITIONING AND LEVEL A ROUTING The set of network interconnections is initially partitioned into two sets, A and B. Nets in set A will be routed in channel ar th ACMllEEE Design Automation Conference@ 1990 IEEE X/90/0006/0704 $1.OO

2 eas between macro-cells and nets in set B will be routed over the entire layout area, the combined between-cell and overcell areas. Control of propagation delays may dictate this net partitioning process such that local interconnections are included in set A, while long distance interconnections are routed in level B using wider lines to yield shorter propagation delays. Alternatively, either set A or set B may be used exclusively for control nets, critical nets, or power and ground nets. If total layout area is a priority. layout area allocated for channels can be controlled through the net partitioning process. The two set of nets are considered as independent routing problems each govemed by its own design rules. This is achieved by assigning entire nets to each set and by not allowing multiterminal nets to be assigned in part to both sets. Thus, all twoterminal partitions of a multi-terminal net are routed using the same set of routing layers, and only finial connections to net terminals are allowed to pass through intervening routing layers. There are two advantages to this net partitioning scheme. First, no extra routing space is required for the net terminal connections since the design of net terminals can usually accommodate the design rules governing the size of vias for the four routing layers used. Second, no obstacles are created in level A routing caused by connections from level B nets to metall and metal2, since these connections only occur at net terminal locations, that is, in areas that would be obstacles in level A routing anyway. Furthermore, reflection problems in high speed designs caused by discontinuities existing in vias connecting wire segments routed in routing layers with different linewidths are minimized. Level A routing can be performed using existing channel routing algorithms. After completion of level A routing, the final dimensions of the layout and the location of the net terminals are known. Subsequent level B routing is performed on this fixed topology. 3. LEVEL B ROUTING Nets in set B are routed over the entire layout area with the exception of areas that represent obstacles. Since net terminal positions and the final layout dimensions are known at the beginning of level B routing, there are significant differences between level A and level B routing that need to be accommodated by the level B routing algorithm. The solution space for the level A routing problem is defined by the relative placement of the macro-cells and the resulting channels. The router divides the routing problem into several channel routing problems which are then solved separately. Channel dimensions are flexible and net terminal locations are not defined rigidly in space since they can move following any channel expansion. Each channel problem can be considered as an one-dimension routing problem. In contrast, net terminal locations and the boundaries of the layout define the solution space in the level B routing problem. Obstacles in the layout may exist due to specific features of the underlying circuits or power and ground routing. However, the size and shape of these obstacles do not correspond to those that exist in level A routing. Partitioning the solution space may be restrictive, that is,' the algorithm should consider the entire solution space. Level B is a two-dimension routing problem and a number of algorithms have been proposed to solve its many variations [ However, the specific characteristics of the level B routing problem, the size of the solution space, the existence of routing obstacles and the locations of net terminals, suggests that a more efficient two-dimensional router can be constructed. The proposed router adopts a different representation for the solution space of the routing problem that results in faster completion of the interconnections on the average when compared to maze type algorithms. The proposed two-dimensional routing algorithm uses a grid model representation of the layout. The routing surface is characterized by an array of rectangular cells defied by horizontal and vertical routing tracks that can have different spacing. The algorithm is based on a breadth fnst search through an unweighted, undirected graph that represents the routing solution space. The vertices in this graph represent routing tracks and the edges represent track intersections that can be used for routing. The quality of the resulting routing is measured in terms of total number of net directional changes and total wire length. The level B routing algorithm processes the nets serially. The algorithm starts with the definition of routing tracks and the assignment of a pair of horizontal and vertical tracks to each net terminal. Net ordering is accomplished using a longest distance criterion. The option of a user specified ordering criterion, such as net criticality, can be exercised. A path searching procedure, done for each two-terminal connection using a modified breadth first search, finds a set of possible paths with the minimum number of comers. The choice of the best path is based on path length and the likelihood of blocking nets not yet routed. A description of the method used for path searching and path selection, and the time and space requirements for level B routing follows Path Searching The solution space for level B routing is represented by an undirected bipartite graph G = (V,E) called Track Intersection Graph. The set of vertices V consists of two mutually exclusive subsets V, and V,, where each vi E VI represents a vertical routing track and each vj E V, represents an horizontal routing track. The edges ei = (vi,vj) E E, correspond to the intersection of a vertical with an horizontal track that can be used for routing. An example of level B routing and its Track Intersection Graph is shown in Figure 1. hl h2 h3 Figure 1: Instance of level B routing and its Track Intersection Graph representation. 705

3 Path searching is accomplished using a modified breadth first search (MBFS) algorithm. A path consists of a sequence of alternating horizontal and vertical track segments. For each twoterminal connection. all possible paths with the minimum number of comers are found, with the exception of a special class of paths that is described later. The solution space for each MBFS is defined by the terminal locations of the interconnection to be realized. The path searching procedure for net B is illustrated in Figure 1. In this example, nets A and C are already connected, and 0, represents a possible obstacle for level B routing. Each net terminal is represented by one edge from the Track Intersection Graph; for net B one terminal is represented by the edge (h2,v2) and the other terminal by the edge (h4,vs). Two modified breadth first searches are performed starting from one of the two terminals. The solution space for each MBFS is defied by the locations of the two net terminals within a rectangular region, such as I n, and a source vertex and two target vertices are identified. The first MBFS starts from vertex v2 and has as targets the vertices v6 and h4; the second MBFS starts from vertex h2 and has the same targets as the fist one. Two Path Selection Trees are created during the search procedure, as shown in Figue 2. These are used later for the selection of the best path for the interconnection. During the MBFS for possible paths, each vertex is examined exactly once with the exception of the target vertices. This results in the exclusion of paths requiring more than one comer on the same track, a restriction that improves the quality of the routing and significantly increases the speed of the algorithm. For this example, three possible paths can be identified one path (v2,h4.v6) from the MBFS that started from vertex v2, and two paths (h2.v3.h4,v6) and (hz,vs,h,,v6) from the MBFS that started from vertex h,. The first path is selected because it requires only one comer while the other two paths required two comers. No further path selection is necessary for this example since only one path with a minimum number of comers is detected Path Selection The Path Selection Trees created during the path searching procedure are used to select the best path for the completion of the interconnection when multiple paths with the same number of directional changes are identified. This is done by proper edge weighting of the Path Selection Trees where the wire length and the likelihood of blocking nets yet to be routed are considered. Edges associated with grid points close to unrouted net terminals and used grid points are weighted high, while edges associated with grid points located in empty routing regions are weighted low. A backtracking technique, that is a depth first search with bounding functions, is used to select the best path. The path selected over the set of paths with minimum number of comers k is the one that minimizes the cost function : k C = wl*wl+ Bw2pdrg; + wz2*dupi + W ~~*~C$) ;=I where, wl = wire length of the path under consideration, drgj = measure of the proximity of comer j to routed dup, = grid points, measure of the proximity of comer j to unrouted net terminals, acfi = the area congestion factor of comer j. The fust term of the objective function controls the total wire length while the second term controls the distribution of wiring segments to avoid blocking unrouted nets. Additional terms can be included in the cost function for nets with special constraints, for example, to prevent parallel routing of sensitive nets. The weights wl,wzl, w22 and ~ 2may 3 be used to customize the selection process to the specific needs of the level B routing problem. Experiments showed, that for routing problems with sparse net distributions it is sufficient to balance the effect of the two terms of the objective function by setting wl=l and w2l=w22=w23 =ID. For routing problems with dense net distributions the second term of the objective function should be weighted more to reduce the possibility of blocking unrouted nets. Figure 2: Path Selection Trees for net B. & Edge weighting in the proposed level B routing algorithm is limited to the Path Selection Trees which are considerably smaller than the entire Track Intersection Graph. This allows the use of more complicated edge weighting schemes that minimize the effect of the order dependency of the algorithm due to the serial processing of the nets. 33. Multi-terminal nets. Multi-terminal nets are routed using a suboptimal algorithm that approximates a rectilinear Steiner tree. The set of terminals belonging to a given multi-terminal net define a vertex set P. Based on the grid model representation of the level B solution space, the vertex set N is defmed as the set of all grid points in the layout that can be used for routing. The rectilinear Steiner tree (RST) for a given set P is a minimum length tree that interconnects all the vertices of set P possibly using one or more vertices from the set N-P, the Steiner points, and a rectilinear distance metric. The problem of constructing the minimum cost RST, known to be NP-complete [ 141. has been studied extensively and many heuristic algorithms have been proposed [ 14-18]. A new heuristic algorithm that approximates the rectilinear Steiner tree was developed based on Prim's algorithm for constructing a minimum spanning tree [19]. Prim's algorithm enlarges a component of the output tree by adding one vertex at a time. The vertex selected is the one with the minimum distance from all vertices of the output component. The new algorithm enlarges the output component by adding a vertex with minimum distance not only from vertices from set P that already belong to the output component but also from Steiner points that belong to the output component. The vertex selected is then connected to the 706

4 set P vertex or Steiner point to which it is closest. The algorithm continues until all vertices belonging to set P have been processed Time and Space Complexity of Level B Routing Algorithm The storage requirement of the proposed algorithm is O(hv) where h and v are the numbers of the horizontal and vertical tracks, essentially the storage requirements of the Track Intersection Graph. Information associated with the Track Intersection Graph is stored in a two-dimensional array which is updated after the completion of each two-terminal connection. This involves an operation of O(t), where t = max(h,v). The time complexity of the level B routing algorithm is O(nhv), where n is the total number of two-terminal connections required Example 4-Layer 4-Layer Over- Channel Router Cell Router Area Area ami33 2,261,480 1,874,880 Xerox ,148 21,101,200 ex3 3,548,475 3,061,635 Percent Reduction in Layout Area EXPERIMENTAL RESULTS The program that implements the described multi-layer routing methodology was developed in the C programming language and runs under SunOS Three examples of macro-cell layouts were tested with the new multi-layer router. The fmt two examples, Xerox and ami33, were presented recently as benchmarks for comparisons [20]; the third example, ex3, is from an industrial macro-cell chip. Table 1 has information for each example tested. The same net partitioning scheme was used in all three examples; critical nets and timing nets were routed in level A, while all other nets were routed in level B. The number of nets routed in level A and the average number of pins per net were 4 (44.25) for ami33, 21 (9.19) for Xerox, and 56 (3.23) for ex3. The performance of the proposed multi-layer routing methodology compared to the performance of a two-layer channel routing methodology is given in Table 2. The comparisons were based on overall layout area, total wire length and total number of vias. For the three examples tested, a significant reduction in all three metrics is observed. The level B routing of example ami33 is shown in Figure CONCLUDING REMARKS Current integrated circuit technology allows the use of several layers of interconnect to provide more degrees of freedom for solving area and performance optimizing routing problems. To take advantage of this, a new methodology for multi-layer routing has been described that relaxes the constraint of routing interconnections only in channel areas. The proposed router was used for three test examples, yielding significant reductions in overall layout area, wire length and number of vias. During level B routing, the router accommodates routing obstacles and also allows the user to influence path selection through appropriate edge weighting of the Path Selection Trees. The user has control of the overall layout area through the partitioning of the interconnections into sets A and B. If layout area optimization is the priority, channel areas can be eliminated and the entire set of interconnections can be routed in level B. assuming that the solution space for level B routing guarantees 100% routing completion. Table 1: Information about the three layout examples. Example ami33 Xerox ex3 Layout Area Wire Length Vias Table 2: Percent reductions for the proposed multi-layer router over a two-layer channel router. A comparison of the proposed multi-layer router with multilayer channel routers was attempted. Since no complete multilayer channel routing package was available, the comparison is based only on overall layout area and the optimistic assumption that a multi-layer channel routing algorithm would reduce the channel area requirements by 50% over the channel area requirements of a two-layer channel routing algorithm. As shown in Table 3, a further reduction in the overall layout area is REFERENCES Y. K. Chen and M. L. Liu. 'Three-layer channel routing," IEEE Transactions on Computer-Aided Design, vol. CAD- 3, no. 2, pp , T. Yoshimura and E. S. Kuh, "Efficient algorithms for channel routing," IEEE Transactions on Computer-Aided Design, vol. CAD-1, no. 1, pp , J. Cong, D. F. Wong, and C. L. Liu, "A new approach to three- or four-layer channel routing," IEEE Transactions on Computer-Aided Design, vol. CAD-7, no. 10, pp ,1988. P. Bruell and P. Sun, "A'greedy' three layer channel router," in Proc. IEEE Intern. Conf. on Computer-Aided Design, 1985, pp R. L. Rivest and C. M. Fiduccia, "A 'greedy' channel router," in hoc. 19th Design Automation Conference, 1982, pp D. Braun et al., "Techniques for multilayer routing," IEEE Transactions on Computer-Aided Design, vol. CAD-7, no. 6, pp , R. I. Greenberg and A. L. Sangiovanni-Vincentelli, "Mulch: A multi-layer router using one, two, and tree layer partitions," in Proc. IEEE Intern. Conf. on Computer-Aided Design, 1988, pp

5 R. J. Enbody and H. C. Du, "Near optimal n-layer channel routing." in Proc. 23rd Design Automation Conference, 1986, pp S. E. Hambrusch, "Channel routing algorithms for overlap models," IEEE Transactions on Computer-Aided Design, vol. CAD-4. pp C. Y. Lee, "An algorithm.for path connections and its applications," IRE Transactions on Electronic Computers, vol. EC-10, pp , K. J. Supowit. "A minimum-impact routing algorithm," in Proc. 19th Design Automation Conference, 1982, pp C. Hsu, "A new two-dimensional routing algorithm," in Proc. 19th Design Automation Conference. 1982, pp M. Marek-Sadowska, 'Two-dimensional router for double layer layout," in Proc. 22nd Design Automation Conference, 1985, pp M. R. Garey and D. S. Johnson, 'The rectilinear Steiner tree problem is NP-complete," SIAM Journal of Applied Mathematics. vol. 32, no. 3, pp F. K. Hwang, "An O(nlogn) algorithm for rectilinear minimal spanning trees," Journal of the Association for Computing Machinery, vol. 26, no. 2, pp , J. H. Lee, N. K. Bose, and F. K. Hwang, "Use of Steiner's problem in suboptimal routing in rectilinear metric," IEEE Transactions on Circuits and Systems, vol. CAS-23, no. 7, pp ,1976. K. Lee and C. Sechen, "A new global router for row-based layout," in Proc. IEEE Intern. Con$ on Computer-Aided Design, 1988, pp J. Ho. G. Vijayan, and C. K. Wong, "New algorithms for the rectilinear Steiner tree problem." IEEE Transactions OR Computer-Aided Design, vol. 9, no. 2, pp , R. C. Prim, "Shortest connection networks and some generalizations," Bell System Technical Journal, vol. 36, no. 6, p ~ , B. Reas, "Benchmarks for cell-based layouts," in Roc. 24th ACMIIEEE Design Automation Conference, 1987, pp Figure 3: Level B routing of layout example ami