ASIP LDPC DESIGN FOR AD AND AC

Transcription

1 ASIP LDPC DESIGN FOR AD AND AC MENG LI CSI DEPARTMENT 3/NOV/2014 TELECOM BRETAGNE BREST FRANCE

2 OUTLINES 1. Introduction of IMEC and CSI department 2. ASIP design flow 3. Template of the high speed LDPC decoding processor 4. Instantiation for the ad and ac standard 2

3 BRIEF INTRODUCTION OF IMEC in 2013: 2086 people 383 residents 289 PhD students 71 nationalities 3

4 Strong expertise and track record in high-speed and low-power architectures and circuits for multi-gbps communication DIGITAL BB LOW POWER ARCHITECTURES SYSTEM AND ALGORITHMS DEMONSTRATION AND TEST RF AND ANALOG IC AND MODULE DESIGN IMEC 2013 CONFIDENTIAL

5 Energy efficiency 5 to 10X higher energy efficiency DIGITAL CASE: IMEC BASEBAND CORES PROGRAMMABILITY WITH HIGH ENERGY EFFICIENCY ASICs BLO X BLO X BLO X High duty cycle and/or complex function ~ specialized data (co)-processor BOADRE S Low duty cycle and/or simple function ~ power efficient DSP DSP Flexibility

6 FULL MODELING IN TARGET COMMERCIAL TOOL FLOW Typical users: ASIC/SoC design teams

7 HIGH SPEED LDPC ASIP: TEMPLATE Configurable memory Compiled firmware, for given set of modes, compaction can be done through synthesis tool MIN SIGN 8 parallel slices Cross-slice operations OUTPUT Syndrome detection

8 INSTRUCTION SET AND MAPPING 8

9 HIGH SPEED LDPC ASIP: TEMPLATE Configurable memory Available instances MIN SIGN ad Horizontal layered decoding ac Check node processing using normalized/offset min-sum Flexible quantization scheme Multiple slices implementation OUTPUT Offset permutation (only rotation during read of data) Early stop & Max iteration configuration Target Toolsuite based Syndrome detection Assembly programmable

10 Number of slices Quantization LLR Max iteration number Early stop Check node algorithm INSTANTIATION AND IMPLEMENTATION ad 8 slices flexibility Template/ processor High throughput instances ac 8 slices ac 4 slices CLAUDE DESSET, MENG LI - CSI 10

11 BER/PER AD REQUIREMENTS Decoder input rate Modes MCS 0-24 Block size Up to Gbps (MCS 22-24) 672bits Coding rates 1/2,5/8,3/4,13/16 Quantization Min 4 bits R3/4 QPSK (MCS8) BER Performance with maximum iteration number 5 SC Multi indoor channel BER floating offset min-sum BER Q5 offset min-sum BER Q4 offset min-sum PER floating offset min-sum PER Q5 offset min-sum PER Q4 offset min-sum E b /N 0 (db) 11

12 Feature Algorithm ad Quantization AD RESULTS FACT SHEET Value Normalized/Offset Min-sum, layered decoding APP: 7/6-bits & UPD: 5/4-bits Parallelization Check-node FUs: 42 Bit-node FUs: 42x8 (half layer in parallel) Functional support Technology 1/2,5/8,3/4,13/16 (all ad modes) 28HPM physical synthesis Clock [MHz] 440 Quantization Average #cycles/layer 4 Throughput [Gbps for 1 iter for 1 core] Latency [ns] Area [sqmm] Power [mw] Energy Efficiency [pj/bit/it] 2 cores + 3 iterations HW/SW early stop 4 bits 25.8 (R=13/16) 0.269(4bits) [core-level] QPSK R13/16 [core-level]; [core-level]; [wrapper-level] Parallel layer decoding Early stop Back-rotation 12

13 SOA COMPARISON Berkeley[1] EPFL[2] Imec s[3] Imec s Decoding algo. Two phases layered layered layered LLR quan. 5 bits 5 bits 5 bits 4 bits Parallelism 42*16 42*2 42*8 42*8 Pipeline scheme frame level X half layer half layer Early stop YES NO NO YES Number of cores Single Single Single Multi-cores ASIC vs. ASIP ASIC ASIC ASIC ASIP Tech node[nm] G 28HPM Working freq. [MHz] Throughput [Gbps] Area [mm^2] Energy eff.[pj/bit/iter] 6.18 N/A [1] 2011, LDPC decoder architecture for high-data rate personal-area networks, Weiner, M., ect. from UC Berkeley [2] 2013, A parallelized layered QC-LDPC decoder for IEEE ad, Alexios B., ect. from EPFL [3] 2013, AN AREA AND ENERGY EFFICIENT HALF-ROW-PARALLELED LAYER LDPC DECODER FOR THE AD STANDARD, Meng L. from IMEC 13

14 802.11AC REQUIREMENTS Decoder input rate Up to 6.93 Gbps (8 spatial streams, 160 MHz, 256- QAM) Modes MCS 0-9 Block size Coding rates Quantization 648, 1296 or 1944bits 4 coding rates Min 5 bits 14

15 MAPPING TO AC 8 slices solution 4 slices solution Average #cycles/iter: 74 Average #cycles/iter: slices solution is more efficient than for low coding rates 15

16 Feature Algorithm Quantization Parallelization Technology ac Clock [MHz] AC RESULTS FACT SHEET Value Normalized/Offset Min-sum, layered decoding APP: 7-bits & UPD: 5-bits Check-node FUs: Z=81/54/27 Bit-node FUs: Zx8 or Zx4 orzx2 28HPM physical synthesis 500MHz Instances 8 slices 4 slices Average #cycles/layer 7 10 Area [sqmm] Throughput [Gbps for1iter (R5/6)~13.1(R1/2) 23.7(R5/6)~8.4(R1/2) Latency [ns] Energy Efficiency [pj/bit/it] Functional support all ac modes (1/2,2/3,3/4,5/6) Functional completeness Parallel layer decoding Back-rotation Demapper (R5/6,Z81) 16

17 SOA COMPARISON Zurich[1] Waseda[2] Rice[3] Imec s Decoding algo. layered layered Multi-layered layered LLR quan. 5 bits 5 bits 5 bits 5 bits Parallelism Z Z*2 Z*4 Z*4 Pipeline scheme NO NO 1/12 layer 1/6 layer Early stop NO NO NO NO ASIC vs. ASIP ASIC ASIC ASIC ASIP Tech node[nm] HPM Size Z & rate Z=81&R=5/6 Z=48&R=? Z=81 & R=5/6 Z=81 & R=5/6 Working freq. [MHz] Throughput [Mbps] it 2370@10it Area [mm^2] 1.77* 3.36* Energy eff.[pj/bit/iter] 15.8* 10.9* N/A 7.1 * tape out results [1] 2010, A 15.8 pj/bit/iter quasi-cyclic LDPC decoder for IEEE n in 90 nm CMOS, Roth. C., etc. from ETH Zurich [2] 2011, A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS, Xiao P., etc. from UC Waseda [3] 2011, Multi-layer parallel decoding algorithm and VLSI architecture for quasi-cyclic LDPC codes, Yang S., ect. from UC Rice 17

18 802.11AC REQUIREMENTS 8 slices solution 4 slices solution Multi-layer decoding 4 slices solution 18

19 Heading for ultra-high throughput FEC

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