512Kx8 Monolithic SRAM, SMD
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- Archibald Wood
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1 512Kx Monolithic SRAM, SMD FEATURES Access Times of,, 2,, 35, 45, 55 Data Retention Function (LPA version) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 512Kx Commercial, Industrial and Military Temperature Rang es 32 lead JEDEC Approved Evolutionary Pinout Ceramic Sidebrazed 6 mil DIP (Package 9) Ceramic Sidebrazed 4 mil DIP (Package 326) Ceramic 32 pin Flatpack (Package 344) Ceramic Thin Flatpack (Package 321) Ceramic SOJ (Package ) 36 lead JEDEC Approved Revolutionary Pinout Ceramic Flatpack (Package 316) Ceramic SOJ (Package 327) Ceramic LCC (Package 52) Single +5V (±1%) Supply Operation The EDI512CA is a 4 megabit Monolithic CMOS Stat ic RAM. The 32 pin DIP pinout adheres to the JEDEC evo lu tion ary stan dard for the four megabit device. All 32 pin packages are pin for pin up grades for the single chip enable 12K x, the EDI12CS. Pi 1 and 3 be come the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC stan dard for the four megabit device. The cen ter pin power and ground pi help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx. A Low Power version with Data Retention (EDI512LPA) is also available for battery backed applicatio. Military product is available compliant to Appendix A of MIL-PRF *This product is subject to change without notice. FIGURE 1 PIN CONFIGURATION PIN DESCRIPTION I/O-7 Data Inputs/Outputs A-1 Address Inputs Write Enables Chip Selects 36 PIN TOP VIEW 32 PIN TOP VIEW OE# Output Enable VCC Power (+5V ±1%) VSS Ground A A1 A2 A3 A4 I/O I/O1 Vcc Vss I/O2 I/O3 A5 A6 A7 A A pin Revolutionary NC A1 A A16 A OE# I/O7 I/O6 Vss Vcc I/O5 I/O4 A A A12 A11 A1 NC A1 A16 A A12 A7 A6 A5 A4 A3 A2 A1 A I/O I/O1 I/O2 Vss pin Evolutionary Vcc A A A A A9 A11 OE# A1 I/O7 I/O6 I/O5 I/O4 I/O3 NC Not Connected BLOCK DIAGRAM Memory Array Address Address I/O A-1 Buffer Decoder Circuits I/O-7 OE# Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 1 Microsemi Corporation (62)
2 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Voltage on any pin relative to Vss -.5 to 7. V Operating Temperature TA (Ambient) Commercial TA +7 C Industrial -4 TA +5 C Military -55 TA +1 C Storage Temperature, Plastic -65 TA + C Power Dissipation 1.5 W Output Current 2 ma Junction Temperature, TJ 5 C NOTE: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func tion al operation of the device at these or any other conditio greater than those in di cat ed in the operational sectio of this spec i fi ca tion is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. TRUTH TABLE OE# Mode Output Power X H X Standby High Z Icc2, Icc3 H L H Output Deselect High Z Icc1 L L H Read Data Out Icc1 X L L Write Data In Icc1 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage VCC V Supply Voltage VSS V Input High Voltage VIH 2.2 VCC +.3 V Input Low Voltage VIL V CAPACITANCE (TA = + C) Parameter Symbol Condition Max Unit Address Lines CI VIN = Vcc or Vss, f = 1.MHz 12 pf Data Lines CO VOUT = Vcc or Vss, f = 1.MHz pf These parameters are sampled, not 1% tested. DC CHARACTERISTICS (VCC = 5V, TA = -55 C to +1 C) Parameter Symbol Conditio Min Max Units Input Leakage Current ILI VIN = V to VCC -1 1 A Output Leakage Current ILO VI/O = V to VCC -1 1 A Operating Power Supply Current ICC1, = VIL, II/O = ma, Min Cycle () ma (2-55) 2 ma Standby (TTL) Power Supply Current ICC2 VIH, VIN VIL, VIN VIH 6 ma Full Standby Power Supply Current ICC3 VCC -.2V CA ma VIN Vcc -.2V or VIN.2V LPA 2 ma Output Low Voltage VOL IOL = 6.mA.4 V Output High Voltage VOH IOH = -4.mA 2.4 V NOTE: DC test conditio: VIL =.3V, VIH = Vcc -.3V AC TEST CONDITIONS Figure 1 Figure 2 Vcc 4Ω Q Q 5Ω 3pF 5Ω Vcc 4Ω 5pF Input Pulse Levels VSS to 3.V Input Rise and Fall Times 5 Input and Output Timing Levels 1.5V Output Load Figure 1 NOTE: For tehqz, tghqz and twlqz, CL = 5pF Figure 2) Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 2 Microsemi Corporation (62)
3 AC CHARACTERISTICS READ CYCLE (VCC = 5.V, Vss = V, -55 C TA +1 C) Symbol Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Read Cycle Time tavav trc Address Access Time tavqv taa Chip Enable Access Time telqv tacs Chip Enable to Output in Low Z (1) telqx tclz Chip Disable to Output in High Z (1) tehqz tchz Output Hold from Address Change tavqx toh Output Enable to Output Valid tglqv toe Output Enable to Output in Low Z (1) tglqx tolz Output Disable to Output in High Z(1) tghqz tohz This parameter is guaranteed by design but not tested. AC CHARACTERISTICS WRITE CYCLE (VCC = 5.V, VSS = V, -55 C TA +1 C) Symbol Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Write Cycle Time tavav twc Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time telwh teleh tavwl tavel tavwh taveh twlwh twleh twhax tehax twhdx tehdx tcw tcw tas tas taw taw twp twp twr twr tdh tdh Write to Output in High Z (1) twlqz twhz Data to Write Time tdvwh tdveh tdw tdw Output Active from End of Write (1) twhqx twlz 1. This parameter is guaranteed by design but not tested Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 3 Microsemi Corporation (62)
4 FIGURE 2 TIMING WAVEFORM READ CYCLE ADDRESS t AVAV tavav t AVQV ADDRESS ADDRESS 1 ADDRESS 2 t ELQV t EHQZ tavqv tavqx t ELQX DATA I/O DATA 1 READ CYCLE 1 ( HIGH; OE#, LOW) DATA 2 OE# DATA OUT t GLQV t GLQX t GHQZ READ CYCLE 2 ( HIGH) FIGURE 3 WRITE CYCLE CONTROLLED ADDRESS t AVAV t AVWH t ELWH t WHAX t AVWL t WLWH t DVWH t WHDX DATA IN DATA VALID t WLQZ t WHQX DATA OUT HIGH Z WRITE CYCLE 1, CONTROLLED FIGURE 4 WRITE CYCLE CONTROLLED ADDRESS t AVAV t AVEH t ELEH t EHAX t AVEL t WLEH t DVEH t EHDX DATA IN DATA VALID DATA OUT HIGH Z WRITE CYCLE 2, CONTROLLED Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 4 Microsemi Corporation (62)
5 DATA RETENTION CHARACTERISTICS (EDI512LPA ONLY) (-55 C TA +1 C) Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym Conditio Min Typ Max Units VCC ICCDR tcdr TR VCC = 2.V VCC -.2V VIN VCC -.2V or VIN.2V 2 tavav 2 V ma FIGURE 5 DATA RETENTION CONTROLLED DATA RETENTION MODE VCC 4.5V 4.5V VCC tcdr tr = VCC -.2V DATA RETENTION, CONTROLLED Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 5 Microsemi Corporation (62)
6 1 1 EDI512CA PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP, SMD XXMXA Pin 1 Indicator x.1 = NOM PACKAGE 326: 32 LEAD SIDEBRAZED CERAMIC DIP Pin 1 Indicator x.1 = NOM PACKAGE : 32 LEAD CERAMIC SOJ, SMD XXMUA Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 6 Microsemi Corporation (62)
7 PACKAGE 316: 36 PIN CERAMIC FLATPACK, SMD XXMTA.92 ± REF Pin PACKAGE 321: 32 PIN THINPACK FLATPACK, SMD XXMYA.3 MAX ± MAX. PACKAGE 344: 32 PIN CERAMIC FLATPACK, SMD XXM9A ±.4.24 REF..112 MAX..3 MAX..16 ±..5 ±.2..3 ±.1 Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 7 Microsemi Corporation (62)
8 PACKAGE 327: 36 LEAD CERAMIC SOJ, SMD XXMMA PACKAGE 52: 36 LEAD CERAMIC LCC BSC Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. Microsemi Corporation (62)
9 ORDERING INFORMATION EDI 512 CA X X X MICROSEMI CORPORATION: SRAM: ORGANIZATION, 512Kx: TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (): PACKAGE E: C = 32 lead Sidebrazed DIP, 6 mil (Package 9) K = 36 lead Ceramic LCC (Package 52) N = 32 lead Ceramic SOJ (Package ) T = 32 lead Sidebrazed DIP, 4 mil (Package 326) B32 = 32 pin Ceramic Thinpack Flatpack (Package 321) F32 = 32 pin Ceramic Flatpack (Package 344) F36 = 36 pin Ceramic Flatpack (Package 316) N36 = 36 lead Ceramic SOJ (Package 327) DEVICE GRADE: B = MIL-STD-3 Compliant M = Military Screened -55 C TA +1 C I = Industrial -4 C TA +5 C C = Commercial C TA +7 C Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 9 Microsemi Corporation (62)
10 Document Title 512Kx Monolithic SRAM, SMD Revision History Rev # History Release Date Status Rev Changes (Pg. 1-1).1 Change document layout from White Electronic Desig to Microsemi.2 Add document Revision History page February 211 Final Microsemi Corporation reserves the right to change products or specifi catio without notice. February Microsemi Corporation. All rights reserved. 1 Microsemi Corporation (62)
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FEATURES 32K x 8 organization Single +5V power supply +125V programming voltage Fast access time: 45/55/70/90/100/120/150 ns Totally static operation Completely TTL compatible 256K-BIT [32K x 8] CMOS EPROM
A29040D Series. 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory. Document Title. Revision History. AMIC Technology, Corp.
Preliminary 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory Document Title 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory Revision History Rev. No. History Issue Date Remark
Rev. No. History Issue Date Remark
Preliminary 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory Document Title 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory Revision History Rev. No. History Issue Date Remark
HIGH SPEED 128K (8K X 16 BIT) IDT70825S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM )
HIGH SPEED 18K (8K X 16 BIT) SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) Features High-speed access Commercial: ///4 (max.) Low-power operation IDT78S Active: 77mW (typ.) Standby: mw (typ.) IDT78L
OPTIONS. Low Power Data Retention Mode. PIN ASSIGNMENT (Top View) I/O 16 I/O 17 I/O 18 I/O 19 I/O17 I/O18 I/O19. Vss I/O20 I/O21 I/O22 I/O23
512K x 32 SRAM SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS SMD 5962-94611 & 5962-95624 (Military Pinout) MIL-STD-883 FEATURES Operation with single 5V supply Vastly improved Icc Specs High speed:
AS6C TINL 16M Bits LOW POWER CMOS SRAM
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CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240
UT8MR8M8 64Megabit Non-Volatile MRAM Datasheet July 2018
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128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM FEATURES Fast access time : 55ns ow power consumption: Operating current : 20/18mA (TYP.) Standby current : 2µA (TYP.) Single 2.7V ~ 5.5V power
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256Kx72 Synchronous Pipeline SRAM FEATURES Fast clock speed: 100, 133, 150, 166 and 200** MHz Fast access time: 5.0, 4.0, 3.8, 3.5, 3.1ns +3.3V power supply (VCC) +2.5V output buffer supply (VCCQ) Single-cycle
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CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
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M29F040B. 4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory
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HIGH-SPEED 4K x 8 FourPort TM STATIC RAM
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A24C02. AiT Semiconductor Inc. ORDERING INFORMATION
DESCRIPTION provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 256 words of 8 bits each. The device is optimized for use in many industrial and
A24C08. AiT Semiconductor Inc. ORDERING INFORMATION
DESCRIPTION The provides 8192 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 1024 words of 8 bits each. The device is optimized for use in many industrial
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32Kx8 AutoStore nvsram
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FEATURES. Single Power Supply Operation - Low voltage range: 2.70 V V
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74AC11139 DUAL 2-LINE DECODER/DEMULTIPLEXER
Designed Specifically for High-Speed Memory Decoders and Data Tramission Systems Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception Center-Pin V CC and GND Configuratio Minimize
ISSI Preliminary Information January 2006
2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2006 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low-voltage Operation Vcc = 1.8V to 5.5V Low
Industrial Temperature Range: -40 o C to +85 o C Lead-free available KEY TIMING PARAMETERS. Max. CAS Access Time (tcac) ns
1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE APRIL 2005 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden
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HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM IDT713/ IDT714/ Features High-speed access : ///1 (max.) Industrial: /1 (max.) Commercial: ////1 (max.) Low-power operation IDT713/IDT714 Active: mw (typ.) Standby:
Am27C Megabit (256 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM V CC V SS V PP
FINAL Am27C020 2 Megabit (256 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time Speed options as fast as 55 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved
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