512K x 8 4Mb Asynchronous SRAM
|
|
|
- Roland Reynolds
- 5 years ago
- Views:
Transcription
1 SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp 512K x 8 4Mb Asynchronous SRAM GS74108ATP/J/X 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 8, 10, 12 ns CMOS low power operation: 120/95/85 ma at minimum cycle time Single 3.3 V power supply All inputs and outputs are TTL-compatible Fully static operation Industrial Temperature Option: 40 to 85 C Package line up J: 400 mil, 36-pin SOJ package GJ: RoHS-compliant 400 mil, 36-pin SOJ package TP: 400 mil, 44-pin TSOP-II package GP: RoHS-compliant 400 mil, 44-pin TSOP-II package X: 6 mm x 10 mm FPBGA package GX: RoHS-compliant 6 mm x 10 mm FPBGA package RoHS-compliant packages available Description The GS74108A is a high speed CMOS Static RAM organized as 524,288 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS74108A operates on a single 3.3 V power supply and all inputs and outputs are TTL-compatible. The GS74108A is available in 400 mil SOJ, 400 mil TSOP-II, and 6 mm x 10 mm FPBGA packages. A4 1 A3 2 A2 3 A1 4 A0 5 6 DQ1 7 DQ2 8 V DD 9 V SS 10 DQ3 11 DQ4 12 WE 13 A17 14 A16 15 A15 16 A14 17 A13 18 SOJ 512K x 8-Pin Configuration 36-pin A5 A6 A7 A8 OE DQ8 DQ7 400 mil SOJ 28 V SS 27 V DD DQ6 DQ5 A9 A10 A11 A12 20 A18 19 FP-BGA 512K x 8 Bump Configuration (Package X) Pin Descriptions Symbol A0 A18 DQ1 DQ8 WE OE V DD VSS Description Address input Data input/output Chip enable input Write enable input Output enable input +3.3 V power supply Ground No connect A OE A2 A6 A7 B DQ1 A1 A5 DQ8 C DQ2 A0 A4 DQ7 D VSS A18 A3 VDD E VDD A17 A9 VSS F DQ3 A13 A10 DQ6 G DQ4 A14 A11 WE DQ5 H A16 A15 A12 A8 6 mm x 10 mm *All GSI Technology packages are at least 5/6 RoHS compliant. Packages listed with the additional G designator are 6/6 RoHS compliant. Rev: /2006 1/ , Giga Semiconductor, Inc.
2 TSOP-II 512K x 8-Pin Configuration A4 A3 A2 A1 A0 DQ1 DQ2 V DD V SS DQ3 DQ4 WE A17 A16 A15 A14 A pin 400 mil TSOP II A5 40 A6 39 A7 38 A8 37 OE 36 DQ8 35 DQ7 34 V SS 33 V DD 32 DQ6 31 DQ5 30 A9 29 A10 28 A11 27 A12 26 A Block Diagram A0 Address Input Buffer Row Decoder Memory Array A18 Column Decoder WE OE Control I/O Buffer DQ1 DQ8 Rev: /2006 2/ , Giga Semiconductor, Inc.
3 Truth Table OE WE DQ1 to DQ8 V DD Current H X X Not Selected ISB1, ISB2 L L H Read L X L Write IDD Note: X: H or L L H H High Z Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD 0.5 to +4.6 V Input Voltage VIN 0.5 to V DD +0.5 ( 4.6 V max.) V Output Voltage VOUT 0.5 to V DD +0.5 ( 4.6 V max.) V Allowable power dissipation PD 0.7 W Storage temperature TSTG 55 to 150 o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -8/-10/-12 V DD V Input High Voltage VIH 2.0 V DD +0.3 V Input Low Voltage VIL V Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range TAc 0 70 o C TAI o C Notes: 1. Input overshoot voltage should be less than V DD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than 2 V and not exceed 20 ns. Rev: /2006 3/ , Giga Semiconductor, Inc.
4 Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN V IN = 0 V 5 pf Output Capacitance COUT V OUT = 0 V 7 pf Notes: 1. Tested at TA = 25 C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to V DD 1 ua 1 ua Output Leakage Current ILO Output High Z VOUT = 0 to V DD 1 ua 1 ua Output High Voltage VOH I OH = 4 ma 2.4 Output Low Voltage VOL I LO = +4 ma 0.4 V Power Supply Currents Parameter Symbol Test Conditions 0 to 70 C 40 to 85 C 8 ns 10 ns 12 ns 8 ns 10 ns 12 ns Operating Supply Current I DD VIL All other inputs V IH or VIL Min. cycle time I OUT = 0 ma 120 ma 95 ma 85 ma 130 ma 105 ma 95 ma Standby Current I SB1 V IH All other inputs V IH or VIL Min. cycle time 30 ma 25 ma 22 ma 40 ma 35 ma 32 ma Standby Current I SB2 V DD - 0.2V All other inputs V DD - 0.2V or 0.2V 10 ma 20 ma Rev: /2006 4/ , Giga Semiconductor, Inc.
5 AC Test Conditions Parameter Conditions DQ Output Load 1 Input high level VIH = 2.4 V Input low level VIL = 0.4 V 50Ω 30pF 1 Input rise time tr = 1 V/ns VT = 1.4 V Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 589Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tlz, thz, tolz and tohz 5pF 1 434Ω AC Characteristics Read Cycle Parameter Symbol Min Max Min Max Min Max Unit Read cycle time trc ns Address access time t AA ns Chip enable access time () t AC ns Output enable to output valid (OE) t OE ns Output hold from address change toh ns Chip enable to output in low Z () t LZ * ns Output enable to output in low Z (OE) t * ns OLZ Chip disable to output in High Z () t * ns HZ Output disable to output in High Z (OE) t OHZ * ns * These parameters are sampled and are not 100% tested. Rev: /2006 5/ , Giga Semiconductor, Inc.
6 Read Cycle 1: = OE = V IL, WE = V IH trc Address taa toh Data Out Previous Data Data valid Read Cycle 2: WE = V IH Address trc taa tlz tac thz OE Data Out High impedance tolz toe DATA VALID tohz Rev: /2006 6/ , Giga Semiconductor, Inc.
7 Write Cycle Parameter Symbol Min Max Min Max Min Max Unit Write cycle time twc ns Address valid to end of write taw ns Chip enable to end of write tcw ns Data set up time tdw ns Data hold time tdh ns Write pulse width twp ns Address set up time tas ns Write recovery time (WE) twr ns Write recovery time () twr ns Output Low Z from end of write twlz * ns Write to output in High Z twhz * ns * These parameters are sampled and are not 100% tested. Address Write Cycle 1: WE control twc taw twr OE tcw tas twp WE tdw tdh Data In DATA VALID twhz twlz Data Out HIGH IMPEDAE Rev: /2006 7/ , Giga Semiconductor, Inc.
8 Write Cycle 2: control twc Address OE taw twr1 tas tcw WE twp tdw tdh Data In DATA VALID Data Out HIGH IMPEDAE 36-Pin SOJ, 400 mil D c L Dimension in inch Dimension in mm Symbol min nom max min nom max A A E HE GE A B e A B c D A A1 A2 y B B1 Detail A Q E e HE GE L y Q 0 o 10 o 0 o 10 o Notes: 1. Dimension D& E do not include interlead flash. 2. Dimension B1 does not include dambar protrusion/intrusion. Rev: /2006 8/ , Giga Semiconductor, Inc.
9 44-Pin, 400 mil TSOP-II 44 D 23 c Symbol Dimension in inch Dimension in mm min nom max min nom max A E HE A A A B A A1 A e B y L1 Detail A L Q c D E e HE L L y Q 0 o 5 o 0 o 5 o Notes: 1. Dimension D& E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm Rev: /2006 9/ , Giga Semiconductor, Inc.
10 6 mm x 10 mm FPBGA D Symbol Unit: mm A 1.10±0.10 A1 0.20~0.30 fb f0.30~0.40 E c 0.36(TYP) Pin A1 Index D 10.0±0.05 D E 6.0±0.05 E Top View e 0.75(TYP) A c aaa 0.10 A1 Side View aaa Pin A1 Index A B C D E F G H fb Solder Ball e E1 D1 e Bottom View Rev: / / , Giga Semiconductor, Inc.
11 Ordering Information Part Number 1 Package 2 Access Time Temp. Range Status 3 GS74108ATP mil TSOP-II 8 ns Commercial MP GS74108ATP mil TSOP-II 10 ns Commercial MP GS74108ATP mil TSOP-II 12 ns Commercial MP GS74108ATP-8I 400 mil TSOP-II 8 ns Industrial MP GS74108ATP-10I 400 mil TSOP-II 10 ns Industrial MP GS74108ATP-12I 400 mil TSOP-II 12 ns Industrial MP GS74108AGP-8 RoHS-compliant 400 mil TSOP-II 8 ns Commercial PQ GS74108AGP-10 RoHS-compliant 400 mil TSOP-II 10 ns Commercial PQ GS74108AGP-12 RoHS-compliant 400 mil TSOP-II 12 ns Commercial PQ GS74108AGP-8I RoHS-compliant 400 mil TSOP-II 8 ns Industrial PQ GS74108AGP-10I RoHS-compliant 400 mil TSOP-II 10 ns Industrial PQ GS74108AGP-12I RoHS-compliant 400 mil TSOP-II 12 ns Industrial PQ GS74108AJ mil SOJ 8 ns Commercial MP GS74108AJ mil SOJ 10 ns Commercial MP GS74108AJ mil SOJ 12 ns Commercial MP GS74108AJ-8I 400 mil SOJ 8 ns Industrial MP GS74108AJ-10I 400 mil SOJ 10 ns Industrial MP GS74108AJ-12I 400 mil SOJ 12 ns Industrial MP GS74108AGJ-8 RoHS-compliant 400 mil SOJ 8 ns Commercial PQ GS74108AGJ-10 RoHS-compliant 400 mil SOJ 10 ns Commercial PQ GS74108AGJ-12 RoHS-compliant 400 mil SOJ 12 ns Commercial PQ GS74108AGJ-8I RoHS-compliant 400 mil SOJ 8 ns Industrial PQ GS74108AGJ-10I RoHS-compliant 400 mil SOJ 10 ns Industrial PQ GS74108AGJ-12I RoHS-compliant 400 mil SOJ 12 ns Industrial PQ GS74108AX-8 6 mm x 10 mm FPBGA 8 ns Commercial MP GS74108AX-10 6 mm x 10 mm FPBGA 10 ns Commercial MP GS74108AX-12 6 mm x 10 mm FPBGA 12 ns Commercial MP GS74108AX-8I 6 mm x 10 mm FPBGA 8 ns Industrial MP GS74108AX-10I 6 mm x 10 mm FPBGA 10 ns Industrial MP Rev: / / , Giga Semiconductor, Inc.
12 Ordering Information Part Number 1 Package 2 Access Time Temp. Range Status 3 GS74108AX-12I 6 mm x 10 mm FPBGA 12 ns Industrial MP GS74108AGX-8 RoHS-compliant 6 mm x 10 mm FPBGA 8 ns Commercial PQ GS74108AGX-10 RoHS-compliant 6 mm x 10 mm FPBGA 10 ns Commercial PQ GS74108AGX-12 RoHS-compliant 6 mm x 10 mm FPBGA 12 ns Commercial PQ GS74108AGX-8I RoHS-compliant 6 mm x 10 mm FPBGA 8 ns Industrial PQ GS74108AGX-10I RoHS-compliant 6 mm x 10 mm FPBGA 10 ns Industrial PQ GS74108AGX-12I RoHS-compliant 6 mm x 10 mm FPBGA 12 ns Industrial PQ Notes: 1. Customers requiring delivery in Tape and Reel should add the character T to the end of the part number. For example: GS74108ATP-8T. 2. All GSI Technology packages are at least 5/6 RoHS compliant. Packages listed with the additional G designator are 6/6 RoHS compliant. 3. MP = Mass Production. PQ = Pre-Qualification. Rev: / / , Giga Semiconductor, Inc.
13 4M Asynchronous Datasheet Revision History Rev. Code: Old; New Types of Changes Format or Content Page #/Revisions/Reason 74108A_r1 Format/Content Creation of new datasheet 74108A_r1; 74108A_r1_ A_r1_01; 74108A_r1_ A_r1_02; 74108A_r1_03 Content Content Content Added 6 ns speed bin Updated all power numbers Updated Recommended Operating Conditions table on page 4 Added 7 ns bin to entire document Added X package Removed 6 ns speed bin from entire document Corrected X package pinout 74108A_r1_03; 74108A_r1_04 Content Removed 7 ns speed bin from entire document 74108A_r1_04; 74108A_r1_05 Content Updated format Added Pb-free information for TSOP-II package 74108A_r1_05; 74108A_r1_06 Content Added Pb-free information for FP-BGA package 74108A_r1_06; 74108A_r1_07 Content Added RoHS-compliant information for SOJ Changed Pb-free references to RoHS-compliant Added status to ordering information table Rev: / / , Giga Semiconductor, Inc.
64K x 16 1Mb Asynchronous SRAM
TSOP, FP-BGA Commercial Temp Industrial Temp 64K x 16 1Mb Asynchronous SRAM GS71116AGP/U 7, 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 7, 8, 10, 12 ns CMOS low power operation:
256K x 16 4Mb Asynchronous SRAM
FP-BGA Commercial Temp Industrial Temp 256K x 16 4Mb Asynchronous SRAM GS74117AX 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 8, 10, 12 ns CMOS low power operation: 130/105/95
AS6C K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issue Add package 48-ball 8mm 10mm TFBGA Revised ORDERING INFORMATION in page 11 Jan.09.2012 July.12.2013 0 FEATURES Fast access
LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.
128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 14, 2008 Preliminary 1.0 Final version release September 21, 2010
CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout
CMOS Static RAM 1 Meg (K x -Bit) Revolutionary Pinout IDT714 Features K x advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/gnd) for reduced noise Equal access and cycle times
IDT71V124SA/HSA. 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout IDT71VSA/HSA Features K x advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/gnd) for reduced noise Equal access
LP62S16256G-I Series. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Revision History. Rev. No. History Issue Date Remark
Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM ocument Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue June 2, 2006 Preliminary PRELIMINARY
CMOS SRAM. K6T4008C1B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.
Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle
4Mb Async. FAST SRAM Specification
S6R4008V1M, S6R4016V1M, S6R4008C1M S6R4016C1M 4Mb Async. FAST SRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO NETSOL PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING
IDT71016S/NS. CMOS Static RAM 1 Meg (64K x 16-Bit)
CMOS Static RAM 1 Meg (4K x 1-Bit) IDT711S/NS Features 4K x 1 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial and Industrial: //2 One Chip Select plus one Output Enable pin
4Mb Async. FAST SRAM A-die Specification
S6R4008V1A, S6R4016V1A, S6R4008C1A, S6R4016C1A, S6R4008W1A S6R4016W1A 4Mb Async. FAST SRAM A-die Specification NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.
3.3V CMOS Static RAM for Automotive Applications 4 Meg (256K x 16-Bit)
.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) IDTVYS IDTVYL Features 25K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle
AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb
REVISION HISTORY Revision Description Issue Date 1.0 Initial issue Feb 2007 2.0 Add-in industrial temperature option for 28-pin 600 July 2017 mil PDIP. Standby current(isb1) reduced to be 20uA for I-grade
Rev. No. History Issue Date Remark
128K X 8 BIT LOW VOLTAGE CMOS SRAM ocument Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue February 19, 2002 Preliminary 0.1 Add 32L Pb-Free
16Mb(1M x 16 bit) Low Power SRAM
16Mb(1M x 16 bit) Low Power SRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING
8K X 8 BIT LOW POWER CMOS SRAM
February 2007 FEATURES Access time :55ns Low power consumption: Operation current : 15mA (TYP.), VCC = 3.0V Standby current : 1µ A (TYP.), VCC = 3.0V Wide range power supply : 2.7 ~ 5.5V Fully Compatible
MOS INTEGRATED CIRCUIT
DATA SHEET 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT MOS INTEGRATED CIRCUIT µpd43256b Description The µpd43256b is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery
ACT S512K32 High Speed 16 Megabit SRAM Multichip Module
ACT S512K32 High Speed 16 Megabit SRAM Multichip Module Features 4 Low Power CMOS 512K x 8 SRAMs in one MCM Factory configured as 512K x 32; User configurable as 1M x 16 or 2M x 8 Input and Output TTL
MOS INTEGRATED CIRCUIT
DATA SHEET 4M-BIT CMOS STATIC RAM 256K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION MOS INTEGRATED CIRCUIT µpd444012a-x Description The µpd444012a-x is a high speed, low power, 4,194,304 bits (262,144
Rev. No. History Issue Date Remark
Preliminary 512K X 8 OTP CMOS EPROM Document Title 512K X 8 OTP CMOS EPROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 17, 1998 Preliminary 1.0 Change CE from VIL to VIH
AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 V CC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current Icc1 on
MOS INTEGRATED CIRCUIT
DATA SHEET 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT MOS INTEGRATED CIRCUIT μpd43256b Description The μpd43256b is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery
HM628128BI Series. 131,072-word 8-bit High speed CMOS Static RAM
131,072-word 8-bit High speed CMOS Static RAM ADE-203-363A(Z) Rev. 1.0 Apr. 28, 1995 The Hitachi HM628128BI is a CMOS static RAM organized 131,072-word 8-bit. It realizes higher density, higher performance
128Kx8 CMOS MONOLITHIC EEPROM SMD
128Kx8 CMOS MONOLITHIC EEPROM SMD 5962-96796 WME128K8-XXX FEATURES Read Access Times of 125, 140, 150, 200, 250, 300ns JEDEC Approved Packages 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) 32 lead,
Low Power Pseudo SRAM
Revision History Rev. No. History Issue Date 1.0 1. New Release. 2. Product Process change from 90nm to 65nm 3. The device build in Power Saving mode as below : 3-1. Deep Power Down (DPD) 3-2. Partial
LY61L102416A 1024K X 16 BIT HIGH SPEED CMOS SRAM
REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issued Jan.09. 2012 Rev. 1.1 Add 48 pin BGA package type. Mar.12. 2012 Rev. 1.2 1. VCC - 0.2V revised as 0.2 for TEST July.19. 2012 CONDITION
CAT22C Bit Nonvolatile CMOS Static RAM
256-Bit Nonvolatile CMOS Static RAM FEATURES Single 5V Supply Fast RAM Access Times: 200ns 300ns Infinite E 2 PROM to RAM Recall CMOS and TTL Compatible I/O Power Up/Down Protection 100,000 Program/Erase
AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations
Features Fast Read Access Time - 150 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor
512Kx8 Monolithic SRAM, SMD
512Kx Monolithic SRAM, SMD 5962-956 FEATURES Access Times of,, 2,, 35, 45, 55 Data Retention Function (LPA version) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 512Kx Commercial,
LY62L205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM
Y62205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Sep.06.2012 Rev. 1.1 Add 25 & 40 spec for ISB1 & IDR on page 4 &
Product Specification
General Information 512MB 64Mx72 ECC SDRAM PC100/PC133 DIMM Description: The VL 374S6553 is a 64M x 72 Synchronous Dynamic RAM high density memory module. This memory module consists of eighteen CMOS 32Mx8
M Rev: /10
www.centon.com MEMORY SPECIFICATIONS 16,777,216 words x 64Bit Synchronous Dynamic RAM Memory Module (Unbuffered DIMM) Centon's 128MB Memory Module is 16,777,216 words by 64Bit Synchronous Dynamic RAM Memory
White Electronic Designs
White Electronic Desig 512Kx8 STATIC RAM CMOS, MODULE FEATURES 512Kx8 bit CMOS Static Random Access Memory Access Times 2 through 1 Data Retention Function (EDI8F8512LP) TTL Compatible Inputs and Outputs
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 13, 2001 Preliminary 0.1
A23W8308. Document Title 262,144 X 8 BIT CMOS MASK ROM. Revision History. Rev. No. History Issue Date Remark
Preliminary 262,144 X 8 BIT CMOS MASK ROM Document Title 262,144 X 8 BIT CMOS MASK ROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 11, 1999 Preliminary PRELIMINARY (November,
White Electronic Designs
256Kx32 Static RM CMOS, High Speed Module FETURES 256Kx32 bit CMOS Static Random ccess Memory ccess Times: 12, 15, 20, and 25ns Individual Byte Selects Fully Static, No Clocks TTL Compatible I/O High Density
I/O 0 I/O 7 WE CE 2 OE CE 1 A17 A18
2M x 8 Static RAM Features High speed t AA = 8, 10, 12 ns Low active power 1080 mw (max.) Operating voltages of 3.3 ± 0.3V 2.0V data retention Automatic power-down when deselected TTL-compatible inputs
LY62L102516A 1024K x 16 BIT LOW POWER CMOS SRAM
Y62102516A 1024K x 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jan. 09. 2012 Rev. 1.1 Deleted WRITE CYCE Notes : 1.WE#,, B#, UB# must be high or must
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue July 23, 2003 1.0 Remove 24/26-pin
MB85R M Bit (128 K 8) Memory FRAM CMOS DS E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET
FUJITSU SEMICONDUCTOR DATA SHEET DS05-13103-5E Memory FRAM CMOS 1 M Bit (128 K 8) MB85R1001 DESCRIPTIONS The MB85R1001 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072 words x
LY62L409716A 4M X 16 BIT LOW POWER CMOS SRAM
Y62409716A 4M 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jun.08.2017 yontek Inc. reserves the rights to change the specifications and products without
LY62W K X 16 BIT LOW POWER CMOS SRAM
REVISION ISTORY Revision Description Issue Date Initial Issue Jul.13.2011 0 FEATURES Fast access time : 55/70ns ow power consumption: Operating current : 45/30mA (TYP.) Standby current : 10A (TYP.) -version
EDI8G322048C DESCRIPTION FEATURES PIN CONFIGURATION PIN NAMES
2048K x 32 Static RM CMOS, High Speed Module FETURES n 2048K x 32 bit CMOS Static n Random ccess Memory ccess Times: 20, 25, and 35ns Individual Byte Selects Fully Static, No Clocks TTL Compatible I/O
AS6C TINL 16M Bits LOW POWER CMOS SRAM
REVISION ISTORY Revision Description Issue Date Initial Issue Jan. 09. 2012 0 FEATURES Fast access time : 55ns ow power consumption: Operating current : 45mA (TYP.) Standby current : 4 A (TYP.) S-version
LY62L K X 16 BIT LOW POWER CMOS SRAM
Y6225716 256K 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Apr.19.2006 Rev. 2.0 Revised ISB(max) : 0.5mA => 1.25mA May.11.2006 Rev. 2.1 Adding 44-pin
AT28C K (32K x 8) Paged CMOS E 2 PROM. Features. Description. Pin Configurations
AT28C256 Features Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms
CAT28C17A 16K-Bit CMOS PARALLEL EEPROM
16K-Bit CMOS PARALLEL EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast Read Access Times: 200 ns Low Power CMOS Dissipation: Active: 25 ma Max. Standby: 100 µa Max. Simple Write Operation: On-Chip Address
LY62L K X 16 BIT LOW POWER CMOS SRAM
REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 1.1 Revised Package Outline Dimension(TSOP-II) Apr.12.2007 Rev. 1.2 Added ISB1/IDR values when TA = 25 and TA = 40
AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64-Bytes Internal Program Control
2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
P3C1256 HIGH SPEED 32K x 8 3.3V STATIC CMOS RAM
HIGH SPEED 3K x 8 3.3 STATIC CMOS RAM FEATURES 3.3 Power Supply High Speed (Equal Access and Cycle Times) 1///5 (Commercial) //5 (Industrial) Low Power Single 3.3 olts ±.3olts Power Supply Easy Memory
IS42VS83200J / IS42VS16160J / IS42VS32800J
32Mx8, 16Mx16, 8Mx32 256Mb Synchronous DRAM FEATURES Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access and precharge Programmable CAS latency: 2, 3
M0360. Rev: /08
www.centon.com MEMORY SPECIFICATIONS 32MX8 BASED 33,554,432words x 72Bit Synchronous Dynamic RAM Memory Module (Unbuffered DIMM) Centon's 256MB ECC UNBUFFERED Memory Module is 33,554,432 words by 72Bit
IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL
IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JUNE 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
White Electronic Designs
12Kx32 EEPROM MODULE, SMD 5962-9455 FEATURES Access Times of 120**, 140, 150, 200, 250, 300ns Packaging: 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic Ceramic HIP (Package 400) 6 lead, 22.4mm sq.
CAT28C K-Bit Parallel EEPROM
256K-Bit Parallel EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast read access times: 120/150ns Low power CMOS dissipation: Active: 25 ma max Standby: 150 µa max Simple write operation: On-chip address and
Product Change Notification (PCN)
Product Change Notification (PCN) Alliance Memory Inc. 511 Taylor Way, Suite 1, San Carlos, CA 94070 Main +1(650)610-6800 FAX +1(650)620-9211 Date: June 1, 2017 PCN TRACKING NO:PCN-29052017-01 Subject:
LY68L M Bits Serial Pseudo-SRAM with SPI and QPI
REVISION HISTORY Revision Description Issue Date Rev. 0.1 Initial Issued May.6. 2016 Rev. 0.2 Revised typos May.19. 2016 Revised the address bit length from 32 bits to 24 bits Oct.13. 2016 0 FEATURES GENERAL
MB85R K (32 K 8) Bit. Memory FRAM DS E CMOS DESCRIPTIONS FEATURES PACKAGES FUJITSU SEMICONDUCTOR DATA SHEET
FUJITSU SEMICONDUCTOR DATA SHEET DS05-13101-4E Memory FRAM CMOS 256 K (32 K 8) Bit MB85R256 DESCRIPTIONS The MB85R256 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words
IDT7134SA/LA. HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM
Features High-speed access : 5/45//7 (max.) Industrial: / (max.) Commercial: 2//5/45//7 (max.) Low-power operation IDT714 Active: 7mW (typ.) Standby: 5mW (typ.) IDT714 Active: 7mW (typ.) Standby: 1mW (typ.)
ACT-S128K32 High Speed 4 Megabit SRAM Multichip Module
CT-S128K32 High Speed 4 Megabit SRM Multichip Module Features 4 Low Power CMOS 128K x 8 SRMs in one MCM Overall configuration as 128K x 32 Input and Output TTL Compatible 17, 20, 25, 35, 45 & 55ns ccess
FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13
128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM FEATURES Fast access time : 55ns ow power consumption: Operating current : 20/18mA (TYP.) Standby current : 2µA (TYP.) Single 2.7V ~ 5.5V power
A 4 A 3 A 2 ROW DECODER 64K x 16 RAM Array I/O 1 I/O X 2048 I/O 9 I/O 16
64K x 16 Static RAM Features Pin- and function-compatible with CY7C1021BV33 High speed t AA = 8, 10, 12, and 15 ns CMOS for optimum speed/power Low active power 360 mw (max.) Data retention at 2.0V Automatic
CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16
CMOS PARALLEL-TO-SERIAL FIFO IDT72125 FEATURES: 25ns parallel port access time, 35ns cycle time 50MHz serial shift frequency ide x16 organization offering easy expansion Low power consumption (50mA typical)
WINTEC I. DESCRIPTION: III. TIMING
ISIONS ZONE DESCRIPTION APPVD 1/26/01 NR I. DESCRIPTION: III. TIMING is a 8Mx64 industry standard 8-pin PC-100 DIMM Manufactured with 4 8Mx 400-mil TSOPII-54 100MHz Synchronous DRAM devices Requires 3.3V+/-0.3V
VERY LOW POWER 1.8V 16K/8K/4K x 16 DUAL-PORT STATIC RAM
VERY LOW POWER 1.8V 16K/8K/4K x 16 DUAL-PORT STATIC RAM IDT70P264/254/244L DATASHEET Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access
2Mb Ultra-Low Power Asynchronous CMOS SRAM. Features. Power Supply (Vcc)
2Mb Ultra-Low Power Asynchronous CMOS SRAM 128Kx16 bit Features Overview The is an integrated memory device containing a 2 Mbit Static Random Access Memory organized as 131,072 words by 16 bits. The device
M8M644S3V9 M16M648S3V9. 8M, 16M x 64 SODIMM
MM644S3V9 MM64S3V9 SDRAM Features: JEDEC Standard 144-pin, PC100, PC133 small outline, dual in-line memory Module (SODIMM) Unbuffered TSOP components. Single 3.3v +.3v power supply. Fully synchronous;
Product Specifications
Product Specificatio L66S7-GAS/GHS/GLS RE:.6 General Information 8MB 6Mx6 SDRAM PC/PC NON-ECC UNBUFFERED -PIN SODIMM Description: The L66S7 is a 6M x 6 Synchronous Dynamic RAM high deity memory module.
4-Mbit (512K x 8) Static RAM
4-Mbit (512K x 8) Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive: 40 C to 125 C High speed t AA = 10 ns Low active power 324 mw (max.) 2.0V data retention
IS41C16257C IS41LV16257C
256Kx16 4Mb DRAM WITH FAST PAGE MODE JANUARY 2013 FEATURES TTL compatible inputs and outputs; tri-state I/O Refresh Interval: 512 cycles/8 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden JEDEC standard
1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018
1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden JEDEC
Industrial Temperature Range: -40 o C to +85 o C Lead-free available KEY TIMING PARAMETERS. Max. CAS Access Time (tcac) ns
1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE APRIL 2005 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden
My-MS. MM27C ,072 x 8 CMOS EPROM PRELIMINARY INFORMATION ISSI IS27C010 FEATURES DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
IS27C010 ISSI MM27C010 131,072 x CMOS EPROM PRELIMINARY INFORMATION FEATURES Fast read access time: 90 ns JEDEC-approved pinout High-speed write programming Typically less than 16 seconds 5V ±10% power
MX23L M-BIT MASK ROM (8/16-BIT OUTPUT) FEATURES PIN CONFIGURATION PIN DESCRIPTION 44 SOP ORDER INFORMATION
32M-BIT MASK ROM (8/16-BIT OUTPUT) FEATURES Bit organization - 4M x 8 (byte mode) - 2M x 16 (word mode) Fast access time - Random access: 70ns (max.) - Page access: 25ns (max.) Page Size - 8 words per
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9
Integrated Device Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,24 X 9, 2,48 X 9, 4,96 x 9 and 8,192 x 9 IDT72421 IDT7221 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 FEATURES: 64 x 9-bit
Advantage Memory Corporation reserves the right to change products and specifications without notice
A832-4X4-66T2 DRAM SIMM FPM 8MX32 DRAM SIMM using 4MX4, 2K Refresh, 5V GENERAL DESCRIPTION The Advantage A832-4X4-66T2 is a 8MX32 Dynamic RAM highdensity memory module. The Advantage A832-4X4-66T2 consists
CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240
64K-Bit CMOS PARALLEL EEPROM
64K-Bit CMOS PARALLEL EEPROM FEATURES Fast read access times: 90/120/150ns Low power CMOS dissipation: Active: 25 ma max. Standby: 100 µa max. Simple write operation: On-chip address and data latches Self-timed
512KX8 CMOS S-RAM (Monolithic)
512KX8 CMOS S-RAM (Monolithic) Features Access Times: 55, 70, 85 and 100ns Package Option: 32-Pin Ceramic DIP, JEDEC Approved Pinout 36-Lead Ceramic SOJ JEDEC Approved Revolutionary Pinout 32-Lead Ceramic
High Performance 4Kx4 Static RAM MIL-STD-883C
High Performance 4Kx4 Static RAM MIL-STD-883C FEATURES Full Military Temperature Operating Range (-55 0 C to + 125 0 C) MIL-STD-883C Processing 4Kx4 Bit Organisation 55 and 70 nsec-agce-ss-times Fully
AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
AT24C01A/02/04/08/16 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128
Am27C020. Advanced Micro Devices. 2 Megabit (262,144 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 2 Megabit (262,144 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 70 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug
ICE27C Megabit(128KX8) OTP EPROM
1- Megabit(128KX8) OTP EPROM Description The is a low-power, high-performance 1M(1,048,576) bit one-time programmable read only memory (OTP EPROM) organized as 128K by 8 bits. It is single 5V power supply
MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION
![MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION](/thumbs/78/78720826.jpg "MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION")
FEATURES 32K x 8 organization Single +5V power supply +125V programming voltage Fast access time: 45/55/70/90/100/120/150 ns Totally static operation Completely TTL compatible 256K-BIT [32K x 8] CMOS EPROM
1.8V Core Async/Page PSRAM
1.8V Core Async/Page PSRAM Overview The IS66WVE4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits.
Am27C512. Advanced Micro Devices. 512 Kilobit (65,536 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 512 Kilobit (65,536 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 55 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single
2-Mbit (128K x 16) Static RAM
2-Mbit (128K x 16) Static RAM Features Temperature Ranges Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C High speed: 55 ns Wide voltage range: 2.7V 3.6V Ultra-low active,
P2M648YL, P4M6416YL. PIN ASSIGNMENT (Front View) 168-PIN DIMM. 8-2Mx8 SDRAM TSOP P2M648YL-XX 16-2Mx8 SDRAM TSOP P4M6416YL-XX
SDRAM MODULE Features: JEDEC - Standard 168-pin (gold), dual in-line memory module (DIMM). TSOP components. Single 3.3v +.3v power supply. Nonbuffered fully synchronous; all signals measured on positive
FM18L08 256Kb Bytewide FRAM Memory
256Kb Bytewide FRAM Memory Features 256K bit Ferroelectric Nonvolatile RAM Organized as 32,768 x 8 bits 45 year Data Retention Unlimited Read/Write Cycles NoDelay Writes Advanced High-Reliability Ferroelectric
IS41C16256C IS41LV16256C
256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 FEATURES TTL compatible inputs and outputs; tri-state I/O Refresh Interval: 512 cycles/8 ms Refresh Mode : -Only, CAS-before- (CBR), and Hidden JEDEC standard
P8M644YA9, 16M648YA9. PIN ASSIGNMENT (Front View) 168-PIN DIMM. 4-8Mx16 SDRAM TSOP P8M644YA9 8-8Mx16 SDRAM TSOP P16M648YA9
SDRAM MODULE P8M644YA9, 16M648YA9 8M, 16M x 64 DIMM Features: PC100 and PC133 - compatible JEDEC - Standard 168-pin, dual in-line memory module (DIMM). TSOP components. Single 3.3v +. 3v power supply.
IS41C16100C IS41LV16100C
1Mx16 16Mb DRAM WITH EDO PAGE MODE FEBRUARY 2012 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: Auto refresh Mode: 1,024 cycles /16 ms -Only, CAS-before- (CBR), and Hidden Self
DS1225Y 64k Nonvolatile SRAM
19-5603; Rev 10/10 NOT RECOMMENDED FOR NEW DESIGNS 64k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during
FM1608B 64Kb Bytewide 5V F-RAM Memory
Pre-Production FM1608B 64Kb Bytewide 5V F-RAM Memory Features 64Kbit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits High Endurance 1 Trillion (10 12 ) Read/Writes 38 year Data Retention (@ +75
IS62/65WVS1288FALL IS62/65WVS1288FBLL. 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE DESCRIPTION
128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE JANUARY 2018 KEY FEATURES SPI-Compatible Bus Interface: - 16/20 MHz Clock rate - SPI/SDI/SQI mode Low-Power CMOS Technology: - Read Current:
Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 128 Kilobit (16,384 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 45 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single
256K-Bit PARALLEL EEPROM
256K-Bit PARALLEL EEPROM FEATURES Fast read access times: 120/150ns Low power CMOS dissipation: Active: 25 ma max Standby: 150 µa max Simple write operation: On-chip address and data latches Self-timed
FM Kb Bytewide FRAM Memory
64Kb Bytewide FRAM Memory Features 64K bit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits High endurance 10 Billion (10 10 ) read/writes 10 year data retention at 85 C NoDelay write Advanced
GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE DECEMBER 2006 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: Auto refresh Mode: 1,024 cycles /16 ms -Only, CAS-before- (CBR),