Fault-adaptive routing

Size: px
Start display at page:

Download "Fault-adaptive routing"

Transcription

1 Fault-adaptive routing Presenter: Zaheer Ahmed Supervisor: Adan Kohler Reviewers: Prof. Dr. M. Radetzki Prof. Dr. H.-J. Wunderlich Date: 30-June /2/2009

2 Agenda Motivation Fundamentals of Routing & Blocks Models xtended X-Y Routing and xtended MCC Fault Model Force Directed Wormhole Routing Conclusion 2

3 Agenda Motivation Fundamentals of Routing & Blocks Models xtended X-Y Routing and xtended MCC Fault Model Force Directed Wormhole Routing Conclusion 3

4 Motivation Fault Adaptive Routing Ability to operate in the event of failure of component Low Communication latency High Throughput 4

5 Agenda Motivation Fundamentals of Routing & Fault Block Models xtended X-Y Routing and xtended MCC Fault Model Force Directed Wormhole Routing Conclusion 5

6 2D mesh Topology Consist of n n Node Address of each Switch is defined as (X,Y) where x and y in range of {0,1,2,.,n-1} ach inner node have 4 neighbors IP core IP core IP core IP core IP core IP core Corner and boundary have 2 and 3 neighbors respectively IP core IP core IP core NoC Switch IP: Intellectual Property IP core 6

7 Types of Routing Algorithm Deterministic Routing Algorithm Uses only one predefine path to destination can be minimal or non-minimal Adaptive Routing Algorithm Can use multiple path to destination based on conditions Can be minimal or non-minimal 7

8 X-Y Routing Algorithm Deterministic Routing There two Steps to destination Packet travel x-dimension until x offset zero Packet travel y-dimension until y offset zero 8

9 X-Y Routing Algorithm Cont Cannot tolerate even a single fault 9

10 Odd-ven Turn Model SW and NW turns are Forbidden in Odd Column SW and NW turns are Forbidden in ven Column S: South-ast N: ast-north NW: North-West WS: West-South [Source: Glass, C.J.; Ni, L.M., "The Turn Model for Adaptive Routing," Computer Arch Proceedings., The 19th Annual International Symposium, pp , 1992] 10

11 Fault Blocks Fault block is a set of nodes excluded from routing Fault block consist of following nodes Faulty Nodes Unsafe Nodes Unreachable Nodes 11

12 Agenda Motivation Fundamentals of Routing & Fault Blocks Models xtended X-Y Routing and xtended MCC Fault Model Force Directed Wormhole Routing Conclusion MCC: Minimal Connected Components 12

13 xtended X-Y Routing Implements Odd-ven Turn Model Algorithm Consist of Two phases Phase1: Travel along X-dimension Phase2: Travel along Y-dimension ach Phase has two modes Normal mode: Follows X-Y Routing Abnormal mode: Traffic diversion is case of hitting faulty node [Source: J. Wu and D. Wang. Fault tolerant and Deadlock-Free routing in 2-D Meshes using Rectilinear-Monotone Polygonal Fault blocks in Proceedings. International Conference on Parallel Processing, 2002, pp ] 13

14 xtended X-Y Routing Cont Phase1 Abnormal mode Packet hit faulty block travel in west in even column O O Phase2 Abnormal mode Packet hit from ast and West to faulty block reroute in Odd and ven Column respectively O O [Source: J. Wu and D. Wang. Fault tolerant and Deadlock-Free routing in 2-D Meshes using Rectilinear-Monotone Polygonal Fault blocks in Proceedings. International Conference on Parallel Processing, 2002, pp ] 14

15 xtended X-Y Routing Cont [Source: J. Wu and D. Wang. Fault tolerant and Deadlock-Free routing in 2- D Meshes using Rectilinear-Monotone Polygonal Fault blocks in Proceedings. International Conference on Parallel Processing, 2002, pp ] 15

16 Minimal Connected Component Fault Block Produces Rectilinear Polygon Shape Source consider at Origin Nodes are labeled as: Useless, if north and east nodes are faulty Can t Reach, if south and west nodes are faulty MCC: Minimal Connected Component 16

17 MCC Fault Block Cont.. Less no. of nodes are included than Rectangular Blocks D S MCC: Minimal Connected Component [Source: J. Wu and D. Wang. Fault tolerant and Deadlock-Free routing in 2-D Meshes using Rectilinear-Monotone Polygonal Fault blocks in Proceedings. International Conference on Parallel Processing, 2002, pp ] 17

18 xtended Minimal Connected Component Merge Two MCC Blocks Facilitate Odd-ven Turn Model MCC: Minimal Connected Components [Source: J. Wu and D. Wang. Fault tolerant and Deadlock- Free routing in 2-D Meshes using Rectilinear-Monotone Polygonal Fault blocks in Proceedings. International Conference on Parallel Processing, 2002, pp ] 18

19 xtended X-Y Routing with xtended MCC Blocks Phase1: packet travel in even Column for North and South bound Phase2: Routed clockwise for I and III quadrant Routed anticlockwise for II and IV quadrant (a) (b) [Source: J. Wu and D. Wang. Fault tolerant and Deadlock- Free routing in 2-D Meshes using Rectilinear-Monotone Polygonal Fault blocks in Proceedings. International Conference on Parallel Processing, 2002, pp ] 19

20 Agenda Motivation Fundamentals of Routing & Fault Blocks Models xtended X-Y Routing and xtended MCC Fault Model Force Directed Wormhole Routing Conclusion MCC: Minimal Connected Components 20

21 Force Directed Wormhole Routing Algorithm Based on Distance Vector Routing Routing Decision based on routing Tables and buffer status of its neighbor Network Initialize with building routing table 21

22 Building Routing Table ach switch send routing flit to its neighbors If a shorter path received, update routing table D Mesh 5 8 Port North South ast West Number of hops to Number of hops to Number of hops to Number of hops to Number of hops to Number of hops to Number of hops to Number of hops to Number of hops to Routing table of switch 4 in 3 3 Mesh [Source: T. Schönwald, J. Zimmermann, O. Bringmann and W. Rosentiel. Fully adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures, Digital System Design Architectures, Methods and Tools, uromicro Conference, Aug 2007 ] 22

23 Routing Packets D=3 D=3 Answer 7 Answer 8 Confirm Address 5 D=0 Answer Address Address 3 5 Confirm Others 8 [Source: T. Schönwald, J. Zimmermann, O. Bringmann and W. Rosentiel. Fully adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures, Digital System Design Architectures, Methods and Tools, uromicro Conference, Aug 2007 ] 23

24 Load Balancing Avoid Network Congestion Penalties are use to avoid overload links Penalty= PAYLOAD_LNGTH no. of Flits sent Distance= α*hopcounttodestination + β*penalty Port North South ast West Penalty switch (0,0) Penalty switch (1,0) Penalty switch (1,1) Penalty switch (1,2) Penalty switch (2,2) Communication between switch 7 and Switch D Mesh Penalty switch (2,6) Penalty table of switch 4 in 3 3 Mesh 24

25 Fault Tolerance If a switch doesn t receive ANSWR flit node will be assume faulty D S 5 [Source: T. Schönwald, J. Zimmermann, O. Bringmann and W. Rosentiel. Fully adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures, Digital System Design Architectures, Methods and Tools, uromicro Conference, Aug 2007 ] 25

26 Conclusion xt. XY Routing with MCC Blocks Less Memory Overheads Feasible for Large Meshes Create Hot Spot FDWR Algorithm Large Memory Requirements Not Feasible for Large Meshes Load Balancing to avoid Hot Spot MCC: Minimal Connected Component FDWR: Force Directed Wormhole Routing 26

27 Thank you for your attention! 7/2/2009

A Deterministic Fault-Tolerant and Deadlock-Free Routing Protocol in 2-D Meshes Based on Odd-Even Turn Model

A Deterministic Fault-Tolerant and Deadlock-Free Routing Protocol in 2-D Meshes Based on Odd-Even Turn Model A Deterministic Fault-Tolerant and Deadlock-Free Routing Protocol in 2-D Meshes Based on Odd-Even Turn Model Jie Wu Dept. of Computer Science and Engineering Florida Atlantic University Boca Raton, FL

More information

Fault-Tolerant and Deadlock-Free Routing in 2-D Meshes Using Rectilinear-Monotone Polygonal Fault Blocks

Fault-Tolerant and Deadlock-Free Routing in 2-D Meshes Using Rectilinear-Monotone Polygonal Fault Blocks Fault-Tolerant and Deadlock-Free Routing in -D Meshes Using Rectilinear-Monotone Polygonal Fault Blocks Jie Wu Department of Computer Science and Engineering Florida Atlantic University Boca Raton, FL

More information

NOC Deadlock and Livelock

NOC Deadlock and Livelock NOC Deadlock and Livelock 1 Deadlock (When?) Deadlock can occur in an interconnection network, when a group of packets cannot make progress, because they are waiting on each other to release resource (buffers,

More information

Dynamic Stress Wormhole Routing for Spidergon NoC with effective fault tolerance and load distribution

Dynamic Stress Wormhole Routing for Spidergon NoC with effective fault tolerance and load distribution Dynamic Stress Wormhole Routing for Spidergon NoC with effective fault tolerance and load distribution Nishant Satya Lakshmikanth sailtosatya@gmail.com Krishna Kumaar N.I. nikrishnaa@gmail.com Sudha S

More information

A NEW DEADLOCK-FREE FAULT-TOLERANT ROUTING ALGORITHM FOR NOC INTERCONNECTIONS

A NEW DEADLOCK-FREE FAULT-TOLERANT ROUTING ALGORITHM FOR NOC INTERCONNECTIONS A NEW DEADLOCK-FREE FAULT-TOLERANT ROUTING ALGORITHM FOR NOC INTERCONNECTIONS Slaviša Jovanović, Camel Tanougast, Serge Weber Christophe Bobda Laboratoire d instrumentation électronique de Nancy - LIEN

More information

Deadlock and Livelock. Maurizio Palesi

Deadlock and Livelock. Maurizio Palesi Deadlock and Livelock 1 Deadlock (When?) Deadlock can occur in an interconnection network, when a group of packets cannot make progress, because they are waiting on each other to release resource (buffers,

More information

Interconnection Networks: Routing. Prof. Natalie Enright Jerger

Interconnection Networks: Routing. Prof. Natalie Enright Jerger Interconnection Networks: Routing Prof. Natalie Enright Jerger Routing Overview Discussion of topologies assumed ideal routing In practice Routing algorithms are not ideal Goal: distribute traffic evenly

More information

Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips

Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips Available online at www.sciencedirect.com Procedia Engineering 15 (2011) 3406 3410 Advanced in Control Engineering and Information Science Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant

More information

Fault-Tolerant Routing Algorithm in Meshes with Solid Faults

Fault-Tolerant Routing Algorithm in Meshes with Solid Faults Fault-Tolerant Routing Algorithm in Meshes with Solid Faults Jong-Hoon Youn Bella Bose Seungjin Park Dept. of Computer Science Dept. of Computer Science Dept. of Computer Science Oregon State University

More information

Fault-Tolerant Wormhole Routing Algorithms in Meshes in the Presence of Concave Faults

Fault-Tolerant Wormhole Routing Algorithms in Meshes in the Presence of Concave Faults Fault-Tolerant Wormhole Routing Algorithms in Meshes in the Presence of Concave Faults Seungjin Park Jong-Hoon Youn Bella Bose Dept. of Computer Science Dept. of Computer Science Dept. of Computer Science

More information

On Constructing the Minimum Orthogonal Convex Polygon in 2-D Faulty Meshes

On Constructing the Minimum Orthogonal Convex Polygon in 2-D Faulty Meshes On Constructing the Minimum Orthogonal Convex Polygon in 2-D Faulty Meshes Jie Wu Department of Computer Science and Engineering Florida Atlantic University Boca Raton, FL 33431 E-mail: jie@cse.fau.edu

More information

EECS 578 Interconnect Mini-project

EECS 578 Interconnect Mini-project EECS578 Bertacco Fall 2015 EECS 578 Interconnect Mini-project Assigned 09/17/15 (Thu) Due 10/02/15 (Fri) Introduction In this mini-project, you are asked to answer questions about issues relating to interconnect

More information

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs -A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs Pejman Lotfi-Kamran, Masoud Daneshtalab *, Caro Lucas, and Zainalabedin Navabi School of Electrical and Computer Engineering, The

More information

On Constructing the Minimum Orthogonal Convex Polygon for the Fault-Tolerant Routing in 2-D Faulty Meshes 1

On Constructing the Minimum Orthogonal Convex Polygon for the Fault-Tolerant Routing in 2-D Faulty Meshes 1 On Constructing the Minimum Orthogonal Convex Polygon for the Fault-Tolerant Routing in 2-D Faulty Meshes 1 Jie Wu Department of Computer Science and Engineering Florida Atlantic University Boca Raton,

More information

FT-Z-OE: A Fault Tolerant and Low Overhead Routing Algorithm on TSV-based 3D Network on Chip Links

FT-Z-OE: A Fault Tolerant and Low Overhead Routing Algorithm on TSV-based 3D Network on Chip Links FT-Z-OE: A Fault Tolerant and Low Overhead Routing Algorithm on TSV-based 3D Network on Chip Links Hoda Naghibi Jouybari College of Electrical Engineering, Iran University of Science and Technology, Tehran,

More information

EC 513 Computer Architecture

EC 513 Computer Architecture EC 513 Computer Architecture On-chip Networking Prof. Michel A. Kinsy Virtual Channel Router VC 0 Routing Computation Virtual Channel Allocator Switch Allocator Input Ports VC x VC 0 VC x It s a system

More information

Fault-Tolerant Routing in Fault Blocks. Planarly Constructed. Dong Xiang, Jia-Guang Sun, Jie. and Krishnaiyan Thulasiraman. Abstract.

Fault-Tolerant Routing in Fault Blocks. Planarly Constructed. Dong Xiang, Jia-Guang Sun, Jie. and Krishnaiyan Thulasiraman. Abstract. Fault-Tolerant Routing in Fault Blocks Planarly Constructed Dong Xiang, Jia-Guang Sun, Jie and Krishnaiyan Thulasiraman Abstract A few faulty nodes can an n-dimensional mesh or torus network unsafe for

More information

Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip

Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip Nauman Jalil, Adnan Qureshi, Furqan Khan, and Sohaib Ayyaz Qazi Abstract

More information

Deadlock-free XY-YX router for on-chip interconnection network

Deadlock-free XY-YX router for on-chip interconnection network LETTER IEICE Electronics Express, Vol.10, No.20, 1 5 Deadlock-free XY-YX router for on-chip interconnection network Yeong Seob Jeong and Seung Eun Lee a) Dept of Electronic Engineering Seoul National Univ

More information

Sanaz Azampanah Ahmad Khademzadeh Nader Bagherzadeh Majid Janidarmian Reza Shojaee

Sanaz Azampanah Ahmad Khademzadeh Nader Bagherzadeh Majid Janidarmian Reza Shojaee Sanaz Azampanah Ahmad Khademzadeh Nader Bagherzadeh Majid Janidarmian Reza Shojaee Application-Specific Routing Algorithm Selection Function Look-Ahead Traffic-aware Execution (LATEX) Algorithm Experimental

More information

Architecture and Design of Efficient 3D Network-on-Chip for Custom Multi-Core SoC

Architecture and Design of Efficient 3D Network-on-Chip for Custom Multi-Core SoC BWCCA 2010 Fukuoka, Japan November 4-6 2010 Architecture and Design of Efficient 3D Network-on-Chip for Custom Multi-Core SoC Akram Ben Ahmed, Abderazek Ben Abdallah, Kenichi Kuroda The University of Aizu

More information

High Performance Interconnect and NoC Router Design

High Performance Interconnect and NoC Router Design High Performance Interconnect and NoC Router Design Brinda M M.E Student, Dept. of ECE (VLSI Design) K.Ramakrishnan College of Technology Samayapuram, Trichy 621 112 brinda18th@gmail.com Devipoonguzhali

More information

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, JANUARY 2014 113 ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels Binzhang Fu, Member, IEEE,

More information

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks Andreas Lankes¹, Soeren Sonntag², Helmut Reinig³, Thomas Wild¹, Andreas Herkersdorf¹

More information

Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH

Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH Outline Introduction Overview of WiNoC system architecture Overlaid

More information

A Literature Review of on-chip Network Design using an Agent-based Management Method

A Literature Review of on-chip Network Design using an Agent-based Management Method A Literature Review of on-chip Network Design using an Agent-based Management Method Mr. Kendaganna Swamy S Dr. Anand Jatti Dr. Uma B V Instrumentation Instrumentation Communication Bangalore, India Bangalore,

More information

JUNCTION BASED ROUTING: A NOVEL TECHNIQUE FOR LARGE NETWORK ON CHIP PLATFORMS

JUNCTION BASED ROUTING: A NOVEL TECHNIQUE FOR LARGE NETWORK ON CHIP PLATFORMS 1 JUNCTION BASED ROUTING: A NOVEL TECHNIQUE FOR LARGE NETWORK ON CHIP PLATFORMS Shabnam Badri THESIS WORK 2011 ELECTRONICS JUNCTION BASED ROUTING: A NOVEL TECHNIQUE FOR LARGE NETWORK ON CHIP PLATFORMS

More information

Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip

Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip Akshay B P 1, Ganesh K M 1, Thippeswamy D R 1, Vishnu S Bhat 1, Anitha Vijayakumar 1, Ananda Y R 2, and John Jose 2 1

More information

Power and Area Efficient NOC Router Through Utilization of Idle Buffers

Power and Area Efficient NOC Router Through Utilization of Idle Buffers Power and Area Efficient NOC Router Through Utilization of Idle Buffers Mr. Kamalkumar S. Kashyap 1, Prof. Bharati B. Sayankar 2, Dr. Pankaj Agrawal 3 1 Department of Electronics Engineering, GRRCE Nagpur

More information

Performance Analysis of NoC Architectures

Performance Analysis of NoC Architectures Performance Analysis of NoC Architectures Anitha G #1,Muralidharan D *2,Muthaiah R #3 School of Computing, SASTRA University,Thanjavur,India #1 mailtoanitharaj@gmail.com, *2 murali@core.sastra.edu, #3

More information

A New Fault Information Model for Fault-Tolerant Adaptive and Minimal Routing in 3-D Meshes

A New Fault Information Model for Fault-Tolerant Adaptive and Minimal Routing in 3-D Meshes A New Fault Information Model for Fault-Tolerant Adaptive and Minimal Routing in 3-D Meshes hen Jiang Department of Computer Science Information Assurance Center West Chester University West Chester, PA

More information

Fault-tolerant & Adaptive Stochastic Routing Algorithm. for Network-on-Chip. Team CoheVer: Zixin Wang, Rong Xu, Yang Jiao, Tan Bie

Fault-tolerant & Adaptive Stochastic Routing Algorithm. for Network-on-Chip. Team CoheVer: Zixin Wang, Rong Xu, Yang Jiao, Tan Bie Fault-tolerant & Adaptive Stochastic Routing Algorithm for Network-on-Chip Team CoheVer: Zixin Wang, Rong Xu, Yang Jiao, Tan Bie Idea & solution to be investigated by the project There are some options

More information

MESH-CONNECTED multicomputers, especially those

MESH-CONNECTED multicomputers, especially those IEEE TRANSACTIONS ON RELIABILITY, VOL. 54, NO. 3, SEPTEMBER 2005 449 On Constructing the Minimum Orthogonal Convex Polygon for the Fault-Tolerant Routing in 2-D Faulty Meshes Jie Wu, Senior Member, IEEE,

More information

MESH-CONNECTED networks have been widely used in

MESH-CONNECTED networks have been widely used in 620 IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 5, MAY 2009 Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model Dong Xiang, Senior Member, IEEE, Yueli Zhang,

More information

ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures: Rou1ng. Prof. Natalie Enright Jerger

ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures: Rou1ng. Prof. Natalie Enright Jerger ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures: Rou1ng Prof. Natalie Enright Jerger Announcements Feedback on your project proposals This week Scheduled extended 1 week Next week:

More information

TDT Appendix E Interconnection Networks

TDT Appendix E Interconnection Networks TDT 4260 Appendix E Interconnection Networks Review Advantages of a snooping coherency protocol? Disadvantages of a snooping coherency protocol? Advantages of a directory coherency protocol? Disadvantages

More information

A Dynamic NOC Arbitration Technique using Combination of VCT and XY Routing

A Dynamic NOC Arbitration Technique using Combination of VCT and XY Routing 727 A Dynamic NOC Arbitration Technique using Combination of VCT and XY Routing 1 Bharati B. Sayankar, 2 Pankaj Agrawal 1 Electronics Department, Rashtrasant Tukdoji Maharaj Nagpur University, G.H. Raisoni

More information

The Odd-Even Turn Model for Adaptive Routing

The Odd-Even Turn Model for Adaptive Routing IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 11, NO. 7, JULY 2000 729 The Odd-Even Turn Model for Adaptive Routing Ge-Ming Chiu, Member, IEEE Computer Society AbstractÐThis paper presents

More information

Joint consideration of performance, reliability and fault tolerance in regular Networks-on-Chip via multiple spatially-independent interface terminals

Joint consideration of performance, reliability and fault tolerance in regular Networks-on-Chip via multiple spatially-independent interface terminals Joint consideration of performance, reliability and fault tolerance in regular Networks-on-Chip via multiple spatially-independent interface terminals Philipp Gorski, Tim Wegner, Dirk Timmermann University

More information

EECS 570. Lecture 19 Interconnects: Flow Control. Winter 2018 Subhankar Pal

EECS 570. Lecture 19 Interconnects: Flow Control. Winter 2018 Subhankar Pal Lecture 19 Interconnects: Flow Control Winter 2018 Subhankar Pal http://www.eecs.umich.edu/courses/eecs570/ Slides developed in part by Profs. Adve, Falsafi, Hill, Lebeck, Martin, Narayanasamy, Nowatzyk,

More information

Interconnection topologies (cont.) [ ] In meshes and hypercubes, the average distance increases with the dth root of N.

Interconnection topologies (cont.) [ ] In meshes and hypercubes, the average distance increases with the dth root of N. Interconnection topologies (cont.) [ 10.4.4] In meshes and hypercubes, the average distance increases with the dth root of N. In a tree, the average distance grows only logarithmically. A simple tree structure,

More information

PERFORMANCE EVALUATION OF FAULT TOLERANT METHODOLOGIES FOR NETWORK ON CHIP ARCHITECTURE

PERFORMANCE EVALUATION OF FAULT TOLERANT METHODOLOGIES FOR NETWORK ON CHIP ARCHITECTURE PERFORMANCE EVALUATION OF FAULT TOLERANT METHODOLOGIES FOR NETWORK ON CHIP ARCHITECTURE By HAIBO ZHU A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN

More information

Basic Switch Organization

Basic Switch Organization NOC Routing 1 Basic Switch Organization 2 Basic Switch Organization Link Controller Used for coordinating the flow of messages across the physical link of two adjacent switches 3 Basic Switch Organization

More information

PDA-HyPAR: Path-Diversity-Aware Hybrid Planar Adaptive Routing Algorithm for 3D NoCs

PDA-HyPAR: Path-Diversity-Aware Hybrid Planar Adaptive Routing Algorithm for 3D NoCs PDA-HyPAR: Path-Diversity-Aware Hybrid Planar Adaptive Routing Algorithm for 3D NoCs Jindun Dai *1,2, Renjie Li 2, Xin Jiang 3, Takahiro Watanabe 2 1 Department of Electrical Engineering, Shanghai Jiao

More information

Extended Junction Based Source Routing Technique for Large Mesh Topology Network on Chip Platforms

Extended Junction Based Source Routing Technique for Large Mesh Topology Network on Chip Platforms Extended Junction Based Source Routing Technique for Large Mesh Topology Network on Chip Platforms Usman Mazhar Mirza Master of Science Thesis 2011 ELECTRONICS Postadress: Besöksadress: Telefon: Box 1026

More information

HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip

HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip Rickard Holsmark 1, Maurizio Palesi 2, Shashi Kumar 1 and Andres Mejia 3 1 Jönköping University, Sweden 2 University of Catania,

More information

ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures: Rou1ng. Prof. Natalie Enright Jerger

ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures: Rou1ng. Prof. Natalie Enright Jerger ECE 1749H: Interconnec1on Networks for Parallel Computer Architectures: Rou1ng Prof. Natalie Enright Jerger Rou1ng Overview Discussion of topologies assumed ideal rou1ng In prac1ce Rou1ng algorithms are

More information

Lecture 24: Interconnection Networks. Topics: topologies, routing, deadlocks, flow control

Lecture 24: Interconnection Networks. Topics: topologies, routing, deadlocks, flow control Lecture 24: Interconnection Networks Topics: topologies, routing, deadlocks, flow control 1 Topology Examples Grid Torus Hypercube Criteria Bus Ring 2Dtorus 6-cube Fully connected Performance Bisection

More information

OASIS NoC Architecture Design in Verilog HDL Technical Report: TR OASIS

OASIS NoC Architecture Design in Verilog HDL Technical Report: TR OASIS OASIS NoC Architecture Design in Verilog HDL Technical Report: TR-062010-OASIS Written by Kenichi Mori ASL-Ben Abdallah Group Graduate School of Computer Science and Engineering The University of Aizu

More information

Global Adaptive Routing Algorithm Without Additional Congestion Propagation Network

Global Adaptive Routing Algorithm Without Additional Congestion Propagation Network 1 Global Adaptive Routing Algorithm Without Additional Congestion ropagation Network Shaoli Liu, Yunji Chen, Tianshi Chen, Ling Li, Chao Lu Institute of Computing Technology, Chinese Academy of Sciences

More information

Interconnection Networks: Topology. Prof. Natalie Enright Jerger

Interconnection Networks: Topology. Prof. Natalie Enright Jerger Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design

More information

A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction

A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction 2009 12th Euromicro Conference on Digital System Design / Architectures, Methods and Tools A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction A. Ehsani Zonouz, M. Seyrafi,

More information

Demand Based Routing in Network-on-Chip(NoC)

Demand Based Routing in Network-on-Chip(NoC) Demand Based Routing in Network-on-Chip(NoC) Kullai Reddy Meka and Jatindra Kumar Deka Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, India Abstract

More information

Routing Algorithm. How do I know where a packet should go? Topology does NOT determine routing (e.g., many paths through torus)

Routing Algorithm. How do I know where a packet should go? Topology does NOT determine routing (e.g., many paths through torus) Routing Algorithm How do I know where a packet should go? Topology does NOT determine routing (e.g., many paths through torus) Many routing algorithms exist 1) Arithmetic 2) Source-based 3) Table lookup

More information

Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC

Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2016.16.3.359 ISSN(Online) 2233-4866 Performance Oriented Docket-NoC (Dt-NoC)

More information

Networks: Routing, Deadlock, Flow Control, Switch Design, Case Studies. Admin

Networks: Routing, Deadlock, Flow Control, Switch Design, Case Studies. Admin Networks: Routing, Deadlock, Flow Control, Switch Design, Case Studies Alvin R. Lebeck CPS 220 Admin Homework #5 Due Dec 3 Projects Final (yes it will be cumulative) CPS 220 2 1 Review: Terms Network characterized

More information

Communication Performance in Network-on-Chips

Communication Performance in Network-on-Chips Communication Performance in Network-on-Chips Axel Jantsch Royal Institute of Technology, Stockholm November 24, 2004 Network on Chip Seminar, Linköping, November 25, 2004 Communication Performance In

More information

Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections

Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections A.SAI KUMAR MLR Group of Institutions Dundigal,INDIA B.S.PRIYANKA KUMARI CMR IT Medchal,INDIA Abstract Multiple

More information

A Novel Semi-Adaptive Routing Algorithm for Delay Reduction in Networks on Chip

A Novel Semi-Adaptive Routing Algorithm for Delay Reduction in Networks on Chip Research Journal of Applied Sciences, Engineering and Technology 4(19): 3641-3645, 212 ISSN: 24-7467 Maxwell Scientific Organization, 212 Submitted: February 13, 212 Accepted: March 24, 212 Published:

More information

An Examination of Routing Algorithms for Parallel Computing Environments

An Examination of Routing Algorithms for Parallel Computing Environments A case can be made that the Achilles heel of parallel processing networks and clusters is that they all have to deal with the unavoidable problem of communication over the System Area Network. In distributed

More information

Dynamic Router Design For Reliable Communication In Noc

Dynamic Router Design For Reliable Communication In Noc Dynamic Router Design For Reliable Communication In Noc Mr. G.Kumaran 1, Ms. S.Gokila, M.E., 2 VLSI Design, Electronics and Comm. Department, Pavai College of Technology, Pachal, Namakkal District, India

More information

A Distributed Formation of Orthogonal Convex Polygons in Mesh-Connected Multicomputers

A Distributed Formation of Orthogonal Convex Polygons in Mesh-Connected Multicomputers A Distributed Formation of Orthogonal Convex Polygons in Mesh-Connected Multicomputers Jie Wu Department of Computer Science and Engineering Florida Atlantic University Boca Raton, FL 3343 Abstract The

More information

Authors Neetu Soni 1, Khemraj Deshmukh 2. Deparment of Electronics and Telecommunication,CSVTU,Bhilai,C.G.,India

Authors Neetu Soni 1, Khemraj Deshmukh 2. Deparment of Electronics and Telecommunication,CSVTU,Bhilai,C.G.,India International journal of Emerging Trends in Science and Technology A Survey on Different Topologies, Switching Techniques and Routing Algorithms for A Network on Chip Authors Neetu Soni 1, Khemraj Deshmukh

More information

Topologies. Maurizio Palesi. Maurizio Palesi 1

Topologies. Maurizio Palesi. Maurizio Palesi 1 Topologies Maurizio Palesi Maurizio Palesi 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and

More information

Lecture 12: Interconnection Networks. Topics: dimension/arity, routing, deadlock, flow control

Lecture 12: Interconnection Networks. Topics: dimension/arity, routing, deadlock, flow control Lecture 12: Interconnection Networks Topics: dimension/arity, routing, deadlock, flow control 1 Interconnection Networks Recall: fully connected network, arrays/rings, meshes/tori, trees, butterflies,

More information

Lecture 3: Flow-Control

Lecture 3: Flow-Control High-Performance On-Chip Interconnects for Emerging SoCs http://tusharkrishna.ece.gatech.edu/teaching/nocs_acaces17/ ACACES Summer School 2017 Lecture 3: Flow-Control Tushar Krishna Assistant Professor

More information

SoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik

SoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik SoC Design Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik Chapter 5 On-Chip Communication Outline 1. Introduction 2. Shared media 3. Switched media 4. Network on

More information

NOW Handout Page 1. Outline. Networks: Routing and Design. Routing. Routing Mechanism. Routing Mechanism (cont) Properties of Routing Algorithms

NOW Handout Page 1. Outline. Networks: Routing and Design. Routing. Routing Mechanism. Routing Mechanism (cont) Properties of Routing Algorithms Outline Networks: Routing and Design Routing Switch Design Case Studies CS 5, Spring 99 David E. Culler Computer Science Division U.C. Berkeley 3/3/99 CS5 S99 Routing Recall: routing algorithm determines

More information

Network on Chip Architecture: An Overview

Network on Chip Architecture: An Overview Network on Chip Architecture: An Overview Md Shahriar Shamim & Naseef Mansoor 12/5/2014 1 Overview Introduction Multi core chip Challenges Network on Chip Architecture Regular Topology Irregular Topology

More information

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture

More information

Communication in Multicomputers with Nonconvex Faults

Communication in Multicomputers with Nonconvex Faults Communication in Multicomputers with Nonconvex Faults Suresh Chalasani Rajendra V. Boppana Technical Report : CS-96-12 October 1996 The University of Texas at San Antonio Division of Computer Science San

More information

Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection

Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz School of Electronics and Computer Science University of Southampton

More information

A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design

A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design Zhi-Liang Qian and Chi-Ying Tsui VLSI Research Laboratory Department of Electronic and Computer Engineering The Hong Kong

More information

Lecture: Interconnection Networks. Topics: TM wrap-up, routing, deadlock, flow control, virtual channels

Lecture: Interconnection Networks. Topics: TM wrap-up, routing, deadlock, flow control, virtual channels Lecture: Interconnection Networks Topics: TM wrap-up, routing, deadlock, flow control, virtual channels 1 TM wrap-up Eager versioning: create a log of old values Handling problematic situations with a

More information

ACO-BASED FAULT-AWARE ROUTING ALGORITHM FOR NETWORK-ON-CHIP SYSTEMS

ACO-BASED FAULT-AWARE ROUTING ALGORITHM FOR NETWORK-ON-CHIP SYSTEMS 2013 IEEE Workshop on Signal Processing Systems ACO-BASED FAULT-AWARE ROUTING ALGORITHM FOR NETWORK-ON-CHIP SYSTEMS Chia-An Lin, Hsien-Kai Hsin, En-Jui Chang, and An-Yeu (Andy) Wu Graduate Institute of

More information

Lecture 12: Interconnection Networks. Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E)

Lecture 12: Interconnection Networks. Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E) Lecture 12: Interconnection Networks Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E) 1 Topologies Internet topologies are not very regular they grew

More information

The Nostrum Network on Chip

The Nostrum Network on Chip The Nostrum Network on Chip 10 processors 10 processors Mikael Millberg, Erland Nilsson, Richard Thid, Johnny Öberg, Zhonghai Lu, Axel Jantsch Royal Institute of Technology, Stockholm November 24, 2004

More information

SOFTWARE BASED FAULT-TOLERANT OBLIVIOUS ROUTING IN PIPELINED NETWORKS*

SOFTWARE BASED FAULT-TOLERANT OBLIVIOUS ROUTING IN PIPELINED NETWORKS* SOFTWARE BASED FAULT-TOLERANT OBLIVIOUS ROUTING IN PIPELINED NETWORKS* Young-Joo Suh, Binh Vien Dao, Jose Duato, and Sudhakar Yalamanchili Computer Systems Research Laboratory Facultad de Informatica School

More information

Design and Evaluation of a Fault-Tolerant Adaptive Router for Parallel Computers

Design and Evaluation of a Fault-Tolerant Adaptive Router for Parallel Computers Design and Evaluation of a Fault-Tolerant Adaptive Router for Parallel Computers Tsutomu YOSHINAGA, Hiroyuki HOSOGOSHI, Masahiro SOWA Graduate School of Information Systems, University of Electro-Communications,

More information

Routing Algorithms. Review

Routing Algorithms. Review Routing Algorithms Today s topics: Deterministic, Oblivious Adaptive, & Adaptive models Problems: efficiency livelock deadlock 1 CS6810 Review Network properties are a combination topology topology dependent

More information

Temperature and Traffic Information Sharing Network in 3D NoC

Temperature and Traffic Information Sharing Network in 3D NoC , October 2-23, 205, San Francisco, USA Temperature and Traffic Information Sharing Network in 3D NoC Mingxing Li, Ning Wu, Gaizhen Yan and Lei Zhou Abstract Monitoring Network on Chip (NoC) status, such

More information

Efficient And Advance Routing Logic For Network On Chip

Efficient And Advance Routing Logic For Network On Chip RESEARCH ARTICLE OPEN ACCESS Efficient And Advance Logic For Network On Chip Mr. N. Subhananthan PG Student, Electronics And Communication Engg. Madha Engineering College Kundrathur, Chennai 600 069 Email

More information

4. Networks. in parallel computers. Advances in Computer Architecture

4. Networks. in parallel computers. Advances in Computer Architecture 4. Networks in parallel computers Advances in Computer Architecture System architectures for parallel computers Control organization Single Instruction stream Multiple Data stream (SIMD) All processors

More information

Recall: The Routing problem: Local decisions. Recall: Multidimensional Meshes and Tori. Properties of Routing Algorithms

Recall: The Routing problem: Local decisions. Recall: Multidimensional Meshes and Tori. Properties of Routing Algorithms CS252 Graduate Computer Architecture Lecture 16 Multiprocessor Networks (con t) March 14 th, 212 John Kubiatowicz Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~kubitron/cs252

More information

CONGESTION AWARE ADAPTIVE ROUTING FOR NETWORK-ON-CHIP COMMUNICATION. Stephen Chui Bachelor of Engineering Ryerson University, 2012.

CONGESTION AWARE ADAPTIVE ROUTING FOR NETWORK-ON-CHIP COMMUNICATION. Stephen Chui Bachelor of Engineering Ryerson University, 2012. CONGESTION AWARE ADAPTIVE ROUTING FOR NETWORK-ON-CHIP COMMUNICATION by Stephen Chui Bachelor of Engineering Ryerson University, 2012 A thesis presented to Ryerson University in partial fulfillment of the

More information

Interconnection Networks

Interconnection Networks Interconnection Networks Interconnection Networks Introduction How to connect individual devices together into a group of communicating devices? Device: r r r Component within a computer Single computer

More information

Chapter 7 Slicing and Dicing

Chapter 7 Slicing and Dicing 1/ 22 Chapter 7 Slicing and Dicing Lasse Harju Tampere University of Technology lasse.harju@tut.fi 2/ 22 Concentrators and Distributors Concentrators Used for combining traffic from several network nodes

More information

ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips

ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips : An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips Varsha Sharma, Rekha Agarwal Manoj S. Gaur, Vijay Laxmi, and Vineetha V. Computer Engineering Department, Malaviya

More information

Bursty Communication Performance Analysis of Network-on-Chip with Diverse Traffic Permutations

Bursty Communication Performance Analysis of Network-on-Chip with Diverse Traffic Permutations International Journal of Soft Computing and Engineering (IJSCE) Bursty Communication Performance Analysis of Network-on-Chip with Diverse Traffic Permutations Naveen Choudhary Abstract To satisfy the increasing

More information

Citation for final published version: Publishers page: <

Citation for final published version: Publishers page:   < This is an Open Access document downloaded from ORCA, Cardiff University's institutional repository: http://orca.cf.ac.uk/109719/ This is the author s version of a work that was submitted to / accepted

More information

Evaluation of Effect of Packet Injection Rate and Routing Algorithm on Network-on-Chip Performance

Evaluation of Effect of Packet Injection Rate and Routing Algorithm on Network-on-Chip Performance Evaluation of Effect of Packet Injection Rate and Routing Algorithm on Network-on-Chip Performance Mostafa Haghi 1, M. Asha Rani 2 P.G. Student, Department of Electronics and Telecommunication, Jawaherlal

More information

Resource Deadlocks and Performance of Wormhole Multicast Routing Algorithms

Resource Deadlocks and Performance of Wormhole Multicast Routing Algorithms IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 9, NO. 6, JUNE 1998 535 Resource Deadlocks and Performance of Wormhole Multicast Routing Algorithms Rajendra V. Boppana, Member, IEEE, Suresh

More information

Communication in Multicomputers with Nonconvex Faults?

Communication in Multicomputers with Nonconvex Faults? In Proceedings of EUROPAR 95 Communication in Multicomputers with Nonconvex Faults? Suresh Chalasani 1 and Rajendra V. Boppana 2 1 Dept. of ECE, University of Wisconsin-Madison, Madison, WI 53706-1691,

More information

Mesh Generation. Quadtrees. Geometric Algorithms. Lecture 9: Quadtrees

Mesh Generation. Quadtrees. Geometric Algorithms. Lecture 9: Quadtrees Lecture 9: Lecture 9: VLSI Design To Lecture 9: Finite Element Method To http://www.antics1.demon.co.uk/finelms.html Lecture 9: To Lecture 9: To component not conforming doesn t respect input not well-shaped

More information

Generic Methodologies for Deadlock-Free Routing

Generic Methodologies for Deadlock-Free Routing Generic Methodologies for Deadlock-Free Routing Hyunmin Park Dharma P. Agrawal Department of Computer Engineering Electrical & Computer Engineering, Box 7911 Myongji University North Carolina State University

More information

Design of a router for network-on-chip. Jun Ho Bahn,* Seung Eun Lee and Nader Bagherzadeh

Design of a router for network-on-chip. Jun Ho Bahn,* Seung Eun Lee and Nader Bagherzadeh 98 Int. J. High Performance Systems Architecture, Vol. 1, No. 2, 27 Design of a router for network-on-chip Jun Ho Bahn,* Seung Eun Lee and Nader Bagherzadeh Department of Electrical Engineering and Computer

More information

A Novel Energy Efficient Source Routing for Mesh NoCs

A Novel Energy Efficient Source Routing for Mesh NoCs 2014 Fourth International Conference on Advances in Computing and Communications A ovel Energy Efficient Source Routing for Mesh ocs Meril Rani John, Reenu James, John Jose, Elizabeth Isaac, Jobin K. Antony

More information

International Journal of Research and Innovation in Applied Science (IJRIAS) Volume I, Issue IX, December 2016 ISSN

International Journal of Research and Innovation in Applied Science (IJRIAS) Volume I, Issue IX, December 2016 ISSN Comparative Analysis of Latency, Throughput and Network Power for West First, North Last and West First North Last Routing For 2D 4 X 4 Mesh Topology NoC Architecture Bhupendra Kumar Soni 1, Dr. Girish

More information

Synchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom

Synchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom ISCA 2018 Session 8B: Interconnection Networks Synchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom Aniruddh Ramrakhyani Georgia Tech (aniruddh@gatech.edu) Tushar

More information

A Strategy for Interconnect Testing in Stacked Mesh Network-on- Chip

A Strategy for Interconnect Testing in Stacked Mesh Network-on- Chip 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems A Strategy for Interconnect Testing in Stacked Mesh Network-on- Chip Min-Ju Chan and Chun-Lung Hsu Department of Electrical

More information