Architecture and Design of Efficient 3D Network-on-Chip for Custom Multi-Core SoC

Transcription

1 BWCCA 2010 Fukuoka, Japan November Architecture and Design of Efficient 3D Network-on-Chip for Custom Multi-Core SoC Akram Ben Ahmed, Abderazek Ben Abdallah, Kenichi Kuroda The University of Aizu School of Computer Science and Engineering, Adaptive Systems Laboratory, Aizu-Wakamatsu, Japan. The University of Aizu Adaptive systems lab 1

2 Outline Introduction 2D-OASIS-NoC Overview Minimal Hop Routing Algorithm 3D-OASIS-NoC Architecture Design Results Conclusion The University of Aizu Adaptive systems lab 2

3 Introduction Communication becomes an essential part in current Systems On chip (SoC). Networks-On-chip (NoC) overcomes bus-based systems problems. NoC features: Simple and scalable architecture. Connects processors, memories and other custom designs together. Switches packets instead of switching wires. The University of Aizu Adaptive systems lab 3

4 FIF O 2D-OASIS-NoC overview 4x4 Mesh topology NORTH Wormhole switching FIFO Stall-and-Go flow control 76 bit flit WEST FIFO FIFO EAST SOUTH K. Mori, A. Ben Abdallah, K. Kuroda, Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA, Proc. of The 19th Intelligent System Symposium (FAN 2009), pp , Sep The University of Aizu Adaptive systems lab 4

5 2D-OASIS-NoC pipeline stages Cycle RC SA CT RC SA CT RC SA CT XY routing 4x4 Mesh topology Bidirectional links 76 bit flit 5 ports switch The University of Aizu Adaptive systems lab 5

6 2D-OASIS-NoC drawbacks 2D-NoC advantages become limited and 3D-NoC showed better performance: Decreases the number of hops. Effect the latency and the throughput The University of Aizu Adaptive systems lab 6

7 Contribution Efficient routing algorithm named minimal hop routing algorithm (MHRA). 3D architecture, design and preliminary results. Reduce overall traffic latency by hops minimization The University of Aizu Adaptive systems lab 7

8 Minimal hop routing algorithm Start Route Yes Next_port = EAST xadr == xdst No xadr < xdst No Next_port = WEST Yes yadr == ydst No Yes yadr < ydst No Next_port = NORTH Next_port = SOUTH Yes zadr == zdst No Yes zadr < zdst No Next_port = UP Next_port = DOWN Yes Next_port = LOCAL To switch allocator The University of Aizu Adaptive systems lab 8

9 Minimal hop routing algorithm Current node addresses From previous node module To next node From switch allocator EAST Node 000 Node 2x2x4 Mesh topology xaddr= 000 < xdst= Next port Destination node addresses Payload Input port architecture EAST=0000 Packet format The University of Aizu Adaptive systems lab 9

10 Minimal hop routing algorithm Node 011 Node NORTH xaddr= = xdst= yaddr= 000 < ydst= NORTH= 0000 The University of Aizu Adaptive systems lab 10

11 Minimal hop routing algorithm Node Node 011 xaddr= = xdst= yaddr= = ydst= zaddr= 000 < zdst= 011 UP UP= The University of Aizu Adaptive systems lab 11

12 Minimal hop routing algorithm xaddr= = xdst= yaddr= = ydst= zaddr= 011 = zdst= 011 LOCAL LOCAL= 0000 The University of Aizu Adaptive systems lab 12

13 3D-OASIS-NoC architecture: Switch architecture NORTH PE N U W R E WEST EAST D S SOUTH The University of Aizu Adaptive systems lab 13

14 3D-OASIS-NoC architecture: Switch allocation stop-in (7) data-sent (7) Flow Control Round Robin STALL-Go Flow control Scheduling grant-out (7) sw-cntrl (49) sw-req(7) port-req (49) tail-sent (49) The University of Aizu Adaptive systems lab 14

15 3D-OASIS-NoC architecture: Crossbar traversal From switch allocator To the Next node From Input port The University of Aizu Adaptive systems lab 15

16 Design results: Design methodology Verilog HDL is used. Quartus II Target device : Stratix III Modelsim Module # code lines Define.v 46 Route.v 80 Fifo.v 100 Input_port.v 113 Stop_go.v 56 Matrix_arb.v 111 Sw_alloc.v 109 Mux_out.v 55 Crossbar.v 45 Router.v 69 Network.v 158 Total 942 The University of Aizu Adaptive systems lab 16

17 Design results: Configuration parameters Parameters 2D 3D Network size 4x4-mesh 2x2x4-mesh Buffer depth 4 4 Flit size 28 bit 33 bit Header 12 bit 17 bit Payload 16 bit 16 bit Switching Wormhole Wormhole Flow control Stall-Go Stall-Go Scheduling Round-robin Round-robin Routing X-Y MHRA The University of Aizu Adaptive systems lab 17

18 Design results: Delay Analysis Flits payload are randomly generated. One single destination node: OASIS-NoC (00) and 3D- OASIS-NoC (000). 2D (Destination node:00) 3D (Destination node:000) Improvement % Node(Y-X) Delay Node(Z-Y-X) Delay % improvement The University of Aizu Adaptive systems lab 18

19 Design results: Hardware Complexity Architecture Area (ALUTs) Power(mW) Speed(MHz) Balance Speed Area 2D D % increased 1.74 % overhead 8.5% decreased The University of Aizu Adaptive systems lab 19

20 Conclusion Combining the 3D integration with Network on Chips offers a good opportunity for big Multi-core SoC designs. We present a hardware design for 3D OASIS Network-on- Chip. 3D-OASIS-NoC achieves about 22% overall delay reduction compared with OASIS-NoC with only 1.74% overhead and 52% additional area. The University of Aizu Adaptive systems lab 20

21 Future work Test the design with Larger workloads (like JPEG application). Reduce the routing algorithm complexity. The University of Aizu Adaptive systems lab 21

22 Thank you The University of Aizu Adaptive systems lab 22