Introduction...2 Prerequisites...2 What is a Global Net?...2 Net Scope...2 Defining Global Nets...3 Establishing Connectivity...5 Propagation...

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1 AppNote A P P N O T E S SM Managing Global Nets in DxDesigner 2007 By: Robert Davies Last Modified: November 6, 2009 Table of contents Introduction...2 Prerequisites...2 What is a Global Net?...2 Net Scope...2 Defining Global Nets...3 Establishing Connectivity...5 Propagation...6 November, 06, 2009 Page 1 of 6 Copyright 2009 Mentor Graphics Corporation Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are trademarks of their respective owners.

2 Introduction This White Paper discusses the management of global nets in the Expedition Enterprise and Independent Software Releases using DxDesigner 2007.x. In particular it discusses the differences between global net management in DxDesigner 2007.x and earlier versions of the software and good design practices to ensure design intent matches physical implementation Prerequisites DxDesigner version or later What is a Global Net? A global net is a net (a.k.a. signal) that is connected throughout a design without the need to physically draw the net either across sheets or through the design hierarchy. Typically global nets are used when defining power supplies within a PCB where connections may consist of explicitly wired connections and implicitly connected pins based on the PCB Part Database. Net Scope By default all nets in DxDesigner are created with local scope, that is, all nets with the same name are connected across all sheets of the schematic in the level in which it exists 1. If these nets need to be connected to other components or nets at a different hierarchical level then they must be connected via pins on a hierarchical block symbol. Using such hierarchical block pins it is possible to change the name of the net as it traverses the different levels of hierarchy. Such net name changes are resolved to a single flat net name once the design is passed to PCB layout, the name being resolved to the upper-most net name. For nets such as power and ground rails or global resets, where connectivity may be required at any level in the hierarchy, it is inconvenient to require the user to establish pin connections at every hierarchical boundary and to draw each net segment throughout the design. In this case it is possible to establish a net as global in scope, that is, it will be connected to every other such net throughout the design hierarchy. When passed to PCB this net retains its original name. 1 Unlike some schematic capture tools there is no requirement to have off-sheet/on-sheet connectors in DxDesigner to establish connectivity between sheets; however it is good design practice to do so. November, 06, 2009 Page 2 of 6

3 Defining Global Nets Global nets are managed in DxDesigner by the use of special symbols referred to as TAPs. TAP symbols are PIN type symbols with a Global Signal Name property equal to the value of the global net. When attached to a net stub the net inherits the name of the Global Signal Name property value. The use of the TAP symbol establishes the net as global in scope. Figure 1 shows a TAP symbol for the VCC global net. Figure 1 TAP symbols are stored in the symbol libraries, either in a Central Library or in a distributed library in the same way as any other PIN type or ANNOTATE type symbol, they do not have corresponding Part Entries (Cells, Decals). Typically a user may have a different symbol for each global signal in his design environment; one for VCC, one for GND, one for 2.5V etc. In this way the user may graphically differentiate each symbol to aid in communicating design intent, as illustrated in Figure 2. November, 06, 2009 Page 3 of 6

4 Figure 2 The TAP symbols are made available to the user through the Special Components section of the Setup Settings dialog in DxDesigner (Figure 3 below). Figure 3 November, 06, 2009 Page 4 of 6

5 Once defined in this dialog they are available in the Add Power and Add Ground menu picks and from the toolbar buttons (Figure 4). Figure 4 TAP symbols are not limited to defining just power supply nets, they may also be used for clock nets, reset signals, or any net that traverses multiple levels of a design hierarchy. In this case the user may wish to define a generic clock or reset symbol for use with different nets and modify the Global Signal Name used at the schematic level. This methodology is fully supported. For example the user could use Clk2 and ClkOut within the design and by modifying the Global Signal Name from Clk2 to ClkOut on the instance of the symbol in the schematic two global nets will be established, Clk2 and ClkOut. Establishing Connectivity To ensure all nets are connected to the appropriate Global Signal all net stubs must be terminated with an appropriate TAP symbol. It is the use of the TAP symbol that declares the net global. TAP symbols may be used anywhere in the hierarchy, it is not necessary to have a TAP symbol at every level of the hierarchy, only where the signal is used. Nets that have the same name as a global net but are not connected to the appropriate TAP are treated as local in scope 2. DRC checks 503 and 504 are designed to report such discontinuities. Figure 5 Figure 5 illustrates a correctly terminated Global net connected to other similarly terminated nets throughout the design 2 To support compatibility with designs being brought forward from DxDesigner 2005.x and earlier releases such named nets will be connected to each other at the same level of hierarchy even without the TAP symbol. However, it is good design practice to add the appropriate TAPS to such nets to communicate design intent. November, 06, 2009 Page 5 of 6

6 Figure 6 Figure 6 shows an incorrectly terminated Global net, in this case the net will be treated as a regular net that happens to have the same name as a Global net but it will not be connected to the other global nets. Propagation By defining a net as global in scope it is automatically propagated through the hierarchy, for this reason it is unnecessary and undesirable to connect such nets to hierarchical blocks as in Figure 7 Figure 7 However to support forward compatibility with earlier designs this mechanism is supported. Once again it is preferable to establish good design practice and use TAP symbols as intended both to guarantee connectivity and to determine design intent. November, 06, 2009 Page 6 of 6