Architecture of an efficient MEMS final test system Dr. Martin Brucke, SPEKTRA Dresden

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1 Architecture of an efficient MEMS final test system Dr. Martin Brucke, SPEKTRA Dresden

2 Architecture of an efficient MEMS final test system Outline Introduction of SPEKTRA What are typical Measurement tasks for the final test of MEMS devices? What does efficient mean? Our Approach Conclusions Discussions

Introduction of SPEKTRA Founded 1994 in Dresden, 50 employees, Locations: Dresden, California (USA) Calibration Systems and Services Vibration, Acoustics, dynamic Force, dynamic Pressure Customers:

3 Introduction of SPEKTRA Founded 1994 in Dresden, 50 employees, Locations: Dresden, California (USA) Calibration Systems and Services Vibration, Acoustics, dynamic Force, dynamic Pressure Customers: National Metrology Institutes, Sensor Manufacturers, Calibration Laboratories Device Testing Excitations: linear/angular Vibration, Shock, Temperature, Magnetic, Acoustics MEMS Final Test System Customers: MEMS Manufacturers

4 Typical Measurement Tasks for the final test of MEMS devices Measurement of electrical power consumptions at different working modes (power up, working mode, idle mode ) Precision DVM Adjustment of measurement / actuation function (acceleration, angular rate, acoustics / micro mirrors, resonators, relays ) communication interfaces to handlers / stimulating units Real time operation capabilities

5 Typical Measurement Tasks for the final test of MEMS devices Contacting tests (Open/Short, Isolation resistance, impedance) Dedicated measurement hardware needed Test of digital communication (protocol, frequency, level) Support of common protocols (SPI, I²C, ) Open for new protocols Tunable digital I/O Limited analogue/digital measurement functions needed

6 What does efficient mean? Our interpretation: Reducing time to market from development to mass production Increasing throughput without affecting the quality Reducing the equipment cost / investment Conference Topic Zero defect in shortest time to market and lowest cost is it possible? Mission impossible??

7 What does efficient mean? Reducing time to market Task: shorten the time from development phase to mass production Time consuming: setting up the tester Hardware and test programs for mass production Tests in development phase are often more extensive than in mass production Using the same tester HW/SW for Development and mass production can help to reduce the time to market

8 What does efficient mean? Increasing the throughput without affecting the quality Throughput = n DUT Testing Time n DUT = MS Factor High parallel operation needed Testing Time Decreasing testing time without affecting the quality More tests in the same time Increasing the data rate between tester and DUT

9 What does efficient mean? Reducing the equipment cost State of the art: Semiconductor tester are used for final test technical overkill and uneconomic Of the shelf measurement hardware (NI, Agilent, ) is used for final test still overkill and uneconomic Dedicated final test hardware produced in high volume can reduce the equipment cost significantly Possible MS Factor depends on type of DUT (acoustics: MS 10, gyroscopes: MS 40, pressure: MS 300 ) Flexibility / scalability of the test system needed

10 Architecture of an efficient MEMS final test system Our approach Schematic of the test system hardware

11 Architecture of an efficient MEMS final test system Our approach Schematic of tester setup Example for R&D Scalable MS factor 2 Mass production application

12 Architecture of an efficient MEMS final test system Our approach Key technical Data Pin-to-Pin Architecture - No shared resources PMU: 4 x four quadrant V/I sources Multi I/O: voltage level -2 V 6 V, up to 10 MHz bandwidth full specification Test DVM: precision voltage/current measurement FPGA: Interface Controller for digital communication, NIOS Microcontroller Open Programming Interfaces Integration into existing Tester environment Integration in development environment (LabView, CVI, )

Architecture of an efficient MEMS final test system Our approach Digital communication realized by IP-Cores in FPGA IP-Cores are developed by SPEKTRA or purchased form 3 rd

13 Architecture of an efficient MEMS final test system Our approach Digital communication realized by IP-Cores in FPGA IP-Cores are developed by SPEKTRA or purchased form 3 rd parties as open source system Actual implemented: SPI, I²C, I²C@18V, CAN, JTAG, PSI5, SENT, LIN In comparison to pattern based systems: Convenient usage of digital communication

14 Architecture of an efficient MEMS final test system Our approach Real time capabilities using the NIOS µc Each DUT gets it s own Tester DUT Communication is not more the bottleneck increasing the data rate between tester and DUT

15 Architecture of an efficient MEMS final test system Conclusions Conference Topic Zero defect in shortest time to market and lowest cost is it possible? Mission impossible?? Usage of the identical Tester HW/SW in development and mass production can reduce time to market Scalable and cost effective Tester HW/SW that suits the demands from MEMS final test reduces costs Testing increases the throughput without affecting the quality more tests in the same time

16 Architecture of an efficient MEMS final test system Discussion Thank you for your attention! Visit us on booth 1365 or

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