Number of CMOS Drivers NT7450OA. Clock Frequency Applicable Driver 1/16, 1/32 NT7451OA NT7450OA, NT7451OA. NT7450oA. 1/8 to 1/32 NT7450AA

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1 NT745 OERIEW The NT745 family of dot matrix LCD drivers are designed for the display of characters and graphics. The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM. The drivers are available in two configuratio. The NT745 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages. These features give the designer a flexible mea of implementing small to medium size LCD displays for compact, low power systems. The NT745 which is able to drive two lines of twelve characters each. The NT745 which is able to drive 8 segments for extention. FEATURES Fast 8bit MPU interface compatible with 8and 68family microcomputers Many command set Total 8 (segment+common) drive sets Low power 3 W at 2 khz external clock Wide range of supply voltages ss : +2.7~ : +3.5~+3. Lowpower CMOS Lineup Product Name Clock Frequency OnChip External Applicable Driver Number of SEG Drivers Number of CMOS Drivers Duty NT745OA 8kHz 8kHz NT745OA, NT745OA 6 6 /6, /32 NT745OA 8kHz NT745oA 8 /8 to /32 NT745AA 2kHz NT745OA, NT745OA 6 6 /6, /32 NT745AA 2kHz NT745OA 8 /8 to /32 NO.2 /24

2 NT745 BLOCK DIAGRAM An example of NT745AA LCD drive Circuit Common counter Display data latch circuit Display start line register Line counter, 2, 3, 4, 5 Line address decoder COM to COM5 SEG to SEG6 Display data RAM (256bit) I/O buffer Column address decoder CL FR Display timing generator circuit Column address counter Column address register Lowaddress register Command decoder Status Bus holder MUP interface D~ A, CS, (E,RW) M/S RES SS NO.2 2/24

3 NT745 PIN DESCRIPTION () Power Pi SS Name,2,3,4,5 Description Connected to the +5 dc power. Common to the cc MPU power pin. dc pin connected to the system ground. Multilevel power supplies for LCD driving. The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied. These voltages must satisfy the following: (2) System Bus Connection Pi to D A RES CS E () () Threestate I/O. The 8bit bidirectional data buses to be connected to the 8 or 6bit standard MPU data buses. Input. Usually connected to the loworder bit of the MPU address bus and used to identify the data or a command. A=: D to are display control data. A=: D to are display data. Input. When the RES signal goes the 68series MPU is initialized, and when it goes, the 8series MPU is initialized. The system is reset during edge see of the RES signal. The interface type to the 68series or 8series MPU is selected by the level input as follows:high level: 68series MPU interface Low level : 8series MPU interface Input. Active low. Effective for an external clock operation model only. An address bus signal is usually decoded by use of chip select signal, and it is entered. If the system has a builtin oscillator, this is used as an input pin to the oscillator amp and an Rf oscillator resistor is connected to it. In such case, the, and E signals must be ORed with the CS signals and entered. If the 68series MPU is connected: Input. Active high. Used as an enable clock input of the 68series MPU. If the 8series MPU is connected: Input. Active low. The signal of the 8series MPU is entered in this pin. When this signal is kept low, the NT745 data bus is in the the output status. If the 68series MPU is connected: Input. Used as an input pin of read control signals (if is high) or write control signals (if low). If the 8series MPU is connected: Input. Active low. The signal of the 8series MPU is entered in this pin. A signal on the data bus is fetched at the rising edge of signal. NO.2 3/24

4 NT745 Product Name 74 NT745OA NT745OA NT745AA NT745AA OSC CS CS CS 75 OSC2 CL CL CL Pad Number 96 to, to COM to COM5* SEG76 to SEG6 COM to COM5* SEG76 to SEG6 M/S SEG79 M/S SEG79 4 SEG78 4 SEG78 SEG77 SEG77 NT745: Common outputs COM to COM5 of the master LSI correspond to COM3 to COM6 of the slave LSI. NO.2 5/24

5 NT745 (3) LCD Drive Circuit Signals Name CL FR Description Input. Effective for an external clock operation model only. This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. If the system has a builtin oscillator. this is used as an output pin for the oscillator amp and an Rf oscillator resistor is connected to it. Input/output. This is an I/P pin of LCD AC signals, and connected to the M terminal of common driver. I/O selection Common oscillator buitin model: Output if M/S is ; Intput if M/S is Dedicate segment model: Input Output. The output pin for LCD column (segment) driving. A single level of, 2, 3 and 5 is selected by the combination of display RAM contents and RF signal. SEGn Output. The Output pin for LCD common (Iow) driving. A single level of,, 4 and 5 is selected by the combination of common counter output and RF signal. The slave LSI has the reverse common output scan sequence than the master LSI. COMn M/S Input. The master or slave LSI operation select pin for the NT745. Connected to (to select the master LSI operation mode) or ss (to select the slave LSI operation mode). When this M/S pin is set, the functio of FR, COM to COM5, OSC (CS), and OSC2 (CL) pi are changed. NT745OA M/S ss FR Output Input COM output COM to COM5 COM3 to COM6 OSC Input NC OSC2 Output Input *The slave driver has the reverse common output scan sequence than the master driver. NO.2 4/24

6 NT745 BLOCK DESCRIPTION System Bus MPU interface.selecting an interface type The NT745 series trafers data via 8bit bidirectional data buses (D to ). As its Reset pin has the MPU interface select function, the 8series MPU or the 68series MPU can directly be connected to the MPU bus by the selection of high or low RES signal level after reset (see Table ). When the CS signal is high, the NT745 series is disconnected from the MPU bus and set to stand by. However, the reset signal is entered regardless of the internal setup status. Table RES signal input level MPU type A E CS D to Active low Active high 68series 8series Data trafer The NT745 and NT745 drivers use the A, E(or ) and (or ) signals to trafer data between the system MPU and internal registers. The combinatio used are given in the table blow. In order to match the timing requirements of the MPU with those of the display data RAM and control registers all data is latched into and out of the driver. This introduces a one cycle delay between a read request for data and the data arriving. For example when the MPU executes a read cycle to access display RAM the current contents of the latch are placed on the system data bus while the desired contents of the display RAM are moved into the latch. This mea that a dummy read cycle has to be executed at the start of every series of reads. See Figure. No dummy cycle is required at the start of a series of writes as data is traferred automatically from the input latch to its destination. Common A 68 MPU 8 MPU Function Read display data Write display data Read status Write to internal register (command) NO.2 6/24

7 NT745 Figure Bus Buffer Delay Data trafer When the Busy flag is logical, the NT745 series is executing its internal operatio. Any command other than Status Read is rejected during this time. The Busy flag is output at pin by the Status Read command. If an appropriate cycle time (tcyc) is given, this flag needs not be checked at the beginning of each command and, therefore, the MPU processing capacity can greatly be enhanced. Display Start Line and Line Count Registers The contents of this register form a pointer to a line of data in display data RAM corresponding to the first line of the display (COM), and are set by the Display Start Line command. The contents of the display start line register are copied into the line count register at the start of every frame, that is on each edge of FR. The line count register is incremented by the CL clock once for every display line, thus generating a pointer to the current line of data, in display data RAM, being traferred to the segment driver circuits. Column Address Counter The column address counter is a 7bit preset table counter that supplies the column address for MPU access to the display data RAM. See figure 2. The counter is incremented by one every time the driver receives a Read or Write Display Data command. Addresses above 5H are invalid, and the counter will not increment past this value. The contents of the column address counter are set with the Set Column Address command. NO.2 7/24

8 NT745 Page Register The page resiter is a 2bit register that supplies the page address for MPU access to the display data RAM. See Figure 2. The contents of the page register are set by the Set Page Register command. Display Data RAM The display data RAM stores the LCD display data, on a bit per pixel basis. The relatiohip between display data, display address and the display is shown in Figure 2. Common Timing Generator Circuit Generates common timing signals and FR frame signals from the CL basic clock. The /6 or /32 duty (for NT745) can be selected by the Duty Select command. If the /32 duty is selected for the NT745 the /32 duty is provided by two chips coisting of the master and slave chips in the common multichip mode. NT745 Display Data Latch Circuit This latch stores one line of display data for use by the LCD driver interface circuitry. The output of this latch is controlled by the Display ON/OFF and Static Drive ON/OFF commands. LCD Driver Circuit The LCD driver circuitry generates the 84level signals used to drive the LCD panel, using output from the display data latch and the common timing generator circuitry. Display Timing Generator This circuit generates the internal display timing signal using the basic clock, CL, and the frame signals, FR. FR is used to generate the dual frame ACdrive wavefrom (type B drive) and to lock the line counter and common timing generator to the system frame rate. CL is used to lock the line counter to the system line scan rate. If a system uses both NT745s and NT745s they must have the same CL frequency rating. NO.2 8/24

9 NT745 Oscillator Circuit (NT745OA) A low powercoumption CR oscillator for adjusting the oscillation frequency using Rf oscillation resistor only. This circuit generates a display timing signal. Some of NT745 series models have a builtin oscillator and others use an external clock. This difference must be checked before use. Connect the Rf oscillation resistor as follows. To suppress the builtin oscillator circuit and drive the MPU using an external clock, the clock having the same phase as the OSC2of mater chip into OSC2 of the slave chip. MPU having a builtin oscillator * If the parasitic capacitance of this section increases, the oscillation frequency may shift to the lower frequency. Therefore, the Rf oscillation frequency must be reduced below the specified level. *2 A CMOS buffer is required if the oscillation circuit is connected to two or more slave MPU chips. Resst Cricuit Detects a rising or falling edge of an RES input and initializes the MPU during poweron. Initialization status. Display is off. 2. Display start line register is set to line. 3. Static drive is turned off. 4. Column address counter is set to address. 5. Page address register is set to page /32 duty NT745 is selected. 7. Forward ADC is selected (ADC command D is and ADC status flag is ). 8. Readmodifywrite is turned off. The input signal level at RES pin is seed, and an MPU interface mode is selected as shown on Table. For the 8series MPU, the RES input is passed through the inverter and the active high reset signal must be entered. For the 68series MPU, the active low reset signal must be entered. As shown for the MPU interface (reference example), the RES pin must be connected to the Reset pin and reset at the same time as the MPU initialization. If the MPU is not initialized by the use of RES pin during poweron, an unrecoverable MPU failure may occur. When the Reset command id issued, initialization. NO.2 9/24

10 NT745 Column address ADC SEG pin D = "" D = "" SEG F H 4E 4D 4C 4B 4A H ,, D D D D D D D D, D,=, Page address DATA Page Page Page2 Page D 4E 4F H A B C D E F A B C D E F Line address Figure 2 Display Data RAM Addressing NO.2 /24

11 NT745 /5 bias, /6 duty /6 bias, /32 duty FR COM COM SS COM SEG SEG COMSEG COMSEG Figure 4 LCD drive waveforms example NO.2 /24

12 NT745 COMMANDS Summary Command Display On/Off Display start line Set page address Set column (Segment) address Read status Write display data Read display data Select ADC Statis drive ON/OFF Select duty ReadModifyWrite End Reset Code A D D Busy / Display start address ( to 3) Page ( to 3) Column address ( to 79) ADC ON/OFF Reset / / / Function Tur display on or off. : ON, : OFF Specifies RAM line corresponding to top line of display. Sets display RAM page in page address register. Sets Display RAM column address in column address register. Reads the following status: BUSY : Busy : Ready ADC : CW output NO/OFF RESET : CCW output : Display off : Display on : Being reset : Nomal Writes data from data bus into display RAM. Reads data from display RAM onto data bus. :CW output, :CCW output Selects static driving operation. :Static frive, :Normal driving Selets LCD duty cycle :/32, :/6 Readmodifywrite ON Readmodifywrite OFF Software reset NO.2 2/25

13 NT745 Command Description Table 3 is the command table. The NT745 series identifies a data bus using a combination of A and ( or ) signals. As the MPU tralates a command in the internal timing only (independent from the external clock), its speed is very high. The busy check is usually not required. Display ON/OFF A D D D AEH,AFH This command tur the display on and off. D=: Display ON D=: Display OFF Display Start Line This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COM. The display area begi at the specified line address and continues in the line address increment direction. This area having the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command, the vertical smooth scrolling and paging can be used. A A4 A3 A2 D A D A CH to DFH This command loads the display start line register. See Figure 2. A4 A3 A2 A A Line Address : : 3 Set Page Address This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified. The display status is not changed even when the page address is changed. A D A D A B8H to BBH This command loads the page address register. See Figure 2. A A Page 2 3 NO.2 3/24

14 NT745 Set Column Address This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU continuously, the column address is incremented by each time it is accessed from the set address. Therefore, the MPU can access to data continuously. The column address stops to be incremented at address 8, and the page address is not changed continuously. A A6 A5 A4 A3 A2 D A D A H to 4FH This command loads the column address register. A6 A5 A4 A3 A2 A A Column Address : : 79 Read Status A D D BUSY ADC ON/OFF RESET Reading the command I/O register (A=) yields system status information. The busy bit indicates whether the driver will accept a command or not. Busy=: The driver is currently executing a command or is resetting. No new command will be accepted. Busy=: The driver will accept a new command. The ADC bit indicates the way column addresses are assigned to segment drivers. ADC=: Normal. Column address n segment driver n. ADC=: Inverted. Column address 79u segment driver u. The ON/OFF bit indicates the current status of the disply. It is the inverse of the polarity of the display ON/OFF command. ON/OFF=: Display OFF ON/OFF=: Display ON The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operation mode. RESET=: Currently executing reset command. RESET=: Normal operation Write Display Data A D D Write data NO.2 4/24

15 NT745 Read Display Data A D D Read data Reads 8bit of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data RAM location specified by the contents of the column address and page address registers and then increments the column address register. After loading a new address into the column address register one dummy read is required before valid data is obtained. Select ADC A D D D AH, AH This command selects the relatiohip between display data RAM column addresses and segment drivers. D=: SEG column address 4FH,...(inverted) D=: SEG column address H,...(normal) This command is provided to reduce restrictio on the placement of driver ICs and routing of traces during printed circuit board design. See Figure 2 for a table of segments and column addresses for the two values of D. Static Drive ON/OFF A D D D A4H, A5H Forces display on and all common outputs to be selected. D=: Static drive on D=: Static drive off Select Duty A D D D A8H, A9H This command sets the duty cycle of the LCD drive and is only valid for the NT745. It is invalid for the NT745 which performs passive operation. The duty cycle of the NT745 is determined by the externally generated FR signal. NT745 D=: /32 duty cycle D=: /6 duty cycle When using the NT745OA, (having a builtin oscillator) and the NT745OA continuously, set the duty as follows:l NT745OA /32 /6 NT745OA /32 /6 NO.2 5/24

16 NT745 ReadModifyWrite A This command defeats column address register autoincerment after data reads. The current conetents of the column address register are saved. This mode remai active until an End command is received. Operation wequence during cursor display When the End command is entered, the column address is returned to the one used during input of ReadModify Write command. This Function can reduce the load of MPU when data change is repeated at a specific display area (such as cursor blinking). * Any command other than Data Read or Write can be used in the ReadModifyWrite mode. However, the Column Address Set command cannot be used. D D EH End A D D EEH This command cancels readmodifywrite mode and restores the contents of the column address register to their value prior to the receipt of the ReadModifyWrite command. Column address NO.2 6/24

17 NT745 Reset A D D E2H This command clears the display start line register. and set page address register to 3 page. It does not affect the contents of the display data RAM. When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command connot be used itead of this Reset signal. Power Save (Combination command) The Power Save mode is selected if the static drive is turned ON when the display is OFF. The current coumption can be reduced to almost the static current level. In the Power Save mode: (a) The LCD drive is stopped, and the segment and common driver outputs are set to the level. (b) The external oscillation clock input is inhibited, and the OSC2 is set to the floating mode. (c) The display and operation modes are kept. The Power Save mode is released when the display is turned ON or when the static drive is turned OFF. If the LCD drive voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the Power Save signal. NT745 If the LCD drive power is generated by resistance division, the resistance and capacitance are determined by the LCD panel size. After the panel size has been determined, reduce the resistance to the level where the display quality is not affected and reduce the power coumption using the divider resistor. NO.2 7/24

18 NT745 SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Rating Unit ss 5,4,2,3 Supply voltage() Supply voltage(2) Supply voltage(3) Input voltage Output voltage Power dissipation Operating temperature Storage temperature Soldering temperature time at lead IN O PD Topr Tstg Tsol Notes:. All voltages are specified relative to =. 2. The following relation must be always hold Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional operation under these conditio is not implied. 4. Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to avoid thermally stressing the package during board assembly. Electrical Specificatio DC Characteristics Ta=2 to 75 deg. C, = unless stated otherwise Parameter Operating voltage() See note. Recommended Recommended Operating Allowable voltage(2) Allowable Allowable Highlevel input voltage Lowlevel input voltage Symbol ss 5,2 3,4 IHT IHC IHT IHC ILT ILC ILT ILC OHT OHC OHC2 Hightlevel output voltage OHT OHC OHC2 ss=3 ss=3 Condition ss=3 ss=3 IOH=3.mA IOH=2.mA IOH=2 A ss=3 ss=3 IOH=2mA IOH=2mA ss=3 IOH=2 A Min x5 5 ss+2..2xss.2xss.2xss ss ss ss ss ss+2.4 ss+2.4.2xss.2xss.2xss.2xss 8. to to to +.3 ss.3 to +.3 ss.3 to to to +5 26, Rating Typ. Max x5 ss+.8.8xss.85xss.8xss mw deg. C deg. C deg. C, sec Unit Applicable Pin ss 5 See note.,2 3,4 See note 2 & 3. See note 2 & 3. See note 2 & 3. See note 2 & 3. OSC2 See note 4 & 5. See note 4 & 5. OSC2 NO.2 8/24

19 NT745 DC Characteristics(Cont'd) Ta=2 to 75 deg. C, = unless stated otherwise Parameter Symbol Condition Min. Typ. Max. Unit Applicable Pin Lowlevel output voltage olt olc olc2 olt olc olc2 lol = 3.mA lol = 2.mA lol = 2 A ss = 3 ss = 3 ss = 3 lol = 2mA lol = 3mA lol = 5 A ss+.4 ss+.4.8xss.8xss.8xss.8xss OSC2 See note 4 & 5. See note 4 & 5. OSC2 Input leakage current ll.. A See note 6. Output leakage current ll A See note 7. LCD driver ON resistance RON Ta = 25deg. C 5 = 5. 5 = k SEG to 79, COM to 5, See note Static current dissipation IDDQ CS = CL =. A During display 5 = 5. fcl = 2kHz Rf = M fcl = 8kHz 4 25 A See note 2, 3 & 4. Dynamic current dissipation IDD() During display 5 = 5 ss = 3 fc = 2kHz L Rf=M 9 25 A See note 2 & 3. IDD(2) During access tycy = 2kHz ss = 3, Druing access tcyc = 2kHz A See note 8. Input leakage current CIN Ta = 25 deg. C, f = MHz pf All input pi Rf =.M 2% Oscillation frequency fosc ss =.5 Rf =.M 2% khz See note 9. ss = 3. Reset time tr. s RES See note 5. Notes:. Operation over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during CPU access. 2. A, D to, E(or ), (or ) and CS 3. CL, FR, M/S and RES 4. D to 5. FR 6. A, E (or ), (or ), CS, CL, M/S and RES NO.2 9/24

20 NT When D to and FR are high impedance. 8. During continual write access frequency. 9. See figure below for details. See figure below for details. For a voltage differential of. between input (,..., 4) and output (COM, SEG) pi. All voltages within specified operating voltage range. 2. NT745 and NT745 only. Does not include traient currents due to stray and panel capacitances. 3. NT745 only. Does not include traient currents due to stray and panel capacitances. 4. NT745 only. Does not include traient currents due to stray and panel capacitances. 5.tR (Rest time) represents the time from the RES signal edge to the completion of rest of the internal circuit. Therefore, the NT745 series enters the normal operation status after this tr. NO.2 2/24

21 NT745 AC Characteristics MPU Bs Read/Write I (infamily MPU) A,CS, D to (ITE) D to (READ) Ta=2 to 75 deg. C, ss=5. Parameter Address hold time Address setup time System cycle time Control pulsewidth Data setup time Date hold time access time Output disable time Rise and fall time Symbol tah8 taw8 tcyc8 tcc tds8 tdh8 tacc8 tch8 tr, tf % unless stated otherwise Condition CL=pF Rating Min. Max Unit Signal A, CS, Dto (ss=2.7 to 4.5, Ta=2 to +75 ) Parameter Address hold time Address setup time System cycle time Control pulsewidth Data setup time Date hold time access time Output disable time Rise and fall time Symbol tah8 taw8 tcyc8 tcc tds8 tdh8 tacc8 tch8 tr, tf Condition CL=pF Rating Min. Max Unit Signal A, CS, Dto NO.2 2/24

22 NT745 MPU Bs Read/Write II (68family MPU) E A,CS D to (ITE) D to (READ) Ta=2 to 75 deg. C, ss=5. % unless stated otherwise Parameter Symbol Condition Rating Min. Max. System cycle time Address setup time Address hold time Data setup time Data hold time tcyc6 taw6 tah6 tds6 tdh6 2 8 Output disable time toh6 6 CL=pF Access time tacc6 9 Enable Read tew pulsewidth Write 8 Rise and fall time tr, tf 5 Unit Signal A, CS, Dto E (ss=2.7 to 4.5, Ta=2 to +75 ) Parameter Symbol Condition Rating Min. Max. Unit System cycle time * Address setup time Address hold time Data setup time Data hold time tcyc6 taw6 tah6 tds6 tdh Output disable time toh6 2 2 CL=pF Access time tacc6 8 Enable Read 2 tew pulsewidth Write 6 Rise and fall time tr, tf 5 Notes:.tcyc6 is the cycle time of CS. E=H, not the cycle time of E. Signal A, CS, Dto NO.2 22/24 E

23 NT745 Display Control Signal Timing CL FR Input Ta=2 to 75 deg. C, ss=5. % unless stated otherwise Parameter Symbol Condition Rating Min. Typ. Lowlevel pulsewidth Highlevel pulsewidth Rise time Fall time FR delay time twlcl twhcl tr tf tdfr Max Unit s s n s n s s Signal CL FR ss=2.7 to 4.5, Ta=2 to +75 Parameter Lowlevel pulsewidth Highlevel pulsewidth Rise time Fall time FR delay time Symbol twlcl twhcl tr tf tdfr Condition Min Rating Typ Max Note: The listed input tdfr applies to the NT745 and NT745 in slave mode. Unit s s n s n s s Signal CL FR Output Ta=2 to 75 deg. C, ss=5. % unless stated otherwise Rating Parameter Symbol Condition Min. Typ. FR delary time tdfr CL=pF.2 Max..4 Unit s Signal FR ss=2.7 to 4.5, Ta=2 to +75 Parameter Symbol Condition Min. FR delary time tdfr CL=pF Rating Typ..4 Max..8 Unit s Signal FR Note: The listed input tdfr applies to the NT745 and NT745 in slave mode. NO.2 23/24

24 NT745 APPLICATION NOTES MPU Interface Configuration 8 Family MPU NT745AA NO.2 24/24

25 NT745 NO.2 PAD DIAGRAM X,Y(,) Chip size:336 x4865 Pad size:2 x 2 Unit: m

26 NT745 NO.2 PAD DIAGRAM(NT745) Pad No COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 SEG6 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG5 SEG5 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG4 SEG4 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG3 SEG3 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG Pad name X Y Pad No SEG2 SEG2 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG A OSC*/CS OSC2*/CL ss DB DB DB2 DB3 DB4 DB5 DB6 Db7 RES FR M/S 4 COM COM COM2 COM3 COM Pad name X Y

27 NT745 NO.2 PAD DIAGRAM(NT745) Pad No SEG7 SEG7 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG6 SEG6 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG5 SEG5 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG4 SEG4 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG3 SEG3 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG Pad name X Y Pad No SEG2 SEG2 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG A OSC*/CS OSC2*/CL ss DB DB DB2 DB3 DB4 DB5 DB6 Db7 RES FR SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG Pad name X Y With collaboration of