NT X 65 RAM-Map STN LCD Controller/Driver V0.02

Transcription

1 32 X 65 RAM-Map TN LCD Controller/Driver V.2

2 Revision History... 3 Features... 4 eneral Description... 4 Pad Configuration... 5 Block Diagram... 6 Pad Descriptions... 7 Functional Descriptions... 2 Commands Command Description Absolute Maximum Rating lectrical Characteristics Microprocessor Interface (for reference only) Bonding Diagram Package Information Ordering Information /7/8 2 Ver.2

3 Revision History NT7545 pecification Revision History Version Content Date. Origin Mar 27. Add OTP Programming Notice Add pad location and alignment mark location Add pad dimensions Jun 27.2 P.69~Correct pad pitch 9~92, 223~224 from 26 to 55 um P5~Change VIHC PC min from.7xvdd to.8xvdd P5~Change VILC PC max from.3xvdd to.2xvdd Jul 27 27/7/8 3 Ver.2

4 Features 32 x 65-dot graphics display LCD controller/driver for black/white TN LCD RAM capacity: 32 x 65 = 8,58 bits 8-bit parallel bus interface for both 88 and 68 series, 4-wire erial Peripheral Interface (PI) Direct RAM data display using the display data RAM. When RAM data bit is, it is not displayed. When RAM data bit is, it is displayed. (At normal display) Many command functions: Read/Write display data, display ON/OFF, Normal/Reverse display, page address set, display start line set, LCD bias set, electronic contrast controls, V voltage regulation internal resistor ratio set, read modify write, segment driver direction select, power save. Other command functions: Partial display, partial start line set, N-Line inversion. Power supply voltage: - VDD =.8 ~ 3.6 V (Digital, Interface Power Input Range) - VDD2 = 2.6 ~ 3.6 V (Pump Power Input Range) - VDD3 = 2.4 ~ 3.6 V (Analog Power Input Range) - VLCD(V-V2) = 4. ~ 4.2 V 3X / 4X / 5X on chip DC-DC converter On chip LCD driving voltage generator or external power supply selectable 64-step contrast adjuster and on chip voltage follower On chip oscillation and hardware reset OTP programming eneral Description The NT7545 is a single-chip LCD driver for dot-matrix liquid crystal displays, which is directly connectable to a microcomputer bus. It accepts 8-bit parallel or serial display data directly sent from a microcomputer and stores it in an on-chip display RAM. It generates an LCD drive signal independent of the microprocessor clock. The set of the on-chip display RAM of 65 x 32 bits and a one-to-one correspondence between LCD panel pixel dots and on-chip RAM bits permits implementation of displays with a high degree of freedom. The NT7545 contain 65 common output circuits and 32 segment output circuits, so that a single chip of NT7545 can make maximum 65 x 32 or 49 x 32 or 33 x 32 dots display with the pad option (DUTY, DUTY). No external operation clock is required for RAM read/write operations. Accordingly, this driver can be operated with a minimum current consumption and its on-board low-current-consumption liquid crystal power supply can implement a high-performance handy display system with minimum current consumption and the smallest LI configuration. 27/7/8 4 Ver.2

5 Pad Configuration 27/7/8 5 Ver.2

6 Block Diagram VDD, VDD3 V,V3 3 COM COM63 COM V V2,V3 (V) (V) (V2) (V3) (V4) egment driver Common driver COM hift register V V V2 V3 V4 Voltage Follower Display data latch VDD2 V2 Voltage Booster Output status selector circuit I/O buffer circuit 32*65 dot dispaly data RAM Line address decoder Line counter Initial display line register Column address decoder Page address register 8 bit column address counter Display timing generator circuit DUTY DUTY CL FR FR Bus holder Command decoder Bus holder Oscillator CL Microprocessor interface I/O buffer /C C2 () () C86 P/ / R D7 (I) D6 D5 D4 D3 D2 D D (CL) 27/7/8 6 Ver.2

7 Pad Descriptions Power upply Pad No. Designati on I/O Description 26~28 VDD upply Power supply input. These pads must be connected to each other. 32~35 VDD2 upply These are the power supply pads for the step-up voltage circuit for the LCD. These pads must be connected to each other. 29~3 VDD3 upply Power supply input. These pads must be connected to each other. 4,54 VDD_OPT O Power supply output for pad option 36~38 V upply round. These pads must be connected to each other. 42~45 V2 upply round. These pads must be connected to each other. 39~4 V3 upply round. These pads must be connected to each other. 7,24,57 V_OPT O round output for pad option. 3~4 OTP_PWR upply Power supply input for OTP cells. One Time Programming pin.this pad must be no connect when unused. 6 CP I H/W elect pump times 4x or 5x. (L=4x & H=5x). After H/W reset, the booster stage will be the setting value. 27/7/8 7 Ver.2

8 LCD Power upply Pad No. Designation I/O Description 5~53 VLCD (V) 46 V 47 V2 48 V3 49 V4 I/O LCD driver supplies voltages. The voltage determined by the LCD cell is impedance-converted by a resistive driver or an operation amplifier for application. Voltages should be according to the following relationship: V V V2 V3 V4 V2 When the on-chip operating power circuit is on, the following voltages are supplied to V to V4 by the on-chip power circuit. Voltage selection is performed by the LCD Bias et command. LCD bias V V2 V3 V4 /4 bias 3/4V 2/4V 2/4V /4V /5 bias 4/5V 3/5V 2/5V /5V /6 bias 5/6V 4/6V 2/6V /6V /7 bias 6/7V 5/7V 2/7V /7V /8 bias 7/8V 6/8V 2/8V /8V /9 bias 8/9V 7/9V 2/9V /9V Configuration Pad Pad No. Designation I/O Description DUTY DUTY I elect the maximum LCD driver duty DUTY DUTY LCD driver duty /33 /49 * /65 27/7/8 8 Ver.2

9 ystem Bus Connection Pad No. Designation I/O Description D D D2 D3 D4 D5 D6 (CL) D7 (I) I/O This is an 8-bit bi-directional data bus that connects to an 8-bit or 6-bit standard MPU data bus. When the serial interface is selected (P/= L ), then D7 serves as the serial data input terminal (I) and D6 serves as the serial clock input terminal (CL). When the serial interface is selected, fix D~D5 pads to VDD or V level. When the chip select is inactive, D to D7 are set to high impedance. I /R I /C C2 () () 56 C86 I I I I This is connected to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. = H : Indicate that D to D7 are display data = L : Indicates that D to D7 are control data When /R is set to L, the settings are initialized. The reset operation is performed by the /R signal level This is the chip select signal. When /C= L and C2= H, then the chip select becomes active, and data/command I/O is enabled. When connected to an 88 MPU, it is active LOW. This pad is connected to the signal of the 88MPU, and the NT7545 data bus is in an output status when this signal is L. When connected to a 68 eries MPU, this is active HIH. This is used as an enable clock input of the 68 series MPU When connected to an 88 MPU, this is active LOW. This terminal connects to the 88 MPU signal. The signals on the data bus are latched at the rising edge of the signal. When connected to a 68 eries MPU, this is the read/write control signal input terminal. When = H : Read When = L : Write This is the MPU interface switch terminal C86 = H : 68 eries MPU interface C86 = L : 88 eries MPU interface 27/7/8 9 Ver.2

10 ystem Bus Connection (continuous) Pad No. Designation I/O Description 58 P/ I This is the parallel data input/serial data input switch terminal P/ = H : Parallel data input P/ = L : erial data input The following applies depending on the P/ status: P/ Data/Command Data Read/Write erial Clock H D to D7, - L I (D7) Write only CL (D6) When P/ = L, fix D~D5 pads to VDD or V level. () and () are fixed to either H or L. With serial data input, RAM display data reading is not supported. 55 CL I Terminal to select whether enable or disable the display clock internal oscillator circuit. CL = H : Internal oscillator circuit for display is enabled CL = L : Use external oscillator circuit for display (requires external input) When CL = L, input the display clock through the CL pad. 5 CL I/O This is the display clock output/input terminal. When CL = H : the clock will be output terminal; and when CL= L : the display requires external input clock. FR O This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON, and is used in conjunction with the FR terminal. 2 FR O This is liquid crystal alternating current signal output terminal. 27/7/8 Ver.2

11 Liquid Crystal Drive Pads Pad No. Designation I/O Description 92~223-3 O egment signal output for LCD display. 59~9 224~255 COM3 COM32 63 O 9,256 COM O Common signal output for LCD display. When in master/slave mode, the same signal is output by both master and slave These are the COM output terminals for the indicator. Both terminals output the same signal. Do not connect these terminals if they are not used. When in master/slave mode, the same signal is output by both master and slave. 27/7/8 Ver.2

12 Functional Descriptions Microprocessor Interface Interface Type election The NT7545 can transfer data via 8-bit bi-directional data bus (D7 to D) or via serial data input (I). When high or low is selected for the parity of P/ pad either 8-bit parallel data input or serial data input can be selected as shown in Table. When serial data input is selected, the RAM data cannot be read out. Table P/ Type /C C2 C86 D7 D6 D to D5 H Parallel Input /C C2 C86 D7 D6 D to D5 L erial Input /C C I CL - - Must always be high or low Parallel Interface When the NT7545 selects parallel input (P/ = high), the 88 series microprocessor or 68 series microprocessor can be selected by causing the C86 pad to go high or low as shown in Table 2. Table 2 C86 Type /C C2 D to D7 H 68 microprocessor bus /C C2 D to D7 L 88 microprocessor bus /C C2 D to D7 Data Bus ignals The NT7545 identifies the data bus signal according to,, (, ) signals. Table 3 Common 68 processor 88 processor () Function Reads display data Writes display data Reads status Writes control data in internal register. (Command) 27/7/8 2 Ver.2

13 erial Interface When the serial interface has been selected (P/ = L ), then when the chip is in active state (/C = L and C2 = H ), the serial data input (I) and the serial clock input (CL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D, in this order. This data is converted to 8 bits of parallel data in the rising edge of eighth serial clock for processing. The input is used to determine whether or not the serial data input is display data, and when = L then the data is command data. The input is read and used for detection of every 8th rising edge of the serial clock after the chip becomes active. Figure is the serial interface signal chart. Figure C /C = L and C2 = H I D7 D6 D5 D4 D3 D2 D D D7 D6 D5 D4 CL Note:. When the chip is not active, the shift registers and the counters are reset to their initial states. 2. Reading is not possible while in serial interface mode. 3. Caution is required on the CL signal when it comes to line-end reflections and external noise. We recommend that the operation can be rechecked on the actual equipment. Chip elect Inputs The NT7545 has two chip-select pads. /C and C2 can interface to a microprocessor when /C is low and C2 is high. When these pads are set to any other combination. D to D7 are high impedance and, and inputs are disabled. When serial input interface is selected, the shift register and counter are reset. Access to Display Data RAM and Internal Registers The NT7545 can perform a series of pipeline processing between LI s using the bus holder of the internal data bus in order to match the operating frequency of display RAM and internal registers with the microprocessor. For example, the microprocessor reads data from display RAM in the first read (dummy) cycle, stores it in the bus holder, and outputs it onto the system bus in the next data read cycle. Also, the microprocessor temporarily stores display data in the bus holder, and stores it in display RAM until the next data write cycle starts. When viewed from the microprocessor, the NT7545 access speed greatly depends on the cycle time rather than access time to the display RAM (tacc). This view shows that the data transfer speed to / from the microprocessor can increase. If the cycle time is inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the immediately following read instruction. The address data is output during the second data read. A single dummy read must be inserted after address setup and after the write cycle (refer to Figure 2). 27/7/8 3 Ver.2

14 Figure 2 MPU DATA N N n n+ Address preset Internal timing Read signal Column address Preset Incremented N N+ N+2 BU holder N n n+ n+2 et address n Dummy read Data Read address n Data Read address n+ Busy Flag When the busy flag is it indicates that the NT7545 chip is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pad with the read instruction. If the cycle time (tcyc) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. Display Data RAM The display data RAM is RAM that stores the dot data for the display. It has a 65 (8 page * 8 bit+)*32 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display common direction, and there are few constraints at the time of display data transfer when multiple NT7545 chips are used, thus display structures can be created easily with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during the liquid crystal display, it will not cause adverse effects on the display (such as flickering). Figure 3 D D D2 D3 D4 COM COM COM2 COM3 COM4 Display data RAM Display on LCD 27/7/8 4 Ver.2

15 The Page Address Circuit As shown in Figure 4, page address of the display data RAM is specified through the Page Address et Command. The page address must be specified again when changing pages to perform access. Page address8 (D3, D2, D, D =,,,,) is the page for the RAM region used; only display data D is used. The Column Address As shown in Figure 4, the display data RAM column address is specified by the Column Address et command. The specified column address is incremented (+) with each display data read / write command. This allows the MPU display data to be accessed continuously. Moreover, the incrimination of column addresses stops with 83H, because the column address is independent of the page address. Thus, when moving, for example, from page column 83H to page column H, it is necessary to specify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. Table 4 Output 3 ADC (H) Column Address 83 (H) (ADC) 83 (H) Column Address (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified. This is the COM output when the common output mode is normal and the COM63 output for NT7545, when the common output mode is reversed. The display area is a 65-line area for the NT7545 from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The internal oscillator circuit is only enabled when CL = H. When CL = L the internal oscillation stops, and the input display clock is through the CL terminal. 27/7/8 5 Ver.2

16 Figure 4. Relationship between display data RAM and address. (if initial display line is DH) Page Address Data Line Address D D D2 2 D3, D2, D, D D3 3,,, D4 Page 4 D5 5 D6 6 D7 7 D 8 D 9 D2 A,,, D3 B Page D4 C D5 D D6 D7 F D D D2 2,,, D3 3 Page2 D4 4 D5 5 D6 6 D7 7 D 8 D 9 D2 A,,, D3 B Page3 D4 C D5 D D6 D7 F D 2 D 2 D2 22,,, D3 23 Page4 D4 24 D5 25 D6 26 D7 27 D 28 D 29 D2 2A,,, D3 2B Page5 D4 2C D5 2D D6 2 D7 2F D 3 D 3 D2 32,,, D3 33 Page6 D4 34 D5 35 D6 36 D7 37 D 38 D 39 D2 3A,,, D3 3B Page7 D4 3C D5 3D D6 3 D7 3F,,, D Page8 Column address ADC D= D= tart COM output COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM2 COM2 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM3 COM3 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM4 COM4 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM5 COM5 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM6 COM6 COM62 COM63 COM LCD OUT /7/8 6 Ver.2

17 Display Timing enerator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of access to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive waveform using a 2 frames alternating current drive method, as shown in Figure 5, for the liquid crystal drive circuit. Figure 5 CL FR COM V V V4 V V V COM V4 V RAM data V n V2 V3 V 27/7/8 7 Ver.2

18 Table 5 shows the relationship between oscillation frequency and frame frequency. foc can be selected as 3.4K or 26.3KHz by using Oscilliation Frequency elect command. Table 5 Duty Item fcl ffr /65 /49 /33 /7 /9 On-chip oscillator is used foc/6 fcl/(2 x 65) On-chip oscillator is not used xternal input fcl fcl/(2 x 65) On-chip oscillator is used foc/8 fcl/(2 x 49) On-chip oscillator is not used xternal input fcl fcl/(2 x 49) On-chip oscillator is used foc/2 fcl/(2 x 33) On-chip oscillator is not used xternal input fcl fcl/(2 x 33) On-chip oscillator is used foc/22 fcl/(2 x 7) On-chip oscillator is not used xternal input fcl fcl/(2 x 7) On-chip oscillator is used foc/44 fcl/(2 x 9) On-chip oscillator is not used xternal input fcl fcl/(2 x 9) Common Output Control Circuit This circuit controls the relationship between the number of common output and specified duty ratio. Common output mode select instruction specifies the scanning direction of the common output pads. Table 6 Duty tatus COM [-5] COM [6-23] COM [24-26] Common output pads COM [27-36] COM [37-39] COM [4-47] COM [48-63] COM Normal COM[-5] NC COM[6-3] /33 Reverse COM[3-6] NC COM[5-] COM Normal COM[-23] NC COM[24-47] /49 Reverse COM[47-24] NC COM[23-] COM Normal COM[-63] /65 COM Reverse COM[63-] The combination of the display data, the COM scanning signals, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows example of the and COM output waveform. Configuration etting The NT7545 has two optional configurations, configured by DUTY, DUTY. DUTY, DUTY Common egment V V2 V3 V4, or, /9V, 6/7V 7/9V, 5/7V 2/9V, 2/7 V /9V, /7V, /8V, 5/6V 6/8V, 4/6V 2/8V, 2/6 V /8V, /6V, /6V, 4/5V 4/6V, 3/5V 2/6 V, 2/5V /6V, /5V 27/7/8 8 Ver.2

19 Figure 6 FR VDD V COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 COM COM COM2 V V V2 V3 V4 V2 V V V2 V3 V4 V2 V V V2 V3 V4 V2 V V V2 V3 V4 V2 V V V2 V3 V4 V2 2 V V V2 V3 V4 V2 COM - COM - V V V2 V3 V4 V2 -V4 -V3 -V2 -V -V V V V2 V3 V4 V2 -V4 -V3 -V2 -V -V 27/7/8 9 Ver.2

20 The Power upply Circuit The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the booster circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control et command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control et Command 2-bit data control functions, and Table 8 shows reference combinations. Table 7 Item tatus D2 Voltage Booster (V/B) circuit control bit ON OFF D Voltage follower (V/F) circuit control bit ON OFF Use ettings Only the internal power supply is used D2 D Table 8 V/B Circuit V/F circuit xternal voltage input tep-up voltage system terminal ON ON VDD2 Used Only the V/F circuit is used OFF ON V, VDD2 Open Only the external power supply is used OFF OFF V to V4 Open *While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. 27/7/8 2 Ver.2

21 The Internal Pumping Voltage Using the step-up voltage circuits within the NT7545 chips it is possible to product 5X, 4X, 3X step-ups of the VDD2-V2 voltage levels by command (Ref 29. DC/DC Multiple et). The internal pumping voltage, please keep the relationship: Pumping Times * VDD2 > VLCD + Temperature Compensation Voltage. Figure 7 5 X VDD2 4 X VDD2 V 2 = V V 2 = V 5x step up voltage 4x step up voltage 3 X VDD2 V 2 = V 3x step up voltage The Voltage Regulator Circuit The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V. Because the NT7545 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Otherwise, NT7545 has temperature coefficient is.5%/ C. 27/7/8 2 Ver.2

22 When the V Voltage Regulator Internal Resistors Are Used Through the use of the V voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V voltage can be calculated using equation A- over the range where V < Pumping Times x VDD2. Rb Rb 63 α V ( ) VV ( ) ( ) VR (quation A-) Ra Ra 62 VR is the IC internal fixed voltage supply, and its voltage at Ta = 25 C is as shown in Table 9. Table 9 quipment Type Temp. coefficient Units VR Internal Power upply -.5 %/ C.4 α is set to level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table shows the value for α depending on the electronic volume register settings. Rb/Ra is the V voltage regulator internal resistor ratio, and can be set to 8 different levels through the V voltage regulator internal resistor ratio set command. The (+Rb/Ra) ratio assumes the values shown in Table depending on the 3-bit data settings in the V voltage regulator internal resistor ratio register. Table D5 D4 D3 D2 D D α V Minimum : 2 : : : : : 32 (default) : : : : 62 : 63 Maximum 27/7/8 22 Ver.2

23 V voltage regulator internal resistance ratio register value and (+ Rb/Ra) ratio (Reference value) Table Register quipment Type by Temp. Cofficient [Units:%/ C] D2 D D (default) The V voltage as a function of the V voltage regulator internal resistor ratio register and the electronic volumn register. Note: When selecting external Rb/Ra resistors, Ra+Rb shoud be greater than.5mω. Figure 8. The Contrast Curve of V Voltage with internal resistors 6 V (V) lectronic Volume (,,) 4.5 (,,) 5.25 (,,) 6 (,,) 6.75 (,,) 7.5 (,,) 8.25 (,,) 9 (,,) /7/8 23 Ver.2

24 etup example: When selecting Ta=25 C and V=7V for a NT7545 model on which the temperture compemsation is internal, using the equation A-, the following setup is enable. Table 2 Contents For V voltage regulator Register D5 D4 D3 D2 D D lectronic Volume When the V voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. The Liquid Crystal Voltage enerator Circuit The V voltage is produced by a resistive voltage divider within the IC, and can be produced at the V, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V, V2, V3, and V4 to the liquid crystal drive circuit. /9 bias or /7 bias for NT7545 can be selected when the duty is /65. (Other applications, pleasse refer the LCD Bias set). 27/7/8 24 Ver.2

25 Reset Circuit When the /R input falls to L, these LIs reenter their default state. The default settings are shown below:. Display OFF 2. Normal display 3. ADC select: Normal display (ADC command D = L ) 4. Power control register (D2, D, D) = (, *,,) 5. Register data clear in serial interface 6. LCD power supply bias ratio /9 (/65 duty), /8 (/49 duty), /6 (/33 duty) 7. DC/DC Multiple et (CP=L, 4X; CP=H,5x) 8. Read modify write OFF 9. tatic indicator: OFF tatic indicator register: (D, D2) = (, ). Display start line register set at first line. Column address counter set at address 2. Page address register set at page 3. Common output status normal 4. V voltage regulator internal power supply ratio set mode clear: V voltage regulator internal resistor ratio register: (D2, D, D) = (,, ) 5. lectronic volume register set mode clear lectronic volume register: (D5, D4, D3, D2, D, D) = (,,,,,,) 6. Test mode clear 7. Oscillation frequency 3.4 KHz 8. Normal display mode and frame inversion status (partial display and N-Line inversion release) 9. N-Line inversion register: (D4, D3, D2, D, D) = (,,,, ), 3-Line inversion 2. Partial start line register: (D5, D4, D3, D2, D, D) = (,,,,, ), the first line 2. Output condition of COM, COM: V : V On the other hand, when the reset command is used, only default settings 8 to 6 above are put into effect. The MPU interface (Reference xample), the /R terminal is connected to the MPU reset terminal, making the chip reinitialize simultaneously with the MPU. At the time of power up, it is necessary to reinitialize using the /R terminal. Moreover, when the control signal from the MPU is in a high impedance state, there may be an overcurrent condition; therefore, take measures to prevent the input terminal from entering a high impedance state. In the NT7545, if the internal liquid crystal power supply circuit is not used, user has to supply the external liquid crystal power after the procedure of RT has been finished (please refer to the timing chart of Reset). During the period of external liquid crystal power supply being supplied, the /R must be kept H. ven though the oscillator circuit operates while the /R terminal is L, the display timing generator circuit is stopped. 27/7/8 25 Ver.2

26 Commands The NT7545 uses a combination of, () and () signals to identify data bus signals. As the chip analyzes and executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its busy check is usually not required. The 88 series microprocessor interface enters a read status when a low pulse is input to the pad and a write status when a low pulse is input to the pad. The 68 series microprocessor interface enters a read status when a high pulse is input to the pad and a write status when a low pulse is input to this pad. When a high pulse is input to the pad, the command is activated. (For timing, see AC Characteristics.). Accordingly, in the command explanation and command table, () becomes (high) when the 68 series microprocessor interface reads status of display data. This is the only different point from the 88 series microprocessor interface. Taking the 88 series microprocessor interface as an example, commands are explained below. When the serial interface is selected, input data starting from D7 in sequence.. Display ON/OFF Alternatively turns the display on and off. D7 D6 D5 D4 D3 D2 D D Hex etting AFh Display ON Ah Display OFF When the display OFF command is executed when in the display all points ON mode, power save mode is entered. ee the section on the power saver for details. 2. Display tart Line et pecifies line address (refer to Figure 6) to determine the initial display line, or COM. The RAM display data becomes the top line of LCD screen. The higher number of lines in ascending order, corresponding to the duty cycle follows it. When this command changes the line address, smooth scrolling or a page change takes place. D7 D6 D5 D4 D3 D2 D D Hex A5 A4 A3 A2 A 4h to 7Fh A5 A4 A3 A2 A Line address 2 : : /7/8 26 Ver.2

27 3. Page Address et pecifies page address to load display RAM data to page address register. Any RAM data bit can be accessed when its page address and column address are specified. The display remains unchanged even when the page address is changed. Page address 8 is the display RAM area dedicated to the indicator, and only D is valid for data change. D7 D6 D5 D4 D3 D2 D D Hex A3 A2 A Bh to B8h A3 A2 A Page address 2 : : Column Address et pecifies column address of display RAM. Divide the column address into 4 higher bits and 4 lower bits. et each of them succession. When the microprocessor repeats to access the display RAM, the column address counter is incremental by during each access until address 32 is accessed. The page address is not changed during this time. D7 D6 D5 D4 D3 D2 D D Hex A7 A6 A5 A4 h to 8h High nibble A3 A2 A h to Fh Low nibble A7 A6 A5 A4 A3 A2 A Column address 2 : : /7/8 27 Ver.2

28 5. Read tatus D7 D6 D5 D4 D3 D2 D D BUY /ADC OFF/ON RT BUY: When high, the NT7545 is busy due to internal operation or reset. Any command is rejected until BUY goes low. The busy check is not required if enough time is provided for each cycle. /ADC: Indicates the relationship between RAM column address and segment drivers. When low, the display is reversed and column address 3-n corresponds to segment driver n. when high, the display is normal and column address corresponds to segment driver n. OFF/ON: Indicates whether the display is on or off. When low, the display turns on. When high, the display turns off. This is the opposite of Display ON/OFF command. RT: Indicates the initialization is in progress by /R signal or by reset command. When low, the display is on. When high, the chip is being reset. 6. Write Display Data Write 8-bit data in display RAM. As the column address automatically increments by after each write, the microprocessor can continue to write data of multiple words. D7 D6 D5 D4 D3 D2 D D Write Data 7. Read Display Data Reads 8-bit data from display RAM area specified by column address and page address. As the column address automatically increments by after each write, the microprocessor can continue to read data of multiple words. A single dummy read is required immediately after column address setup. Refer to the display RAM section of FUNCTIONAL DCRIPTION for details. Note that no display data can be read via the serial interface. D7 D6 D5 D4 D3 D2 D D Read Data 8. ADC elect Changes the relationship between RAM column address and segment driver. The order of segment driver output pads could be reversed by software. This allows flexible IC layout during LCD module assembly. For details, refer to the column address section of Figure 4. When display data is written or read, the column address is incremented by as shown in Figure 4. D7 D6 D5 D4 D3 D2 D D Hex etting h Normal Ah Reverse 27/7/8 28 Ver.2

29 9. Normal/ Reverse Display Reverses the Display ON/OFF status without rewriting the contents of the display data RAM. D7 D6 D5 D4 D3 D2 D D Hex etting A6h A7h RAM Data H LCD ON voltage (normal) RAM Data L LCD ON voltage (reverse). ntire Display ON Forcibly turns the entire display on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This command has priority over the Normal/Reverse Display command. When D is low, the normal display status is provided. D7 D6 D5 D4 D3 D2 D D Hex etting A4h Normal display mode A5h Display all points ON When D is high, the entire display ON status is provided. If the ntire Display ON command is executed in the display OFF status, the LCD panel enters Power save mode. Refer to the Power ave section for details.. LCD Bias et This command selects the voltage bias ratio required for the liquid crystal display. Duty D7 D6 D5 D4 D3 D2 D D Hex /33 /49 /65 A2h /6 bias /8 bias /9 bias A3h /5 bias /6 bias /7 bias 2. Read-Modify-Write A pair of Read-Modify-Write and nd commands must always be used. Once Read-Modify-Write is issued, column address is not incremental by Read Display Data command but incremental by Write Display Data command only. It continues until nd command is issued. When the nd is issued, column address returns to the address when Read-Modify-Write is issued. This can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or other events. D7 D6 D5 D4 D3 D2 D D Hex h Note: Any command except Read/Write Display Data and Column Address et can be issued during Read-Modify-Write mode. 27/7/8 29 Ver.2

30 Cursor display sequence et Page Address et Column Address Read-Modify-Write No Dummy Read Read Data Write Data Data process Completed? Yes nd 3. nd Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write is issued) D7 D6 D5 D4 D3 D2 D D Hex h Column address N N+ N+2 N+3 N+m N Return Read-Modify-Write mode is selected nd 27/7/8 3 Ver.2

31 4. Reset This command resets the Display tart Line register, Column Address counter, Page Address register, and Common output mode register, the V voltage regulator internal resistor ratio register, the lectronic Volume register, the static indicator mode register, the read-modify-write mode register, and the test mode. The Reset command does not affect on the contents of display RAM. Refer to the Reset circuit section of Function Description. D7 D6 D5 D4 D3 D2 D D Hex 2h The Reset command cannot initialize LCD power supply. Only the Reset signal to the /R pad can initialize the supplies. 5. Output tatus elect Register When D3 is high or low, the scan direction of the COM output pad is selectable. Refer to Output tatus elector Circuit in Function Description for details. D7 D6 D5 D4 D3 D2 D D Hex * * * Ch to C7h *: Invalid bit D3 = : Normal (COM COM63/47/3) D3 = : Reverse (COM63/47/3 COM) C8h to CFh 6. Power Control et elect one of eight power circuit functions using 3-bit register. An external power supply and part of on-chip power circuit can be used simultaneously. Refer to Power upply Circuit section of FUNCTIONAL DCRIPTION for details. D7 D6 D5 D4 D3 D2 D D Hex A2 * 28h to 2Fh When goes low, voltage follower turns off. When goes high, it turns on. When A2 goes low, voltage booster turns off. When A2 goes high, it turns on. When A2, go low, both voltage booster and follower turn off, and external power is needed. 27/7/8 3 Ver.2

32 7. V Voltage Regulator Internal Resistor Ratio et This command sets the V voltage regulator internal resistor ratio. For details, see explanation under The Power upply Circuits. D7 D6 D5 D4 D3 D2 D D Hex Rb/Ra Ratio 2h mall 2h 22h : : : 26h 27h Large 8. The lectronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V through the output from the voltage regulator circuits of the internal liquid crystal power supply. It is a two-byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. () The lectronic Volume Mode et When this command is input, the electronic volume register set command is enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. D7 D6 D5 D4 D3 D2 D D Hex 8h (2) lectronic Volume Register et By using this command to set six bits of data to the electronic volume register, the liquid crystal voltage V assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. D7 D6 D5 D4 D3 D2 D D Hex V * * XX mall XX : : : XX XX Large When the electronic volume function is not used, set D5 - D to. 27/7/8 32 Ver.2

33 9. tatic Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FR terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double bytes command paired with the static indicator register set command, and thus command must be executed one after the other. (The static indicator OFF command is a single byte command) () tatic Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. D7 D6 D5 D4 D3 D2 D D Hex etting ACh tatic Indicator OFF ADh tatic Indicator ON (2) tatic Indicator Register et This command sets two bits of data into the static indicator register and used to set the static indicator into a blinking mode. D7 D6 D5 D4 D3 D2 D D Hex Indicator Display tatus * * * * * * XX OFF XX XX ON (blinking at approximately second intervals) ON (blinking at approximately.5 second intervals) XX ON (constantly on) 27/7/8 33 Ver.2

34 2. Power ave (Compound Command) When all displays are turned on during display off, the Power ave command is issued to greatly reduce current consumption. If the static indicator is off, the Power ave command makes the system enter sleep mode. If the static indicator is on, this command makes the system enter standby mode. Release the leep mode using the both Power ave OFF command (Display ON command or ntire Display OFF command) and et Indicator On command. tatic Indicator OFF tatic Indicator ON Power ave (Display OFF and ntire Display ON) (leep mode) (tandby mode) Power ave OFF (Display ON or ntire Displays OFF ) tatic Indicator ON (leep mode released) (tandby mode released) leep Mode This mode stops every operation of the LCD display system, and can reduce current consumption nearly to a static current value if no access is made from the microprocessor. The internal status in the sleep mode is as follows: () tops the oscillator circuit and LCD power supply circuit. (2) tops the LCD driver and outputs the V level as the segment/common driver output. (3) Holds the display data and operation mode provided before the start of the sleep mode. (4) The MPU can access the built-in display data RAM. tandby Mode tops the operation of the duty LCD displays system and turns on only the static drive system to reduce current consumption to the minimum level required for static drive. The ON operation of the static drive system indicates that the NT7545 is in standby mode. The internal status in the standby mode is as follows: () tops the LCD power supply circuit. (2) tops the LCD drive and outputs the V level as the segment / common driver output. However, the static drive system still operates. (3) Holds the display data and operation mode provided before the start of the standby mode. (4) The MPU can access the built-in display data RAM. When the Reset command is issued in the standby mode, the sleep mode is set. When the LCD drive voltage level is given by an external resistive driver, the current of this resistor must be cut so that it may be fixed to floating or V level, prior to or concurrently with causing the NT7545 to go to the sleep mode or standby mode. When an external power supply is used, likewise, the function of this external power supply must be stopped so that it may be fixed to floating or V level, prior to or concurrently with causing the NT7545 to go to the sleep mode or standby mode. 27/7/8 34 Ver.2

35 2. NOP Non-Operation Command. D7 D6 D5 D4 D3 D2 D D Hex 3h 22. Oscillation Frequency elect This command is to select the oscillation frequency of driver IC as below. D7 D6 D5 D4 D3 D2 D D Hex Oscillation Frequency 4h Typical 3.4 KHz 5h Typical 26.3 KHz 23. Partial Display Mode et This command enables to select the display mode. When D is low, the IC is in normal display mode, the maximum display duty ratio is decided by pin connection of DUTY and DUTY and the command LCD Bias et decides the LCD bias ratio. The IC enters into partial display mode when D is high, then the commands Partial Display Duty et and Partial Display Bias et decide the LCD display duty and bias ratios. D7 D6 D5 D4 D3 D2 D D Hex Display Mode 82h Normal Display 83h Partial Display 27/7/8 35 Ver.2

36 24. Partial Display Duty and Bias et These two commands set the LCD display duty and bias ratios when the IC is in partial display mode. They are invalid when the IC is in normal display mode. When the partial display duty is set, the LCD bias for partial display is set simultaneous as below. The partial display duty will be kept at maximum duty (decided by pins DUTY and DUTY) when setting duty is larger than maximum duty. D7 D6 D5 D4 D3 D2 D D Hex Partial Duty canning Line 3h /9 duty Line [:7], COM 3h /7 duty Line [:5], COM 32h /33 duty Line [:3], COM 33h /49 duty Line [:47], COM 34h /65 duty Line [:63], COM * 35h 37h Reserved No effect Using Partial Display Bias et command to change the LCD bias in partial display mode. D7 D6 D5 D4 D3 D2 D D Hex LCD Bias 38h /4 39h /5 3Ah /6 3Bh /7 3Ch /8 3Dh /9 3h Reserved 3Fh Reserved Note: The COM waveform of no display area is non-select waveform. 27/7/8 36 Ver.2

37 25. Partial tart Line et (Double Byte Command) This command makes it possible to set the partial start line for partial display. It is a two-byte command used as a pair and the Number of tart Line et command must be issued after the Partial tart Line et command. () Partial tart Line et When this command is input, no other command except for the Number of tart Line et command can be used. D7 D6 D5 D4 D3 D2 D D Hex D3h (2) Number of tart Line et By using this command to set six bits of data to the Partial tart Line register. Once the Number of the tart Line et command has been used to set data into the register, then the partial start line will affect on the LCD display. The number of partial start line is always equal to zero when the partial start line is larger than maximum duty ratio (decided by pins DUTY and DUTY). D7 D6 D5 D4 D3 D2 D D Hex Partial tart Line * * XX line XX line XX 2 line : : : XX 62 line XX 63 line 27/7/8 37 Ver.2

38 26. The N-Line Inversion (Double Byte Command) This command makes it possible to adjust the number of scan lines for liquid crystal display inversion. It is a two-byte command used as a pair and the Number of Line et command must be issued after the N-Line Inversion et command. () N-Line Inversion et When this command is input, no other command except for the Number of Line et command can be used. D7 D6 D5 D4 D3 D2 D D Hex 85h (2) Number of Line et By using this command to set five bits of data to the N-Line inversion register. Once the Number of Line et command has been used to set the data into the register, then the N-Line inversion will affect on the LCD display. D7 D6 D5 D4 D3 D2 D D Hex Line Inversion * * * XX line XX 2 line : : : XX 32 line Note : The number of inversed scan line = register setting value +. Note 2: When Partial Duty = /9 or /7, the N-line inversion function release and the LCD display scan line is back to frame inversion status m Frame Inversion M n n N-line Inversion M' 27. Release N-Line Inversion This command is used to exit the N-Line inversion function. The N-Line inversion function is released and the LCD display is set back to frame inversion status once this command is executed. D7 D6 D5 D4 D3 D2 D D Hex 84h 27/7/8 38 Ver.2

39 29. elect DC-DC et-up (Double Byte Command) This command makes it possible to set up the DC/DC multiple factors. By using this command to select 4 types of DC/DC multiple factors. After H/W reset, the DC-DC set-up will be the CP setting value. D7 D6 D5 D4 D3 D2 D D Hex 89h * * * * * * DC[:] XX D7 D6 D5 D4 D3 D2 DC[:] Hex elect DC-DC converter circuit * * * * * * h 5 times boosting circuit * * * * * * h 4 times boosting circuit * * * * * * 2h 3 times boosting circuit * * * * * * 3h 3 times boosting circuit 3. One Time Programming et (Double Byte Command) This command can enable and execute OTP programming. OTP_N= nable OTP OTP_P= Programming OTP D7 D6 D5 D4 D3 D2 D D Hex DFh * * * * * * OTP_P OTP_N Xx Note: An ffective One Time Programming is OTP_N= and OTP_P=. 27/7/8 39 Ver.2

40 3. lectronic Volume Calibration (Double Bytes Command) This command makes it possible to calibrate the contrast value of the liquid crystal display by setting the electronic volume calibration register. Because the variation of LCD module in term of contrast level, the calibration function can be used to achieve the best visual contrast of every LCD module by adjusting VLCD (V) voltage. By using this command to set 4 bits of data to the electronic volume calibration register; the V offset value assumes one of the +/- 7 steps. D7 D6 D5 D4 D3 D2 D D Hex D2h * * * * OTP [3:] XX OTP [3:] Hex Calibration Value 7h 6h 5h 4h 3h 2h h h 8h 9h Ah Bh Ch Dh h Fh +7 tep +6 tep +5 tep +4 tep +3 tep +2 tep + tep tep(default) tep - tep -2 tep -3 tep -4 tep -5 tep -6 tep -7 tep 27/7/8 4 Ver.2

41 32. Test Command This is the dedicated IC chip test command. It must not be used for normal operation. If the Test command is issued inadvertently, set the /R input to low or issue the Reset command to release the test mode. D7 D6 D5 D4 D3 D2 D D Hex Fh to FFh *: Invalid bit Cautions: The NT7545 maintains an operation status specified by each command. However, the internal operation status may be changed by a high level of ambient noise. Users must consider how to suppress noise on the package and system or to prevent ambient noise insertion. To prevent a spike in noise, built-in software for periodical status refreshment is recommended. The test command can be inserted in an unexpected place. Therefore it is recommended to enter the test mode reset command Fh during the refresh sequence. 27/7/8 4 Ver.2

42 One Time Programming Notice. One Time Programming teps: tep Instruction Action Note H/W Reset et /R H/W reset sequence. 2 Initialization et initial 3 nable One Time Programming(OTP) 4 Judge contrast 5 Adjust V by OTP 6 Connect OTP Power et OTP_N= By judging the contrast with golden sample is the same or not et parameters to adjust contrast as golden sample Connect an external voltage to OTP_PWR pin end the original initialization settings to display properly (fix a specified electronic volume) et double byte command(dfh&h) et golden test patterns to judge the contrast is best or not by vision et double byte command (D2h&Xx) and adjust the electronic volume value by One Time Programming et command (OTP [3:]), until there is the best visual contrast. OTP_PWR = 7.5V 7 xecute One Time Programming(OTP) Program OTP cells, and set OTP_P= et double byte command(dfh&3h) 8 -- Wait 2s -- 9 Disable One Time Programming(OTP) xit OTP Programming et OTP_N= & OTP_P= et double byte command(dfh&h) -- Open OTP_PWR OTP_PWR = Floating H/W reset et /R H/W reset sequence. 2 nd Wait 5ms -- 27/7/8 42 Ver.2

43 2. One Time Programming Flow Chart tart tep Connect an external voltage(7.5v) to OTP_PWR Pin Hardware reset Initialization tep 2 tep 7 Programming OTP OTP_P= " tep 3 tep 8 nable OTP. Judge contrast 2. Adjust V by OTP tep 4~5 Wait 2s tep 9 Disable One Time Programming Command OTP_N= & OTP_P= tep ~ Accept Parameters No. Open external voltage 2. Hardware reset tep 2 Yes tep 6 nd 27/7/8 43 Ver.2

44 Table3. Command Table Command Code D7 D6 D5 D4 D3 D2 D D Hex () Display OFF (2) Display tart Line et Display tart Address (3) Page Address et Page Address (4) Column Address et Higher Column Address Lower Column Address Function NT7545 Ah Turn on LCD panel when high, and AFh turn off when low 4h to 7Fh Bh to B8h h to 8h pecifies RAM display line for COM et the display data RAM page in Page Address register et 4 higher bits and 4 lower bits of column address of display data RAM in register (5) Read tatus tatus XX Reads the status information (6) Write Display Data Write Data XX Write data in display data RAM (7) Read Display Data Read Data XX Read data from display data RAM (8) ADC elect (9) Normal/Reverse Display () ntire Display ON/OFF () LCD Bias et (2) Read-Modify-Write h h Ah A6h A7h A4h A5h A2h A3h et the display data RAM address output correspondence Normal indication when low, but full indication when high elect normal display () or entire display on ets LCD driving voltage bias ratio Increments column address counter during each write (3) nd h Releases the Read-Modify-Write (4) Reset 2h Resets internal functions (5) Common Output Mode elect * * * (6) Power Control et Operation tatus (7) V Voltage Regulator Internal Resistor ratio et Resistor Ratio (8) lectronic Volume 8h mode et lectronic Volume Register et * * lectronic Control Value XX (9) et tatic indicator ON/OFF et tatic Indicator Register Ch elect COM output scan direction to *: invalid data CFh 28h to 2Fh 2h to 27h * * * * * * Mode XX (2) Power ave elect the power circuit operation mode elect internal resistor ratio Rb/Ra mode ets the V output voltage electronic volume register ACh ets static indicator ON/OFF ADh : OFF, : ON ets the flash mode Compound command of Display OFF and ntire Display ON (2) NOP 3h Command for non-operation 27/7/8 44 Ver.2

45 Command (22)Oscillation Frequency elect (23)Partial Display mode et Command Table (continue) Code D7 D6 D5 D4 D3 D2 D D Hex (24)Partial Display Duty et Duty Ratio (25)Partial Display Bias et Bias Ratio (26)Partial tart Line et 4h 5h 82h 83h 3h 37h 38h 3Fh Function NT7545 elect the oscillation frequency nter/release the partial display mode ets the LCD duty ratio for partial display mode ets the LCD bias ratio for partial display mode nter Partial tart Line et D3h Partial tart Line et Partial tart Line XX (27)N-Line Inversion et Number of Line et (28)N-Line Inversion Release (29)DC/DC Multiple et 85h * * * Number of Line XX 84h 89h * * * * * * DC[:] XX ets the LCD Number of partial display start line nter N-Line inversion ets the number of line used for N-Line inversion xit N-Line Inversion elect the step-up of the internal voltage converter DFh nable and Programming OTP (3)One Time Programming set * * * * * * (3)lectronic Volume D2h Calibration * * * * OTP [3:] XX (32)Test Command * * * * OTP_ P OTP_ N XX Fh to FFh et V output voltage electronic volume for calibration(one Time programming) IC test command. Do not use! (33)Test Mode Reset Fh Command of test mode reset Note: Do not use any other command, or system malfunction may result. 27/7/8 45 Ver.2

46 Command Description Instruction etup: Reference. Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 ( pin) and V and V4 (COM pin) are output through the LCD driving output pins and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V - V4) and the VDD pin, the picture on the display may instantaneously become totally dark when the power is turned on. To avoid such failure, we recommend the following flow sequence when turning on the power... When the built-in power is being used immediately after turning on the power: 27/7/8 46 Ver.2

47 .2. When the built-in power is not being used immediately after turning on the power Turn ON the VDD - V power keeping the /R pin = "L" When the power is stabilized Release the reset state. (/R pin = "H") Initialized state (Default) Power saver TART (multiple commands) Function setup by command input (User setup) () LCD bias setting (8) ADC selection (5) Common output state selection Function setup by command input (User setup) (7) etting the built-in resistance radio for regulation of the V voltage (8) lectronic volume control Power saver OFF Function setup by command input (User setup) (6) Power control setting This concludes the initialization 27/7/8 47 Ver.2

48 2. Data Display nd of initialization Function setup by command input (User setup) (2) Display start line set (3) Page address set (4) column address set Function setup by command input (user setup) (6) Display data write Function setup by command input (User setup) () Display ON/OFF nd of data display 3. Power OFF Optional status Function setup by command input (User setup) (2) Power save VDD-V power OFF 27/7/8 48 Ver.2

49 Absolute Maximum Rating DC upply Voltage (VDD, VDD2, VDD3) V to +4.V DC upply Voltage (V) -.3V to +5.V Input Voltage (Vin).. -.3V to VDD+.3V Operating Ambient Temperature -4 C to +85 C torage Temperature -55 C to +25 C *Comments tresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. xposure to the absolute maximum rating conditions for extended periods may affect device reliability. lectrical Characteristics DC Characteristics (V = V, VDD =.8 ~ 3.6V, Ta = -4 ~ +85 C unless otherwise specified) ymbol Parameter Min. Typ. Max. Unit Condition VDD Operating Voltage V VDD3 Operating Voltage V VDD2 Operating Voltage V 3X~ 5X boosting V Voltage Regulator Operating Voltage V VR Reference Voltage V Ta = 25 C, -.5%/ C μa VDD = 3V, V = 9V, built-in boosting power supply off, display on, display data = checker and no access, Ta = 25 C IDD Current Consumption μa VDD, VDD2, VDD3 = 3V, V = 9V, 5X built-in boosting power supply, display on, display data = checker and no access, temperature coefficient is -.5%/ C, Ta = 25 C. 27/7/8 49 Ver.2

50 DC Characteristics (continued) ymbol Parameter Min. Typ. Max. Unit Condition IP IB VIHC VILC VOHC VOLC ILI leep Mode Current Consumption tandby Mode Current Consumption High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low -Level Output Voltage Input Leakage Current -. 5 μa During sleep, Ta = 25 C μa During standby, Ta = 25 C.8 x VDD V -.8 x VDD V - - VDD V.2 x VDD V NT7545, D - D7, (), (), /C, C2, CL, CL, FR, C86, P/, /R and CP - VDD V IOH = -.5mA (D - D7, FR, FR and CL).2 x VDD V μa IHZ HZ Leakage Current μa RON RON2 LCD Driver ON Resistance LCD Driver ON Resistance KΩ V =.V KΩ V = 8.V IOL =.5mA (D - D7, FR, FR and CL) Vin = VDD or V (, (), (), /C, C2, CL, M/, C86, P/ and /R) When the D - D7, FR and CL are in high impedance Ta = 25 C, These are the resistance values for when a.v voltage is applied between the output terminals n or COMn and the various power supply terminal (V, V, V2, V3, V4) CIN Input Pad Capacity pf Ta = 25 C, f = MHz foc = 3.4 KHz, /65duty Hz VDD =.8~3.6V ffrm Frame Frequency foc = 26.3 KHz, /65duty Hz VDD =.8~3.6V Notes:. Voltages V V V2 V3 V4 V2 must always be satisfied. 27/7/8 5 Ver.2

51 AC Characteristics. ystem Buses Read/Write Characteristics (for 88 eries MPU) /C (C2) ta8 tah8 tcyc8, D~D7 (Write) D~D7 (Read) tacc8 tcclw, tcclr td8 tdh8 tcchw, tcchr tch8 (VDD = 2.7 ~ 3.6V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition TAH8 Address hold time - - ns TA8 Address setup time - - ns tcyc8 ystem cycle time ns tcclw Control low pulse width (write) ns tcclr Control low pulse width (read) ns tcchw Control high pulse width (write) ns tcchr Control high pulse width (read) ns TD8 Data setup time ns TDH8 Data hold time - - ns D~D7 tacc8 access time ns TCH8 Output disable time 5-5 ns D~D7, CL = pf 27/7/8 5 Ver.2

52 ystem Buses Read/Write Characteristics (for 88 eries MPU) (continued) (VDD =.8 ~ 2.7V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tah8 Address hold time - - ns ta8 Address setup time - - ns tcyc8 ystem cycle time ns tcclw Control low pulse width (write) ns tcclr Control low pulse width (read) ns tcchw Control high pulse width (write) ns tcchr Control high pulse width (read) ns td8 Data setup time ns tdh8 Data hold time - - ns tacc8 access time ns tch8 Output disable time - ns D~D7 D~D7, CL = pf *. The input signal rise time and fall time (tr, tf) is specified at 5ns or less. (tr + tf) < (tcyc8 - tcclw - tcchw) for write, (tr + tf) < (tcyc8 - tcclr - tcchr) for read. *2. All timing is specified using 2% and 8% of VDD as the reference. *3. tcclw and tcclr are specified as the overlap interval when /C is low (C2 is high) and or is low. 27/7/8 52 Ver.2

53 2. ystem Buses Read/Write Characteristics (for 68 eries MPU), /C (C2) ta6 tah6 tcyc6 twhw, twhr twlw, twlr D~D7 (Write) D~D7 (Read) tacc6 td6 tdh6 toh6 (VDD = 2.7 ~ 3.6V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tah6 Address hold time - - ns ta6 Address setup time - - ns tcyc6 ystem cycle time ns twhw Control high pulse width (write) ns twhr Control high pulse width (read) ns twlw Control low pulse width (write) ns twlr Control low pulse width (read) ns td6 Data setup time ns tdh6 Data hold time - - ns tacc6 access time ns toh6 Output disable time 5-5 ns, D~D7 D~D7 CL = pf 27/7/8 53 Ver.2

54 ystem Buses Read/Write Characteristics (for 68 eries MPU) (continued) (VDD =.8 ~ 2.7V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tah6 Address hold time - - ns ta6 Address setup time - - ns tcyc6 ystem cycle time ns twhw Control high pulse width (write) ns twhr Control high pulse width (read) ns twlw Control low pulse width (write) ns twlr Control low pulse width (read) ns td6 Data setup time ns tdh6 Data hold time - - ns tacc6 access time ns toh6 Output disable time - ns, D~D7 D~D7 CL = pf *. The input signal rise time and fall time (tr, tf) is specified at 5ns or less. (tr + tf) < (tcyc6 - twlw - twhw) for write, (tr + tf) < (tcyc6 - twlr - twhr) for read. *2. All timing is specified using 2% and 8% of VDD as the reference. *3. twhw and twhr are specified as the overlap interval when /C is low (C2 is high) and is high. 27/7/8 54 Ver.2

55 3. erial Interface Timing /C (C2) tc tcyc tch tr thw tlw CL tf ta tah td tdh I (VDD = 2.7 ~ 3.6V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tcyc erial clock cycle ns CL thw erial clock H pulse width ns CL tlw erial clock L pulse width ns CL ta Address setup time ns tah Address hold time - - ns td Data setup time ns I tdh Data hold time - - ns I tc Chip select setup time ns /C, C2 tch Chip select hold time ns /C, C2 27/7/8 55 Ver.2

56 erial Interface Timing (continued) (VDD =.8 ~ 2.7V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tcyc erial clock cycle ns CL thw erial clock H pulse width ns CL tlw erial clock L pulse width ns CL ta Address setup time ns tah Address hold time ns td Data setup time ns I tdh Data hold time ns I tc Chip select setup time ns /C, C2 tch Chip select hold time - - ns /C, C2 *. The input signal rise time and fall time (tr, tf) is specified as 5ns or less. *2. All timing is specified using 2% and 8% of VDD as the standard. 27/7/8 56 Ver.2

57 4. Display Control Timing CL (Output) tdfr FR (VDD = 2.7 ~ 3.6V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tdfr FR delay time ns CL = 5 pf (VDD =.8 ~ 2.7V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tdfr FR delay time ns CL = 5 pf 5. Reset Timing trw tr /R Internal tatus During Reset (VDD = 2.7 ~ 3.6V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tr Reset Time - -. μs trw Reset low pulse width - - μs /R (VDD =.8 ~ 2.7V, Ta = -4 ~ +85 C) ymbol Parameter Min. Typ. Max. Unit Condition tr Reset Time μs trw Reset low pulse width μs /R 27/7/8 57 Ver.2

58 Microprocessor Interface (for reference only) 88-series microprocessors V DD V CC V DD A to A7 /IORQ Decoder /C C2 C86 MPU NT7545 D to D7 D to D7 V V DD /R /R P/ ND V V Figure 9 68-series microprocessors Figure 27/7/8 58 Ver.2

59 27/7/8 59 Ver.2 Application information for LCD panel (for reference only). Type I (ADC elect =, COM Output elect = ) COM COM2 COM3 COM44 COM45 COM IC Bumper Face Down C O M C O M C O M C O M 4 C O M 3 2 C O M COM63 2. Type II (ADC elect =, COM Output elect = ) IC Bumper Face Down COM44 COM45 COM3 C O M 3 C O M 3 C O M 4 3 C O M C O M C O M COM2 COM COM63 COM

60 27/7/8 6 Ver.2 3. Type III (ADC elect =, COM Output elect = ) COM44 COM45 COM63 COM COM2 COM IC Bumper Face Up 2 C O M 3 C O M 3 C O M 4 3 C O M C O M C O M COM 4. Type IV (ADC elect =, COM Output elect = ) IC Bumper Face Up COM COM2 COM3 COM C O M C O M C O M C O M 4 C O M 3 2 C O M COM45 COM44 COM

61 Application information for Pin Connection to MPU (for reference only). 88 MPU Mode: (DUTY, = : /65duty, CP= : 4x, CL = : Internal display OC) NT7545 COM63 COM COM48 COM49 COM47 COM46 OTP_PWR FR FR OTP_PWR /C /R CL CP V_OPT /C C2 /R COM34 COM33 COM D[..7] D D D2 D3 D4 D5 D6 D7 DUTY DUTY VDD VDD VDD3 VDD2 V C V V3 V2 V V2 V3 V4 V CL C86 P/ COM COM COM V COM3 COM3 COM5 COM6 COM3 COM4 27/7/8 6 Ver.2

62 2. 68 MPU Mode: (DUTY, = : /65duty, CP = : 4x, CL = : Internal display OC.) NT7545 OTP_PWR /C /R D[..7] VDD FR FR OTP_PWR CL CP V_OPT /C C2 /R D D D2 D3 D4 D5 D6 D7 DUTY DUTY VDD VDD3 VDD2 COM63 COM COM48 COM49 COM47 COM46 COM34 COM33 COM V V V3 V2 V V2 V3 V4 V V C CL C86 P/ COM COM COM COM2 COM3 COM3 COM5 COM6 COM3 COM4 27/7/8 62 Ver.2

63 3. erial Mode: (DUTY, = : /65duty, CP = : 4x, CL = : Internal display OC.) COM47 COM46 OTP_PWR /C /R FR FR OTP_PWR CL CP V_OPT /C C2 /R COM34 COM33 COM VDD CL I D D D2 D3 D4 D5 D6 D7 DUTY DUTY VDD VDD3 VDD2 V V V3 V2 V V2 V3 V4 V C V CL C86 P/ COM COM COM COM2 COM3 COM4 27/7/8 63 Ver.2

64 Bonding Diagram Pad No. Designation X Y Pad No. Designation X Y FR VDD FR VDD OTP_PWR VDD OTP_PWR VDD CL VDD CP VDD V_OPT V /C V C V /R V V V V VDD_OPT V D V D V D V D V D V D V D V D V DUTY V V_OPT V DUTY VDD_OPT VDD CL VDD C VDD V_OPT VDD P/ /7/8 64 Ver.2

65 Pad No. Designation X Y Pad No. Designation X Y 59 COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM /7/8 65 Ver.2

66 Pad No. Designation X Y Pad No. Designation X Y /7/8 66 Ver.2

67 Pad No. Designation X Y Pad No. Designation X Y COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM /7/8 67 Ver.2

68 Alignment Mark Location (Total: 2 pins) NO X Y L R Left side Right side (Unit: um) 27/7/8 68 Ver.2

69 Package Information Pad Dimensions Item Pad No. ize X Y Unit Chip size μm Chip thickness μm ~ ~75,76~9 Pad pitch 92~ ~239,24~ μm 9~92,223~ Bump size Output Pad 76~9,224~239 92~223 59~75 24~ μm Input Pad ~ Bump height All pads 5 ± 3 μm 27/7/8 69 Ver.2

70 Ordering Information Part No. NT7545H-D/3 Packages old Bump on Chip Tray Cautions. The contents of this document will be subjected to change without notice. 2. Precautions against light projection: Light has the effect of causing the electrons of semiconductor to move; so light projection may change the characteristics of semiconductor devices. For this reason, it is necessary to take account of effective protection measures for the packages (such as COB and CO, etc.) causing chip to be exposed to a light environment in order to isolate the projection of light on any part of the chip, including top, bottom and the area around the chip. Observe the following instructions in using this product: a. During the design stage, it is necessary to notice and confirm the light sensitivity and preventive measures for using IC on substrate (PCB, lass or Film) or product. b. Test and inspect the product under an environment free of light source penetration. c. Confirm that all surfaces around the IC will not be exposed to light source. 27/7/8 7 Ver.2