UT8MR8M8-EVB 64Megabit Non- Volatile MRAM Evaluation Board User Manual July

Transcription

1 Standard Products UT8MR8M8-EVB 64Megabit Non- Volatile MRAM Evaluation Board User Manual July 0 INTRODUCTION The Aeroflex 64Megabit Non-Volatile magnetoresistive random access memory (MRAM) is a highperformance memory multichip module (MCM) compatible with traditional asynchronous SRAM operations, organized as four individual 6,777,6 words by 8 bits. The MRAM is equipped with five chip enables (/En), a single write enable (/W), and a single output enable (/G) pin, allowing for significant system design flexibility without bus contention. Data is non-volatile for > 5 years at temperature and data is automatically protected against power loss by a low voltage write inhibit. The UT8MR8M8-EVB allows the user access to most all the features of the 64Mb MRAM via bench top evaluation or using the UT699 LEON-3FT evaluation board..0 SCOPE This document describes the features and necessary steps to set-up and operate the Aeroflex Colorado Springs 64Megabit Non-Volatile MRAM Evaluation Board. Users must be familiar with the UT699 LEON-3FT Processor and the 64Megabit Non-Volatile MRAM datasheets. 3.0 REFERENCE DOCUMENTS Aeroflex Colorado Springs, UT8MR8M8 64Megabit Non-Volatile MRAM Datasheet, Aeroflex Gaisler GR-CPCI-UT699 LEON3-FT CPCI Development Board User Manual, Aeroflex Colorado Springs, UT699 3-bit Fault Tolerant SPARC TM V8/LEON3FT Processor Datasheet,

2 4.0 FUNCTIONAL DIAGRAM UT8MR8M8 64M Non-Volatile MRAM (64-Lead FP MCM) Figure. Notional UT8MR8M8-EVB block diagram

3 5.0 FEATURES AND GENERAL OPERATION The Aeroflex 64Megabit Non-Volatile MRAM Evaluation Board provides the user with a flexible means to configure, control, access, and read/write data to the UT8MR8M8 device. Power to the board may be provided through the J9 connector on the GR-UT699 CPCI Development Board or through the 00 mil connector J8 on the UT8MR8M8-EVB. Only one power source should be used at a time. 5. Power 5.. External Power Power to the UT8MR8M8-EVB may be provided externally using 3.3V if using in a bench top only configuration. Figure. External Power Jumper Configuration Settings 3

4 5.. Aeroflex Gaisler Board Power Power to the UT8MR8M8-EVB is also provided from the J9 connector on the GR-CPCI-UT699 LEON3- FT CPCI Development Board. J7, the 0 pin connector, is located on the back side of the EVB. Use caution when mating the 64Megabit Non-Volatile MRAM Evaluation Board to the LEON-3FT evaluation board. Ensure that the mating connectors are lined up and that the power is removed from the GR-cPCI-UT699 eval board prior to plugging in the MRAM evaluation board. Table. LEON-3FT-EVB Power Pins (J9) Table. LEON-3FT-EVB Ground pins (J9) LEON-3FT connector LEON-3FT connector Pin Signal Pin Signal 0 3.3V VSS 0 3.3V 3 VSS V 5 VSS V 7 VSS 5 3.3V VSS 7 3.3V VSS 8 3.3V 3 VSS 9 3.3V 4 VSS 0 3.3V 50 VSS 3.3V 60 VSS 6 VSS 70 VSS 80 VSS 90 VSS 00 VSS 0 VSS 4 VSS 6 VSS 8 VSS 0 VSS 4

5 Figure 3. Aeroflex Gaisler LEON-3FT J7 to J9 connector 5

6 5. Address Inputs Table 3. Address Inputs J7 pin out LEON-3FT connector (J9) UT8MR8M8 Device (J7) Pin Signal Pin Signal 45 A0 0 A0 76 A 9 A 44 A 8 A 77 A3 7 A3 43 A4 6 A4 78 A5 8 A5 4 A6 7 A6 79 A7 6 A7 39 A8 5 A8 8 A9 4 A9 38 A0 4 A0 83 A 40 A 37 A 39 A 84 A3 38 A3 36 A4 37 A4 85 A5 58 A5 35 A6 57 A6 86 A7 56 A7 34 A8 55 A8 87 A9 A9 33 A0 59 A0 88 A A 3 A 3 A 6

7 5.3 Data I/O The UT8MR8M8 has eight bidirectional data lines, DQ[7:0]. The data inputs/outputs are connected to J7 as shown in table 4. Table 4. Data I/O J7 pin out LEON-3FT connector (J9) UT8MR8M8 Device (J7) Pin Signal Pin Signal 95 D4 46 DATA0 97 D5 47 DATA 99 D6 50 DATA 03 D7 5 DATA3 05 D8 4 DATA4 07 D9 5 DATA5 09 D30 8 DATA6 3 D3 9 DATA7 7

8 5.4 Chip Enable Asserting /E_All allows the device to be addressed as a single, 64Mb memory using address bits A and A to decode and select of 4 MRAM die. LEON-3FT connector (J9) Pin Signal Pin Signal Table 5. Enable Signals LEON-3FT (J5) UT8MR8M8 Device (J7) Can be jumpered to /E_ALL for LEON-3FT to control the UT8MR8M8 48 ROMSN0 74 IOSN Can be jumpered to /E_ALL The user can exercise either the IOSN or ROMSN0 pin on the LEON-3FT to exercise the /E_All pin on the MRAM. There is a three pin header, J5, that allows the user to select IOSN or ROMSN0 to control the /E_All pin. Figure 6. /E_All header control 5.4. Use as an External Memory with LEON Set J5 to ROMSN0 on the UT8MR8M8-EVB and uninstall JP6 on the UT699-EVB Use as IO Space Set J5 to IOSN option on the UT8MR8M8-EVB and install JP6 on the UT699-EVB. 5.5 Write Enable (/W) 8

9 /W controls read and write operation. During a read cycle, /G must be asserted to enable the outputs. Table 6. Write Enable LEON-3FT J7 to J9 connector LEON-3FT connector (J9) UT8MR8M8 Device (J7) Pin Signal Pin Signal 46 WEB 4 /W 5.6 Output Enable (/G) /W controls read and write operation. During a read cycle, /G must be asserted to enable the outputs. Table 7. Output Enable LEON-3FT J7 to J9 connector LEON-3FT connector (J9) UT8MR8M8 Device (J7) Pin Signal Pin Signal 47 OEB 53 /G 5.7 Deep Sleep Power Down (ZZ) ZZ controls the sleep mode operation. Enabling sleep mode causes all other inputs to be do not cares. ZZ places all die into internal low power even while system power is still applied to VDD. Pin on the UT8MR8M8 are routed to a three pin header J. The center pin on the three pin J header is tied to the ZZ pin, the other pins are tied to VDD and VSS. Please refer to the UT8MR8M8 datasheet for further information. UT8MR8M8 Deep Power Down 5.8 Multi-Bit Error Flag (MBE) Figure 7. ZZ pin 9

10 The open drain MBE pin drives low when ECC logic detects two bit errors during the current read cycle. It allows for wired-or of multiple MBE signals when using multiple MRAMs. The MBE signal is routed to the one pin J6 header. This pin can be monitored if the user chooses to do so. MBE UT8MR8M8 Figure 8. MBE pin 6.0 Quick Start Guide The following steps describe how the user to get the UT8MR8M8-EVB up and running with the UT699 LEON-3FT EVB.. Connect J5to the UT8MR8M8-EVB to ROMSN0 for using MRAM as PROM - or - Connect J5to the UT8MR8M8-EVB to IOSN for using MRAM as IO Space. Disconnect power to the UT699-EVB 3. Plug the UT8MR8M8-EVB J7 to J9 on the UT699-EVB 4. Configure DIP switches S3 and S4 as shown in Table 9 and Reference Section 3 SETTING UP AND USING THE BOARD in the user s manual for the GR-UT699 board. Install the jumpers as indicated in Table. 0

11 Table 8. Quick Start LEON-3FT S3 8-bit mode Configuration DIP Switch S3 Switch Function Value Comment PIO0 0 8-bit Mode (Closed) PIO 0 8-bit Mode (Closed) 3 PIO 0 PROM EDAC disabled (Closed) 4 PIO3 (Open) 5 PIO4 (Open) 6 PIO5 (Open) 7 PIO6 (Open) 8 PIO7 (Open) Table 9. Quick Start LEON-3FT S4 Configuration DIP Switch S4 Switch Function Value Comment PIO8 (Open) PIO9 (Open) 3 PIO0 (Open) 4 PIO (Open) 5 PIO (Open) 6 PIO3 (Open) 7 PIO4 (Open) 8 PIO5 (Open)

12 Table 0. Quick Start LEON-3FT Jumper settings for ROMSN0 or IOSN Jumper Jumper Setting Comment JP -: Do Not Install 3-4: Do Not Install 5-6: Do Not Install 7-8: Do Not Install ASIC TEST mode pin not enabled DSU is enabled JTAG interface is enabled. Watchdog output can cause board reset JP Do Not Install Ethernet MDIO interface interrupt is not connected to GPIO4 JP3-3: Install End-stub termination enabled see section.4. JP4-3: Install End-stub termination enabled see section.4. JP5 -: Install 3-4: Install 5-6: Install 7-8: Install Connects RAMSN0 and RAMSN to on board SRAM banks JP6 Do Not Install Connects ROMSN0 to on board MRAM on UT8MR8M8-EVB -: Install Connects IOSN to on board MRAM on UT8MR8M8-EVB JP7 -: Install 3-4: Install PCI Host Mode clocks to backplane see section. JP8 -: Install 3-4: Install 5-6: Install 7-8: Install 9-0: Install -: Install 3-4: Install 5-6: Install 7-8: Install 9-0: Install PCI Host Mode- Pull ups enabled see section. JP9 -: Install 3-4: Install PCI Host Mode see section. JP0 -: Install 3-4: Install PCI Host Mode see section. JP Install Connects to Front Panel LED indicators JP -: Install See section.9 JP3 -: Install See section.9 JP4 Install Can be used as current measure point for Vcore supply to ASIC JP5 Install Can be used as current measure point for 3.3V supply to ASIC JP6 Install Connected to Front Panel push buttons for RESET and BREAK JP7 -: Install Main Processor Clock is also source for SPW_CLK JP8 -: Install Board RESETN also generated PCI_RSTN for PCI Host 6. Power on the UT699-EVB 7. Using GRMON: a. MRAM as PROM: The following commands need to be run to set up memory configuration register to allow reading and writing the MRAM when it is configured as the PROM for the UT699. i. wmem 0x x803c8 ii. mcfg 0x803c8 iii. User code

13 b. MRAM as I/O space: The following commands need to be run to set up memory configuration register to allow reading and writing the MRAM when it is configured as I/O space for the UT699. i. wmem 0x x00BC8 ii. mcfg 0x00BC8 iii. User code 7.0 COMPATIBILITY WITH GR-UT699 EVALUATION BOARD The UT8MR8M8-EVB can plug directly into the J9 connector on the LEON-3FT evaluation board. J9 on the GR-UT699 evaluation board is pinned out as listed in table below. For further information on interfacing the UT8MR8M8-EVB with the GR-UT699 Evaluation board please see the Aeroflex Gaisler GR-UT699 Development Board User Manual. Table. UT8MR8M8-EVB to UT699-3FT LEON connections LEON-3FT connector UT8MR8M8 Device Pin Signal Pin Signal VSS +5V NC 3 VSS 4 -V NC 5 VSS 6 +V NC 7 VSS 8 D5 NC 9 D7 NC 0 3.3V VSS D4 NC 3 D6 NC 4 D3 NC 5 D5 NC 6 D NC 7 D4 NC 8 D NC 9 D3 NC 0 3.3V VSS D0 NC 3 D NC 4 D9 NC 5 D NC 3

14 6 D8 NC 7 D0 NC 8 A6 NC 9 A4 NC V 3 VSS 3 A 3 A 33 A0 59 A0 34 A8 55 A8 35 A6 57 A6 36 A4 37 A4 37 A 39 A 38 A0 4 A0 39 A8 5 A V 4 VSS 4 A6 7 A6 43 A4 6 A4 44 A 8 A 45 A0 0 A0 46 WEB 4 WEB 47 OEB 53 OEB 48 ROMSN0 ROMSN0 49 RAMSN4 NC 50 VSS 5 3.3V 5 RAMSN3 NC 53 RAMSN NC 54 RAMSN NC 55 RAMSN0 NC 56 RWEN NC 57 RWEN0 NC 58 BRDYN NC 59 RESETN NC 60 VSS 6 VSS 6 CLK NC 63 BEXCN NC 64 RWEN NC 65 RWEN3 NC 66 RAMOEN0 NC 67 RAMOEN NC 68 RAMOEN NC 69 RAMOEN3 NC 70 VSS 4

15 7 3.3V 7 RAMOEN4 NC 73 RAMSN NC 74 IOSN 75 READ NC 76 A 9 A 77 A3 7 A3 78 A5 8 A5 79 A7 6 A7 80 VSS 8 3.3V 8 A9 4 A9 83 A 40 A 84 A3 38 A3 85 A5 58 A5 86 A7 56 A7 87 A9 A9 88 A A 89 A3 NC 90 VSS 9 3.3V 9 A5 NC 93 A7 NC 94 D6 NC 95 D4 46 DATA0 96 D7 NC 97 D5 47 DATA 98 D8 NC 99 D6 50 DATA 00 VSS 0 3.3V 0 D9 NC 03 D7 5 DATA3 04 D0 NC 05 D8 4 DATA4 06 D NC 07 D9 5 DATA5 08 D NC 09 D30 8 DATA6 0 VSS 3.3V D3 NC 3 D3 9 DATA7 4 VSS 5 +V NC 5

16 6 VSS 7 -V NC 8 VSS 9 +5V NC 0 VSS 6

17 8.0 BOARD SCHEMATICS The schematics are for reference ONLY. 7

18 Change Block MQ VDD3_3V D D VDD3_3V ADR_38 ADR_38 E_38_CS U A0 3 A A 4 5 E 6 E E3 GND VDD 6 O0 O O O3 O4 O5 O6 O CEB_ CEB_ CEB_3 CEB_4 54AC38/FP VDD3_3V Silkscreen UT8MR8M8(P) C B Silkscreen VDD Silkscreen VSS Silkscreen IOSN J5 ROMSN0 3 HEADER 3 Silkscreen ZZ SLEEPY J 3 HEADER 3 IOSN R5 0k R6 0k E_38_CS ROMSN0 VDD3_3V R3 0k Silkscreen 3.3V POWER VDD3_3V J8 HEADER VDD3_3V CEB_ ADR4 ADR3 ADR ADR ADR0 ADR9 DATA4 DATA5 DATA6 DATA7 CEB_ ADR_38 ADR_38 ADR9 ADR8 ADR7 ADR6 ADR5 U VSS VDD 64 3 VDD VSS NC NC4 6 5 NC NC5 6 E0_B E3_B A4 A A3 A A A A A7 55 A0 A8 54 A9 NC6 3 ZZ_NUIL G_B NC3 NC7 5 5 DQ4 DQ DQ5 DQ 7 VDD VSS 49 8 VSS VDD DQ6 DQ 46 0 DQ7 DQ0 E_B E_B 45 E_B_ALL_NUIH VSS 44 3 A_NUIL MBE_NUO 43 4 A_NUIL W_B A9 A A8 A 39 7 A7 A 38 8 A6 A A5 A4 30 VSS VSS 36 3 VSS VSS 35 3 VSS VDD 34 VDD VSS 33 UT8MR8M8_MQ9_0 CEB_4 ADR0 ADR5 ADR6 ADR7 ADR8 OEB VDD3_3V DATA3 DATA DATA DATA0 CEB_3 WEB ADR0 ADR ADR ADR3 ADR4 Silkscreen J6 MBE Silkscreen GND J9 J0 HEADER HEADER 0K R HEADER Silkscreen VDD Silkscreen VSS Silkscreen UT54ACS38E pin G J 3 HEADER 3 VDD3_3V R7 0k R8 0k VDD3_3V IOSN ADR ADR3 ADR5 ADR7 ADR9 ADR ADR3 ADR5 ADR7 ADR9 ADR_38 DATA0 DATA DATA DATA3 DATA4 DATA5 DATA6 DATA7 Silkscreen TO LEON-3FT UT699 EVAL board J7 6 6 DGND 63 CLK 64 BEXCN 65 RWEN 66 RWEN3 67 RAMOEN0 68 RAMOEN 69 RAMOEN 70 RAMOEN3 7 DGND 7 3.3V 73 RAMOEN4 74 ROMSN 75 IOSN 76 READ 77 A 78 A3 79 A5 80 A7 8 DGND 8 3.3V 83 A9 84 A 85 A3 86 A5 87 A7 88 A9 89 A 90 A3 9 DGND 9 3.3V 93 A5 94 A7 95 D6 96 D4 97 D7 98 D5 99 D8 00 D6 0 DGND 0 3.3V 03 D9 04 D7 05 D0 06 D8 07 D 08 D9 09 D 0 D30 DGND 3.3V 3 D3 4 D3 5 DGND 6 +V 7 DGND 8 -V 9 DGND 0 +5V DGND 60 RESETN DGND 59 BRDYN RWEN0 56 RWEN 55 RAMSN0 54 RAMSN 53 RAMSN 5 RAMSN3 DGND 5 3.3V RAMSN4 48 ROMSN0 OEN 47 WRITEN A0 44 A 43 A4 4 A6 DGND 4 3.3V A8 38 A0 37 A 36 A4 35 A6 34 A8 33 A0 3 A DGND 3 3.3V 30 9 A4 8 A6 7 D0 6 D8 5 D 4 D9 3 D D0 DGND 3.3V 0 9 D3 8 D 7 D4 6 D 5 D5 4 D3 3 D6 D4 DGND 3.3V 0 9 D7 8 D5 DGND 7 +V 6 DGND 5 -V 4 DGND 3 5V DGND ROMSN0 OEB WEB ADR0 ADR ADR4 ADR6 ADR8 ADR0 ADR ADR4 ADR6 ADR8 ADR0 ADR_38 VDD3_3V C B CONN_MEZ0 C C C3 C4 C5 C6 + C7 0.uF0.0uF 0.uF0.0uF 0.uF0.0uF 47uF A A Aeroflex Colorado Springs 4350 Centennial Blvd. Colorado Springs Colorado M MRAM EVALUATION BOARD Size Scale CAGE Code DWG NO Rev C 6534 Larsen of Tuesday, March 0, Sheet -

19 ORDERING INFORMATION UT ***** Device Type: 8MR8M8-EVB = 64Megabit Non-Volatile MRAM Evaluation Board 8

20 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi Rel 9