SpaceWire Remote Terminal Controller

Transcription

1 Remote Terminal Controller Presented by Jørgen Ilstad On board Payload Data Section, ESTEC Wahida Gasti, ESA ESTEC Co Authors Sandi Habinc, Gaisler Research Peter Sinander, SAAB Space Slide : 1

2 Overview Introduction ESA Strategy On-board ASSP SpW Description SpW and On-board Computing Architecture Payload Applications Platform Applications Conclusion Slide : 2

3 Introduction Satellite payloads are becoming increasingly more complex Increased requirements of on-board processing capabilities Onboard intelligence or even some form of autonomy for advanced satellites ESA anticipated this trend by developing a concept to facilitate implementation of such requirements Payload data systems based on integration of building blocks allowing equipment and module re-use. Slide : 3

4 ESA strategy on payload developments Development of Application Specific Standard Products (ASSP) Devices capable of answering most onboard computing needs for the coming decade. Adopt upcoming ASIC developments to use similar device architectures based on pre-validated ESA IP cores for the purpose of reducing development time and recurring costs. Ensure SpW nodes developed by ESA (i.e. component, module, unit etc) to be easily integrated in ESA On-Board Distributed Computing and Control System. Slide : 4

5 SpW Description Supports Dual FIFO configuration (DMA support) Watchdog timer with external trigger output Supports Generation of Pulse Commands using the internal timers FIFO i/f (Parity check) 32 bit Timer DSU serial Link (UART) 2 x UART Serial links 16 bit GPIO Prg. I/O shared with IRQ and UARTs Dual SpW controller JTAG i/f Meiko FPU LEON2 FT Core Ver r Kb On chip memory (EDAC) DSU Tracebuffer 512 lines 16bit Memory Controller (EDAC) IRQ (16 ext.) CAN controller MUX Channel select DAC i/f ADC i/f Memory mapped 24 bit GPIO 2 x 32 bit Timers Supports one ADC and one DAC device, with 8- or 16-bit wide data, and 8-bit address. Unused address and data bits can be used as general purpose I/O. Supports two PROM banks, four SRAM banks and memory mapped I/O. Features 23 byte-address bits, 32 data bits and 8 check bits. Unused data bits can be used as general purpose input output. SRAM, (EE)PROM, Flash PROM Dedicated programmable input output channels, with input interrupts. Supports external clock source and external triggers. On-Chip LVDS drivers Link1 Link2 Two 200 Mbit links Supports RMAP and DMA transfers and simultanous operation A B Two CAN channels, one cold redundant AMBA Bus Domain Slide : 5

6 CAN On-Board Payload Data Section TEC-EDP SpW as part of the On-board computing architecture Payload Discrete Signals Payload Applications Remote Terminal Unit CAN and SpW network bridge 2 4 High Data Rate Instrument Control 1 Cmd. Pulses Discrete Signals Alarms 3 SSMMC On-board Computer ACE 5 AOCS SpW i/f Platform Applications Router X10 ASIC TT&C SpW ASIC Versatile device offering: Computational power interfaces CAN interface ADC/DAC interfaces Memory with EDAC FIFO with parity check General Purpose I/O UARTs 32 bit timers Slide : 6

7 CAN On-Board Payload Data Section TEC-EDP Payload Applications Instrument Control Payload 4 High Data Rate Instrument Control 1 Cmd. Pulses Discrete Signals Alarms On-board Computer Router X10 ASIC SpW ASIC Discrete Signals 2 Remote Terminal Unit 3 SSMMC ACE 5 AOCS SpW i/f TT&C Payload Slide : 7

8 CAN On-Board Payload Data Section TEC-EDP Attitude Control Electronics Platform applications Payload 4 High Data Rate Instrument Control 1 Cmd. Pulses Discrete Signals Alarms On-board Computer Router X10 ASIC SpW ASIC Discrete Signals 2 Remote Terminal Unit 3 SSMMC ACE 5 AOCS SpW i/f TT&C Solid State Mass Memory Controller Slide : 8

9 The SpW- Conclusion Is a result of ESA strategy towards modular architectures based on. Answers to ASSP development strategy to reduce development time and recurring costs. Architecture offers both substantial processing capability as well as SpW, CAN i/f, memory and FIFO i/f, GPIO etc. which makes it suitable for both payload and platform applications. Will be supported by industry s/w and h/w development tools available early Alpha customers is currently validating the FPGA implementation of the SpW to asses the device to be used as common backend of the Bepi- Colombo instruments. ASIC manufactured in MCGA 349 package in Atmel ATC18RHA technology Flight Prototypes available early Slide : 9

10 Thank you for your attention Preliminary datasheet and user manual is obtainable from Slide : 10