Application Note # Design For Boundary-Scan Testing and In-System Programming Guidelines. September 18, 2003

Transcription

1 CORELIS Application Note # Design For Boundary-Scan Testing and In-System Programming Guidelines September 18, 2003 Please send inquiries and comments to: Tech Support: Sales Info: Web: Page 1 of 31

2 Table of Contents GENERAL DESCRIPTION 4 COMPONENT DESIGN RULES 4 Placement of the TAP signal pins 4 Higher-order Instruction Capture Bits 4 3-state and Bidirectional Pin Control 4 Unused Instruction Opcodes 5 Automated Tools for Design of Component JTAG Logic 5 Pin Numbers in BSDL File Should Match Those of Datasheet 5 BOUNDARY-SCAN INFRASTRUCTURE 6 Place All Devices in a Single Boundary-scan Chain 6 Check Devices for Full IEEE Compliance 6 Group Components With Similar Logic Characteristics 6 Maintain Signal Integrity 6 Connection to the Boundary-scan Chain 8 Making the Boundary-scan Chain Reconfigurable 8 BOARD-LEVEL DESIGN 10 TCK Clock Distribution 10 Provide Control of Critical Nodes 11 Testing of Memory Devices as non-boundary-scan Clusters 11 Ensure Proper Power Supply Bypassing 12 Use Components That Have a BSDL File Available 12 Compliance Enable Conditions Listed in the BSDL File Must be Met 12 Page 2 of 31

3 Use BS Compatible Buffers and/or Whenever Possible 13 Corelis SCANIO Modules for Edge Connectors and Test Points 13 Flash Programming 14 Pin Numbers in Board Netlist Must Match the BSDL Files 15 NON-IDEAL COMPONENTS BEHAVIOR 16 Motorola MPC Xilinx Devices 17 Devices That Do Not Include a Boundary-scan Register 21 Motorola Non-Compliant Lattice Parts 22 Lucent ORCA FPGAs 22 IDT 64474/64475/64574/64575 Microprocessors 23 Altera EPM7128ATC and Similar Parts 23 Altera FLEX 6000 Parts 23 Motorola MPC TI 320C6202 DSP Chip 24 Lattice s ScanPath Linker Chip 25 TI MSP430 Family of DSP Chips 26 TI TMS320VC5441 DSP Chip 267 Page 3 of 31

4 General Description Boundary-scan (JTAG) uses dedicated test logic built into the components on-board to support testing and in-system programming. This document provides some general guidelines for designing at the component and board level which help to ensure the successful use of boundary-scan to accomplish these goals. Component Design Rules The boundary-scan architecture begins at the component level. In many cases, the components used in your design will be off the shelf with dedicated JTAG logic and a BSDL file provided by the component manufacturer. In some cases, you will be required to incorporate the JTAG logic into the component yourself (such as with a custom ASIC). In those cases when you are designing the JTAG logic into your own component, there are several factors to be considered: Placement of the TAP signal pins The TAP signal pins (TDI, TDO, TMS, TCK and TRST*) should be physically separated from one another on the component. Problems related to the TAP signals are the most difficult type of boundary-scan testing problem to diagnose. If possible, these pins should be placed adjacent to power pins on the component. The reasoning behind this is that a TAP signal shorted to a power pin is much more easily diagnosed than 2 TAP signals shorted together or a TAP signal shorted to another signal. With fine pitch devices, the most common type of manufacturing faults are shorts (solder bridges) between adjacent pins and open pins. Placing the TAP pins on the corners of the device reduces even further the possibility that the pin will be shorted to an adjacent pin. Higher-order Instruction Capture Bits The higher-order Instruction Capture bits should be predictable. Leaving these bits as don t care makes boundary-scan chain problems more difficult to diagnose. In addition, these bits can be used as a simple method of component identification when no other method exists (i.e., IDCODE is not supported). 3-state and Bidirectional Pin Control Direction/high-impedance state control for certain types of bidirectional and 3-state pins (such as address and data) should be separated. If these are not separated, it may cause problems. One example of this is when using boundary-scan for ISP of flash devices. In this case, if the flash device itself is connected directly to the address and data pins of a microprocessor and the direction/high-impedance state of the address and data pins are controlled with the same control cell in the boundary-scan register of the microprocessor, then it is not possible to have the address pins configured as output and at the same time have the data pins configured as input, making it impossible to use the boundary-scan of the microprocessor itself to do ISP the flash device. Page 4 of 31

5 Unused Instruction Opcodes Unused TAP instruction opcodes should default to BYPASS. This ensures that the component is maintained in a safe state in the event that one of these opcodes in inadvertently selected. Automated Tools for Design of Component JTAG Logic When designing your own ASIC, it may be worthwhile to consider using automated tools for the insertion of JTAG logic into the component. By doing this, there will be a higher probability that the JTAG logic in the component itself will fully comply to the IEEE standard. Tools for Automatic Test Pattern Generation (ATPG) of boundary-scan test vectors rely heavily on the fact that the boundary-scan components are fully compliant to the IEEE standard. If a component is not fully compliant to the IEEE standard, there is a good chance that the component may not even be able to be used for boundary-scan testing. In the worst case scenario, it may even be necessary to physically BYPASS the component in the chain by jumpering the TDI node to the TDO node and forcing the TMS pin high. In addition, when these tools are used, a BSDL is produced automatically saving the time and effort of manually creating it. Pin Numbers in BSDL File Should Match Those of Datasheet In order for tools for Automatic Test Pattern Generation (ATPG) of boundary-scan test vectors to correctly correlate the pin numbers between the board netlist and the BSDL files for the boundary-scan components used on board, the component pin numbers in the BSDL files for the boundary-scan components on-board must exactly match the pin numbers in the board netlist. Therefore when creating a BSDL file for a boundary-scan component, the pin numbers used BSDL file for a boundary-scan component should exactly match those given in the component datasheet or spec. Page 5 of 31

6 Boundary-scan Infrastructure Boundary-scan devices in a typical design are organized into boundary-scan chains. Successful testing and ISP of your design with boundary-scan hinges on the fact that the boundary-scan chains on the can be reliably scanned by an external boundary-scan controller. Therefore, it is very important to observe some simple rules when constructing the boundaryscan chains on your design: Place All Devices in a Single Boundary-scan Chain It simplifies connection to the board all of the components on board can be organized into a single boundary-scan chain. If this is not feasible due to other design constraints, then products such as the Corelis Buffer can be used to externally combine the boundary-scan chains on-board into a single chain (TAP chaining). In addition to the TAP chaining capability, the Buffer also provides signal buffering and conditioning. It may also be possible to externally combine the chains on on-board with a simple fixture or cable. When doing this though, you may need to consider signal loading on the common signals such as TCK and other signal quality factors. Check Devices for Full IEEE Compliance Before placing a component in a boundary-scan chain with the remainder of the devices onboard, verify that the component fully complies to the IEEE standard. Tools for Automatic Test Pattern Generation (ATPG) of boundary-scan test vectors rely heavily on the fact that the boundary-scan components are fully compliant to the IEEE standard. If a component is not fully compliant to the IEEE standard, there is a good chance that the component may not even be able to be used for boundary-scan testing. In the worst case scenario, it may even be necessary to physically BYPASS the component in the chain by jumpering the TDI node to the TDO node and forcing the TMS pin high. Group Components With Similar Logic Characteristics In many cases, you will use devices with different logic characteristics on the same design (e.g., a mixture of 5v logic and 3.3v logic). By grouping the devices with similar logic characteristics together in the boundary-scan chain, it minimizes the amount of special interfacing required. Maintain Signal Integrity Provisions should be made to ensure that the signal quality of critical TAP signals on board, such as TCK, is maintained. Corelis recommends the following signal terminations on the board TAP signals: Page 6 of 31

7 Pin Signal Direction Termination 1 TRST* Input to the UUT 1K pull-up 2 GND 3 TDI Input to the UUT 1K pull-up 4 GND 5 TDO Output of the UUT 33 ohm series 6 GND 7 TMS Input to the UUT 1K pull-up 8 GND 9 TCK Input to the UUT 1K pull-up 10 GND Additional details can be found in Application Note available from Corelis. Using these values of signal terminations has been shown to be very effective in eliminating noise and signal integrity problems on the many designs tested with Corelis ScanPlus boundary-scan tools. When there are a large number of boundary-scan devices on board, it may be necessary to buffer the common TAP signals such TCK and provide separate copies of this signal to individual groups of the boundary-scan components on board to reduce the loading on the signal. Doing this in no way complicates the boundary-scan testing and ISP of the board when using Corelis ScanPlus tools. Note that the design of components that fully comply to the IEEE standard ensures that a reasonable amount of clock skew between components and also between the external boundary-scan controller and the components on board (less than ¼ TCK clock period) is acceptable because: The state of TMS (driven by the external boundary-scan controller) changes on the falling edge of TCK. The component TAP state changes on the rising edge of TCK based on the current state of TMS. The state of TDO changes on the falling edge of TCK and the TDI value is clocked in on the rising edge of TCK. So it is relatively simple to find a buffer that will meet these requirements. The multiple test run feature of ScanPlus Runner can be used in many cases to detect and isolate signal quality problems. In many cases, signal quality problems will result in an intermittent failure of the Infrastructure test, which shifts a large number of patterns through the boundary-scan chain without affecting the I/O of the components on board. The degree of test failure depends on the severity of the problem. In some cases, you may only see one test Page 7 of 31

8 failure in 1000 but it is still detectable. It is fairly simple to setup ScanPlus Runner to run the Infrastructure test a large number of times and detect these types of problems. Connection to the Boundary-scan Chain For connection to the boundary-scan chain on board, Corelis recommends a simple 10-pin header that contains the 5 TAP signals and 5 grounds. This can be as simple as 2x5 pin strip header or it can be a shrouded header which provides connector keying. Details of this are provided in Application Note available from Corelis. For in-system flash programming, a 16-pin connector is recommended that contains some additional control signals to reduce flash programming time. Details of this are provided in Application Note available from Corelis. Making the Boundary-scan Chain Reconfigurable In some cases (such as for JTAG emulation), it is required to keep certain boundary-scan components (such as a microprocessor) isolated in a chain by themselves. This can be done using jumpers or through the addition of electronic components to the board design. Shown in the figure below is an example of using jumpers to make the boundary-scan chain reconfigurable. VCC JTAG Connector TDI Microprocessor Other JTAG Device Other JTAG Device TCK TMS Jumper 1 TDO 2 position header (Jumper 2) In this figure, 2 jumpers are used to determine whether just the microprocessor is in the chain or all JTAG devices are in the chain. By installing Jumper 1 and also installing a jumper between the bottom 2 posts on the 2 position header, all devices are included in the chain. If Jumper 1 is removed, the pull-up resistor will hold the TMS on the "other" JTAG devices in a high state, keeping them in Test-Logic-Reset. If a jumper is then installed on the top 2 posts on the 2 position header, the TDO from the microprocessor is routed to the connector. This effectively places just the microprocessor in the chain. Shown in the figure below is an example of including additional logic devices in the boundaryscan devices in order to make the boundary-scan chain reconfigurable: Page 8 of 31

9 JTAG Connector TDI Microprocessor Other JTAG Device Other JTAG Device TCK VCC TMS SELECT NAND TDO MUX Shown in this figure is a similar arrangement, using logic (multiplexers) instead of jumpers. A "select" at the connector is used to determine the chain configuration. Grounding the "select" will just include the microprocessor in the chain. If the "select" is left open, then all devices are included. This arrangement is nice because it allows you to control the JTAG chain configuration based on the cable that is plugged into the JTAG connector. Page 9 of 31

10 Board-level Design In order to ensure maximum testability through boundary-scan, it is important to follow some rules when designing your board for boundary-scan testing. Even the smallest details can make the difference between a low test coverage and successfully testing your board through boundary-scan. Corelis offers a service free-of-charge where we review your design for boundary-scan testability. During this process, we can give you an estimate of the amount of test coverage that can be achieved through boundary-scan and we can also offer suggestions on how to improve testability. Even with this in mind, below are some general rules to follow to ensure that your design is testable through boundary-scan: TCK Clock Distribution The entire operations of the boundary scan circuits depend on the quality of the TCK signal. Distributing the TCK clock signal to all the boundary scan devices on the board requires special attention. Basically, the general rule of thumb is that the TCK signal need to be treated like any other high speed clock signal on the board. Use the same high speed signal distribution guidelines that you apply to any other clock signal on your target board. TCK must be treated like any other high speed clock on the board with all relevant rules: loading, termination, distribution, layout-routing, matching trace impedance to termination resistor(s), keeping the clock trace as short as possible, etc. The following are some of the issues that should be considered by the circuit designer when designing for testability: 1. When buffering the TCK signal do NOT use PLL based clock buffer chips. Zero delay clock distribution devices (for distributing the TCK signal to multiple devices on the board) always incorporate internal PLL and cannot be used. Unlike CPU clocks and system clocks the TCK clock is not free running Therefore the zero delay clock distribution buffers will not work as they contain an internal PLL which requires free running input clock source because the TCK signal is NOT a free running clock. For example, the Cypress CY2309 or the Pericom PI6CV857L are clock driver chips that incorporate a non-pll bypass mode of straight through clock in to clock out mode (for testing). 2. Add series resistors on clock drivers outputs. 3. While a single TAP makes it easy to connect and test the user can implement multiple TAPs to connect to different sections of the target board (see Corelis app note ). It is generally recommended to restrict the total number of TAPs to 4 or less. 4. The size of the board and the number of boundary-scan (BS) compatible components may require separate TCK signal buffers for each group of physically adjacently BS devices. 5. Adding buffers on the TCK (and the other TAP signals) will decrease the maximum TCK clock rate that can be used for scanning. While this is typically not an issue for boundary scan interconnect tests maintaining high TCK clock rates is important for reducing the overall programming time of Flash memories. 6. The remainder of the TAP signal are less sensitive and the 1K pull-up generally suffice and typically no other special considerations are required. Page 10 of 31

11 7. Using an active cable (BUFFER ) could help improve the TCK signal quality. The active cable places buffers closer to the tip of the cable that plugs into the customer target board 8. Splitting the board into multiple TAPs helps segment the board into small adjacent boundary scannable clusters. However, it would require extra connectors and a BUFFER or equivalent external cable 9. In a chassis with multiple cards the boundary scan can be configured in a multi-drop configuration where a single TAP is bussed across the backplaned. The Corelis ScanGate chip can be used to buffer all TAP signals from the host and distribute them reliably to multiple local TAPs under host software control. Provide Control of Critical Nodes Some non-boundary-scan devices include the ability place all of the 3-state outputs in a high impedance state. In some cases, this is done when the reset is asserted to the device. In some cases, it is a dedicated pin such as the ONCE pin on some Motorola devices. Asserting these pins can be done by using a dedicated jumper which is installed on-board during boundary-scan testing. It can also be done using the Parallel I/O (host bus controlled I/O) available on the Corelis boundary-scan controllers. In ScanPlus Runner, the Parallel I/O on the boundary-scan controllers can be used to support boundary-scan testing. For state machines and other types of synchronous devices (such as synchronous memory), it is critical that we have control of the clock to the device (cluster) with a boundary-scan controllable pin. If caught early in the design stage, there are methods of providing control of the clock signal with boundary-scan and not affecting the overall operation of the circuit. For example, if a tri-state capable clock driver/generator is used in the design and if it is possible to tri-state this for purpose of testing (using a jumper or other mechanism), then you can attach a normally "unused" boundary-scan pin (maybe from an FPGA) to this net. This boundary-scan pin will only be used for testing and will not be used during the normal operation of the circuit. This will give you boundary-scan control of the net when testing, yet not affect the operation of the circuit functionally. Testing of Memory Devices as non-boundary-scan Clusters In today s market, the majority of memory devices available do not include boundary-scan capability. Even if the memory devices on-board do not include boundary-scan capability, they can still be tested automatically using ScanPlus TPG through what is referred to as a Memory Cluster test. Memory Cluster tests are produced automatically by ScanPlus TPG for many types of memory devices, including Async DRAM, Sync DRAM, Async SRAM, Sync SRAM, Async FIFOs, Sync FIFOs, Registers, etc. Memory cluster tests are performed by emulating read/write cycles to the memory device using surrounding boundary-scan devices. The patterns in this case are not applied to the memory device in real-time, but memory cluster testing will give you the capability of detecting opens and shorts on the pins of the memory device, which are the most common types of problems found in manufacturing and production. Therefore, when testing memory devices that do not include boundary-scan capability, it is critical that we have the ability to control the pins on the memory device using surrounding boundary-scan devices. This includes, but not limited to, address pins, data pins, chip select/enable, output enable, RAS (DRAM), CAS (DRAM), clock Page 11 of 31

12 (synchronous devices), write strobe (FIFO), read strobe (FIFO), and write enable. Note that in addition to this, the boundary-scan device(s) that are used to apply patterns to the memory device in-system must have the capability of driving the address and control pins on the memory device, and independently have the ability to drive or sample from the data pins on the memory device. On some boundary-scan devices, multiple outputs on the device are assigned to the same control cell in the boundary-scan register, limiting the way the outputs are configured/controlled When generating a Memory Cluster test, you specify a Memory Information File (MIF) to ScanPlus TPG. This is a "model" of the memory device and allows us to produce the test patterns automatically. We provide many MIFs with ScanPlus TPG. If you cannot find a MIF for the specific memory device that you are interested in, let us know and we may have one available, or we can generate one for you, or you can easily create one of your own. Ensure Proper Power Supply Bypassing Boundary-scan testing sometimes places additional constraints on board design. For example, when all components enter the UPDATE-DR state, a large number of outputs on-board may change state simultaneously (more than during normal operation). This can induce ground bounce or other circuit problems when the devices on-board are not properly bypassed. The ScanPlus tools support a feature where individual components can be held in the BYPASS state during testing. In this way, you can break up the testing of the interconnects on-board into several sub-tests, keeping the number of outputs that change simultaneously to a minimum. Use Components That Have a BSDL File Available During the component selection phase, ensure that the manufacturer has created a BSDL file for any JTAG components that you intend to use in your design. This will prevent unnecessary delays when it becomes time to generate the boundary-scan tests for your board. BSDL is the standard language for describing boundary-scan devices and device manufacturers usually provides a BSDL for the component as soon as engineering samples are available. Typically, you can get BSDL files from the component manufacturer s web site. Corelis also maintains an internal library of BSDL files. If you have difficulty finding the BSDL file for the device that you are using, check with us. We may have it in our library or we may be able to help you locate it. Compliance Enable Conditions Listed in the BSDL File Must be Met The Compliance Enable Description in the BSDL file indicates the component pin states that must be maintained in order for the TAP and test logic in the component to be operational. For example, in the BSDL file for the Motorola MPC106 device, the following Compliance Enable description is provided: attribute COMPLIANCE_PATTERNS of mpc106: entity is "(LSSD_MODE_L) (1)"; This indicates that the pin LSSD_MODE_L on the MPC106 component must be held in a high Page 12 of 31

13 state in order for the TAP and test logic in the component to operate in a manner consistent with that described in the IEEE standard. In BSDL files generated under earlier (proposed) versions of BSDL, this may have been described through a COMPLIANCE_ENABLE statement. Use BS Compatible Buffers and/or Whenever Possible This is basically a tradeoff between diagnostics capability and cost. As buffers and data transceivers increase in size (20-bit and 32-bit devices are now common), it is becoming much more cost effective to include boundary-scan capability in these devices. With ScanPlus TPG, it is fairly easy to create cluster tests for Buffers and Data Transceivers. With cluster tests, you are basically applying patterns to one side of the buffer or data transceiver using boundary-scan devices and capturing the result using boundary-scan devices on the other side. By doing this, you are getting fault coverage over these devices, but you are not able to diagnose failures down to the pin/node level. By using boundary-scan buffers and data transceivers, you can diagnose down to the pin and node level. SDRAM and DDR Memory Testing This is basically a tradeoff between diagnostics capability and cost. As buffers and data In order to test SDRAM and DDR memory devices as boundary scan clusters it is required that the entire SDRAM chip be "surrounded" by boundary scan, including the clock signal. Often, the clock signal of the SDRAM device is driven directly by a special clock driver/pll chip - which is not boundary scan compatible. There are a few options as to how to control the SDRAM clocks: 1. Disable the clock driver chip(s) during testing by negating the ENABLE input of the chip. 2. Drive the clock by an external signal or 3. Drive the clock from an unused FPGA or CPLD pin. The spare pin is tri-stated during normal operational mode and in testing mode this pin is driven by boundary scan. 4. Provide on board jumpers so that the clock to each SDRAM device can be connected to another boundary scannable pin during testing (and to the clock driver chip during normal operational mode). Corelis SCANIO Modules for Edge Connectors and Test Points The SCANIO provide boundary-scan controlled digital I/O that can be used to support testing of board edge connectors and also internal board nodes that are otherwise inaccessible through boundary-scan. To use a SCANIO module, connect the digital I/O on the SCANIO module to the nodes on-board that you want to access with boundary-scan and place the boundary-scan devices in the SCANIO in series with the boundary-scan devices on-board. This can be an edge connector or even an internal board node accessible through a test point or header. The SCANIO boundary-scan devices are then added to the board Topology and netlist is merged with the board netlist using the Corelis ScanPlus Merge product. Page 13 of 31

14 Flash Programming In-system programming of flash devices through JTAG is done by emulating read/write cycles to the flash device using surrounding boundary-scan devices. Therefore, when programming flash devices that do not include boundary-scan capability, it is critical that we have the ability to control the pins on the flash device using surrounding boundary-scan devices. This includes, but not limited to, address pins, data pins, chip select/enable, output enable, clock (synchronous devices), and write enable. Note that in addition to this, the boundary-scan device(s) that are used to apply patterns to the flash device in-system must have the capability of driving the address and control pins on the memory device, and independently have the ability to drive or sample from the data pins on the flash device. On some boundary-scan devices, multiple outputs on the device are assigned to the same control cell in the boundary-scan register, limiting the way the outputs are configured/controlled. Data pins must never be assigned to the same control cell as other pins that are mandatory for programming the flash device (i.e. address, chip select, write enable, etc.) If there are non-boundary-scan components in between a boundary-scan component and the flash device, this must be specified to the Corelis ScanPlus Flash Generator tool. During flash programming, the data must flow from the boundary-scan device towards the flash device for write cycles, and from the flash device to the boundary-scan device for read cycles. The level of the directional control boundary-scan pin(s) connected to the transceiver during write (low or high) is specified to ScanPlus Flash Generator, which in turn automatically specifies to ScanPlus Flash Programmer how to handle setting these pins during programming. The following equation can be used for calculating the absolute minimum flash programming time through a JTAG interface (that is, the best programming time that can be achieved): (#bits in chain) * (#scans/write) * (#writes/location) * (#locations) TCK frequency Where: #bits in chain - effective length of the boundary-scan chain (assuming unused components placed in BYPASS) #scans/write - number of DR scans which are required in order to write a data value to the flash #writes/location - number of data values that must be written to program each location #locations - number of data locations to be programmed TCK frequency - frequency of the JTAG TCK signal Below is an example calculation, assuming the following conditions: Device 28F016SV (size is 2Mbyte = bytes or words) Data Access Type Page 14 of 31

15 Word (16-bits) TCK Frequency 5 MHz #Scans/Write 1 (direct write provide to flash) #Writes/Location 2 (command value and then data value) #Bits in Scan Chain 202 (Intel 386EX processor) Using these values, the absolute minimum programming time that can be achieved when programming the entire device is: ((202 * 1 * 2 * ) / ) = 84 seconds This is the absolute lowest possible programming time (theoretical) that can be achieved in this situation. In practice (depending on the speed of the computer used, length of the scan chain, etc), this programming time can typically vary from anywhere from 1.4 to 3.3 times this value. Pin Numbers in Board Netlist Must Match the BSDL Files In order for tools for Automatic Test Pattern Generation (ATPG) of boundary-scan test vectors to correctly correlate the pin numbers between the board netlist and the BSDL files for the boundary-scan components used on board, the component pin numbers in the board netlist must exactly match the pin numbers in the BSDL files for the boundary-scan components onboard. Therefore, manufacturer standard pin numbering (when using off-the-shelf components) should be used in the component symbols/models for schematic capture. Page 15 of 31

16 Non-ideal Components Behavior The IEEE standard describes in detail the operation of components that comply to the standard. There are some cases where components comply to the standard only under specified conditions or are not compliant at all. Motorola MPC860 The Motorola MPC860 supports on-chip debugging through a BDM port and also boundaryscan testing through a JTAG TAP. The MPC860 is designed such that the BDM and JTAG functions are shared on the same pins, the function of which are determined at power-up. Following which, the pin functions can be switched (overridden) by writing to an internal MPC860 register (DBPC field in the SIUMCR register). So it is possible that software executing on the MPC860 may change the function of the pins, even though they are JTAG at power-up. The boundary scan TAP is set to boundary-scan during reset. There are three requirements. 1. Set the DBPC bits [12,11] to [1,1] in the Hard Reset Configuration Word (HRCW). This can be done by setting the MPC860 data bus bits 12,11 high during a chip reset. One easy way to implement it is to provide pull-up resistors on the D11 and D12 signals. This way every time that the HRESET# is active (low) the data bus is tri-stated and the signal level on these lines will be 1 because of the pull-up resistors. 2. In addition, the RSTCONF# signal must be active (low) during chip reset to enable the automatic writing of the data bus content into the Hard Reset Configuration Word whenever the chip is being reset (HRESET# asserted, then de-asserted). 3. HRESET# must go inactive with the proper timing relative to PORESET# signal. For more details, please refer to the MPC860 PowerQUICC User s Manual, MPC860UM/AD. In the 07/98, REV. 1 version, see sections 12.3 MPC860 Reset Configuration for a discussion; Table 3-1 Signal Descriptions for a description of the RSTCONF# AND HRESET# pins; 13.3 Internal Pull-Up and Pull-Down Resistors for a description of the internal resistors connected to the data bus pins during reset; Reset Configuration for a description of the ; Table Hard Reset Configuration Word Field Descriptions for a description of the DBPC bits. With the HCRW set for boundary-scan mode, the following multi-purpose pins will be set as noted: TCK/DSCK functions as TCK TDI/DSDI functions as TDI TDO/DSDO functions as TDO Note that the setting of the two data bus bits is different for BDM mode and JTAG mode. If both are to be used, the board designer will need to accommodate both situations. Motorola has recommendations on how to implement that. Remember that if you re not using the data bus explicitly to define the Hard Reset Configuration Word, the default for this word is 0 which means that DBPC bits are not configured for JTAG operation. Page 16 of 31

17 scan testing through a JTAG TAP. The MPC860 is designed such that the BDM and JTAG functions are shared on the same pins, the function of which are determined at power-up. Following which, the pin functions can be switched (overridden) by writing to an internal MPC860 register (DBPC field in the SIUMCR register). So it is possible that software executing on the MPC860 may change the function of the pins, even though they are JTAG at power-up. When using the MPC860 for boundary-scan testing, you need to ensure that the chip is configures such that the shared pins are functioning as JTAG TAP and not BDM. Refer to the MPC860 documentation for additional details. Xilinx Devices There is an IEEE compatibility issue with the Xilinx FPGA chips that requires special considerations. The Xilinx FPGAs (XC4000, XC5000, XCS-Spartan and XCV-Virtex parts) are FULLY boundary-scan compatible only in the following two configuration modes: 1. Before the chip is configured, provided that the INIT* signal was constantly held at '0' - thereby inhibiting configuration. 2. After configuration, if boundary scan is included by the user in the FPGA design (except Virtex parts which are always FULLY boundary scan compatible after configuration is done) Please refer to figure 47, page 4-51 in the 1998 Xilinx Data book (or figure 46, page 6-50 in the 1999 Xilinx Data book). Note that if the chip is in the pre configuration mode and is in the middle of configuring then it is NOT fully boundary-scan compatible (EXTEST instruction not supported because all of the I/O pins are tri-stated). What you need to do is to make sure that the INIT* signal is held permanently low and that the PROG* pin is held high after it was pulsed low at least one time. If the PROG* pin is held low, the Boundary Scan registers for the boundary scan EXTEST operation inside the chip will reset and EXTEST will not work. Releasing PROG*, but holding the INIT* low will halt configuration just as it is beginning. With the INIT* signal held low, the tools will then execute the EXTEST instruction successfully. Suggested Rework Instructions Here is what you need to do to assure that the Xilinx part is boundary-scan compatible. Before you run any of the boundary scan tests implement the following fix to the target board. Turn the target board power OFF. Permanently connect the INIT* signal to ground (low) with a jumper wire. After power is applied to the target board the jumper wire will prevent the INIT* signal from ever going high. Now the Xilinx part is 100% boundary scan compatible. Turn power ON and proceed with the boundary-scan testing. Also, make sure that the PROG* pin of the Xilinx part is high before you run any of the boundary-scan tests. You need to also make sure that the PROG* pin remains high for the duration of the boundary-scan tests. BSDL file Related Fixes Page 17 of 31

18 There are 3 more issue to consider that have to do with the BSDL file. The first issue is that Xilinx provided some BSDL files with all the pin numbers starting with the letter "P". For example, pin numbers for the popular 208 pin PQFP package are numbered P1, P2, P3,... P208. However, these pin numbers are numbered 1,2,3,...,208 in the netlist and therefore ScanPlus TPG is not able to correlate pins in the netlist to pins in the BSDL file. The simple solution is to modify the relevant section of the BSDL file. For example, modify the pin numbers section of the BSDL file from: to: constant PQ208: PIN_MAP_STRING:= "CCLK:P153," & "DONE:P103," & "GND:(P194,P2,P14,P25,P37,P49,P67,P79,P90,P101," & "P119,P131,P142,P160,P171,P182)," & "INIT:P77," & "IO2:P184," & "IO3:P185," & "IO4:P186," & constant PQ208: PIN_MAP_STRING:= "CCLK:153," & "DONE:103," & "GND:(194,2,14,25,37,49,67,79,90,101," & "119,131,142,160,171,182)," & "INIT:77," & "IO2:184," & "IO3:185," & "IO4:186," & The second problem is that the original BSDL files that are found on the Xilinx web specify that even when output pins are tri-stated the output should always read back a "1". This would be true if the Xilinx FPGA was not connected to anything and would rely on the internal weak pullup resistor of each FPGA pin to set the read-back value. However, in the real world, the FPGAs are connected to external devices that may or may not maintain a high "1" level on these pins. To remedy the situation, you need to modify the BSDL file(s) for the Xilinx FPGA parts. Simply replace all "PULL1" statements with "Z". For example, instead of: " 0 (BC_1, *, internal, X)," & Page 18 of 31

19 " 1 (BC_1, *, internal, X)," & " 2 (BC_1, *, controlr, 1)," & " 3 (BC_1, IO239, output3, X, 2, 1, PULL1)," & " 4 (BC_1, IO239, input, X)," & " 5 (BC_1, *, controlr, 1)," & " 6 (BC_1, IO240, output3, X, 5, 1, PULL1)," & " 7 (BC_1, IO240, input, X)," & " 8 (BC_1, *, controlr, 1)," & " 9 (BC_1, IO241, output3, X, 8, 1, PULL1)," & change it to: " 0 (BC_1, *, internal, X)," & " 1 (BC_1, *, internal, X)," & " 2 (BC_1, *, controlr, 1)," & " 3 (BC_1, IO239, output3, X, 2, 1, Z)," & " 4 (BC_1, IO239, input, X)," & " 5 (BC_1, *, controlr, 1)," & " 6 (BC_1, IO240, output3, X, 5, 1, Z)," & " 7 (BC_1, IO240, input, X)," & " 8 (BC_1, *, controlr, 1)," & " 9 (BC_1, IO241, output3, X, 8, 1, Z)," & The third issue is with post-configured parts. The BSDL release contains JTAG behavior in preconfiguration. After configuration, most pins are configured as Input or Output, not a 3-state capable bi-directional pin. In most cases the BSDL file does not need to be altered, however it may become necessary to modify the BSDL files to meet the new configuration. It should be noted that Xilinx recommends that one tests the Xilinx device prior to configuration, since changing the BSDL file is difficult and error-prone. To create a post-configuration BSDL file: 1. Enable USER instructions as appropriate. If you do not use the user instructions, no modifications are needed. If you use either USER1 or USER2, include appropriate entries in the REGISTER_ACCESS description. For more information, consult Supplement (B) to IEEE Std Set disable result of all pads as configured. Page 19 of 31

20 The disable result is the value of the signal when it is disabled. It is specified in the BOUNDARY_REGISTER section of the BSDL file. If pull-up = NO and pull-down = NO, then the disable result value is Z If pull-up = YES and pull-down = NO, then the disable result value is PULL1 If pull-up = NO and pull-down = YES, then the disable result value is PULL0 Unused pads are PULL0 Following are three BSDL code examples of how to modify the BOUNDARY_REGISTER section. For this example, code has been used from Revision: 1.2 of xcv100_pq240.bsd This is the untouched code: attribute BOUNDARY_REGISTER of XCV100_PQ240 : entity is -- cellnum (type, port, function, safe[, ccell, disval, disrslt]) " 0 (BC_1, *, controlr, 1)," & " 1 (BC_1, PAD60, output3, X, 0, 1, PULL0)," & " 2 (BC_1, PAD60, input, X)," & " 3 (BC_1, *, controlr, 1)," & " 4 (BC_1, PAD59, output3, X, 3, 1, PULL0)," & " 5 (BC_1, PAD59, input, X)," & " 6 (BC_1, *, internal, X)," & " 7 (BC_1, *, internal, X)," & " 8 (BC_1, *, internal, X)," & " 9 (BC_1, *, controlr, 1)," & " 10 (BC_1, PAD57, output3, X, 9, 1, PULL0)," & " 11 (BC_1, PAD57, input, X)," & " 12 (BC_1, *, controlr, 1)," & If pin 57 has been configured as a bidirectional pin, no code modifications are required: -- UNCONFIGURED OR BIDIRECTIONAL PIN: " 9 (BC_1, *, controlr, 1)," & " 10 (BC_1, PAD57, output3, X, 9, 1, PULL0)," & " 11 (BC_1, PAD57, input, X)," & If pin 57 is configured an input, then you should modify it as such: -- PIN CONFIGURED AS AN INPUT " 9 (BC_1, *, internal, 1)," & " 10 (BC_1, *, internal, X)," & " 11 (BC_1, PAD57, input, X)," & Page 20 of 31

21 If pin 57 is configured an output, then you should modify it as such: -- PIN CONFIGURED AS AN OUTPUT " 9 (BC_1, *, internal, 1)," & " 10 (BC_1, PAD57, output2, X)," & " 11 (BC_0, PAD57, observe_only, X)," & Repeat these modifications for every configured pin in your design. 3. Set safe state of boundary cells as necessary. The safe bit supplies a value that should be loaded when board-level test generation software might otherwise choose a value randomly (it is not forcing). The safe bit has several example uses: 1. The value in a control cell that turns off its associated drivers; 2. The value that an output should have during INTEST that minimizes driver current; 3. A preferred value to present to on-chip logic at a component input during EXTEST. The control cells (which correspond to the 3-state of the pad) that already have the proper value doesn't need to be changed. The output and input values are design-dependent. Knowledge of the user's application is necessary to set these (can't be automatically done based solely on the.ncd file). 4. Rename entity if necessary to avoid name collisions. If the entity name used in the BSDL file causes a collision with other BSDL or VHDL files, then you must rename the entity. 5. Modify USERCODE value in USERCODE_REGISTER declaration. Fill in the USERCODE value supplied during the BitGen process if using this function. Devices That Do Not Include a Boundary-scan Register Some devices include a JTAG TAP for purposes of in-system programming, but do not include a boundary-scan register for testing. Sometimes you can determine this from the BSDL file for the device or from the datasheet for the device. The Vantis MACH111 falls into this category. When generating test vectors for your board using ScanPlus TPG, the compliance problem field for this device in the board Topology file should be set to YES, indicating that the device should be placed BYPASS and not involved in boundary-scan interconnect and cluster testing. Page 21 of 31

22 Motorola Earlier versions of the Motorola DSP do not support the SAMPLE/PRELOAD instruction. The following DSP56303 silicon masks contain bugs that make them non-compliant with boundary-scan IEEE Std : OF88S OF94R 1F94R OJ22A 2J22A 3J22A 4J22A The following DSP56303 does not list boundary-scan non-compliance in its errata (however you may want to verify this with Motorola before purchasing): OH82G Non-Compliant Lattice Parts There is a known chip problem with some Lattice parts (e.g., isplsigdx160v BGA272). The value of the IR capture of this chip is which is not IEEE compliant. Lattice fixed this problem on production parts and it only exists on engineering samples. Here is what you need to do: 1. User ScanPlus TPG and ScanPlus Runner versions 3.45 or later. 2. Use the correct BSDL file (10110) when generating the infrastructure test. 3. Use the Modified BSDL file (11001) for generating all other tests. 4. When using Runner, under the PROPERTIES menu select the option of "Disable Scan Integrity checks". Everything should not work just fine. Lucent ORCA FPGAs Lucent ORCA FPGA devices use the PRGM pin as a TRST, but it s not called PRGM/TRST, it s just called PRGM. In the description it mentions that asserting PRGM also resets the TAP controller. If you don t happen to notice that, any time that PRGM goes low during a test, it resets the ORCA s JTAG port. So you have to be careful to exclude it from testing so it doesn t accidentally go low. Page 22 of 31

23 IDT 64474/64475/64574/64575 Microprocessors In order for the IDT 64474/64475/64574/64575 processor chips to be fully IEEE compliant and operate according to the BSDL description provided by the manufacturer, the following inputs must be setup as described below: 1. JTAG32 signal must be connected to GND. 2. MASTERCLOCK needs to be running during JTAG operation. 3. VCCOK* has to be asserted (LOW) during JTAG operation. Altera EPM7128ATC and Similar Parts While in boundary scan mode, the device pins are supposed to be fully controlled by the boundary scan logic. This is not the case with some devices from Altera. AT device (specifically the EPM7128ATC) pins will take on the programmed type during JTAG operations. What this means is that if a pin is programmed as open-drain, the pin will remain open-drain even during JTAG operations. Furthermore, Altera pointed out that there is an option to automatically convert (optimize) pins to open-drain if they do not drive. The problem is that now the actual programmed part does not fully comply with the (generic) BSDL file for the device. The simplest solution to the problem is to erase the device prior to executing interconnect or cluster tests. Altera FLEX 6000 Parts The Altera FLEX 6000 family of parts are fully boundary scan compatible in the preconfiguration mode. During configuration the devices are NOT boundary scan compatible. After configuration the devices may or may not be boundary scan compatible, depending on the configuration data option that was selected by the user (when preparing the configuration data using the Altera development tools). In order to perform boundary scan testing on FLEX 6000 devices the nconfig pin of each device must be held LOW ( 0 ). The nconfig pin is a boundary scan compliance enable pin that must be held at 0 to enable boundary scan testing. Page 23 of 31

24 Motorola MPC8260 The Motorola MPC8260 supports has a compliance enable pin that is not properly mentioned in the BSDL file. The PORESET* pin of the Motorola MPC8260 device must be high in order for boundary scan to work properly. Holding this pin high BEFORE and DURING boundary scan testing needs to be accomplished by the actual circuit of the board under test or by forcing the pin to the correct state with external means such as jumpers, probing, etc. Note that a constraint statement in a Constraints file cannot be used to set a compliance enable pin to the correct value BEFORE the test. It can only be used to maintain the signal at the correct state DURING the test. Therefore, even when the PORESET* pin is connected to a boundary scannable output pin and this ouput pin is specified as a FIXED_HIGH constraint in the ScanPlus TPG Constraints file it is not enough because the PORESET* pin MUST be set to the HIGH state even BEFORE the boundary scan test commences. TI 320C6202 DSP Chip The TI 320C6202 DSP chip has two modes of operation: EMULATION mode and Boundary- Scan mode. In order to run boundary-scan interconnect testing the chip MUST be in Boundary- Scan mode. When EMU0/1 are pulled high the device is in Emulation mode and the boundaryscan Instruction (IR) register is 8 bits long. If the EMU0/1 pins are pulled low then the device is in boundary scan mode and the IR register is 4 bits long (as specified in the BSDL file). For boundary scan testing the user needs to make sure that the /TRST pin is pulsed from high to low while the EMU0/1 emulation pins are pulled low. Also, the user must make sure that at least one clock pulse occurs on the TCK signal while the EMU0/1 signals are pulled LOW in order for the device to enter boundary scan mode. Page 24 of 31

25 Lattice s ScanPath Linker Chip The Lattice Semiconductor LSC BSCAN-1 Multiple Scan Port Addressable Buffer ( ScanPath Linker ) device is a low voltage second source alternative to the TI 8997 ScanPath Linker device. Customers often use this device to segment large target boards into several local scan chains where each chain can be enabled or disabled by (ScanPlus TPG) software. This is especially useful for target boards that have multiple configurations with optional parts and optional daughter cards. The user can remove an option without having to worry about breaking the overall card scan chain. The following two figures show a typical implementation of the Lattice ScanPath Linker parts in a 12 TAPs (chains) configuration: ScanPath Linkers Program & Test Chain TDI_ISP ScanPath Linker #1 U88 ScanPath Linker #2 U89 ScanPath Linker #3 U90 P3 TDO_ISP isplsi 2064VE- 100LT44 isplsi 2064VE- 100LT44 isplsi 2064VE- 100LT44 These devices must be configured through the P3 connector prior to using the P2 connector for any of the other chains. Page 25 of 31

26 12 Local Scan Chains (One of 12 shown) ScanPath Linker #1 TDITESTCON U1-U9 P2 TDOTESTCON U88 TDO_CHAIN_0 TDI_CHAIN_0 TDOTESTCON1 TDO U9 U8 U89 U7 TDOTESTCON2 U6 U90 TDI U5 U4 U3 U2 TDOTESTCON U1 In order to improve the local TAPs signal quality make sure to program the Lattice CPLD parts with the slew rate limited I/O pins option. TI MSP430 Family of DSP Chip The TI MSP430 family of low power DSP chips include many varieties of parts, including parts that contain internal Flash memory. While these parts are NOT boundary scan compatible, these parts incorporate a standard IEEE port that is used for Flash memory programming as well as for software debug. The Corelis ScanPlus Flash tools can be used to program MSP430 parts. For example, the MSP430F149 part was programmed on a stand alone TI evaluation kit board. In this configuration the MSP430F149 chip was the only chip in the scan chain. The following restrictions should be noted by the board designer in order to be able to in-system program the Flash memory on the MSP430 chips: Page 26 of 31

27 1. MSP430 series DSP device must the first chip in the scan chain. Additional boundary scan compatible devices can only be placed after the MSP430F149 device and not before it. In other words, the TDI signal of the MSP430F149 must be connected to the boundary-scan header connector that goes to the boundary scan tester. 2. The hardware reset signal must be toggled prior to the start of the Flash programming in order to reset the MSP430 series chip and bring it to a known state. The user can simply connect the reset input of the MSP430 series chip to the ScanPlus Flash External Write signal or alternatively manually reset the chip before starting the programming session. Connecting the reset signal to the boundary scan tester is highly recommended. See the Corelis Application Note, ScanPlus Flash TAP, doc document for further information on the recommended 16 pin header configuration. TI TMS320VC5441 DSP Chip Boundary scan test requires control of the five test access port signals (TMS, TCK, TDI, TDO and TRST) as described in IEEE standard Two additional signals, EMU0 and EMU1/OFF, are used by TI DSPs to provide emulation debug capability through the JTAG test access port. Also, TI uses these signals for scan-based factory tests. During boundary scan tests, EMU0 and EMU1/OFF must be held high while TRST is transitioned from low to high. This operation sets the correct internal test mode for boundary scan test to be performed. EMU0 and EMU1/OFF should be pulled high through a 4.7k ohm pull-up resistor on each pin. The pull-up resistors are connected to the DV DD power supply for the VC5441. Boundary scan ATPG tools should be configured to cycle TRST prior to beginning boundary scan tests to ensure that the device is in the proper test mode. Multi-Chip Modules Boundary Scan compatible Multi-Chip Modules are devices which combine multiple boundaryscan devices onto one module. From the outside it looks like a single device while inside there are multiple chips that are all interconnected on a common substrate and then packaged into a module. No BSDL file can describe such a device as it is a chain of multiple devices, each with each own BSDL file. The solution is to approach this as if the multi-chip module pins are a connector. The multi-chip module is a little plug-in board. Create a netlist or schematic that connects each boundary scan device to the appropriate pin on the multi-chip module. Create the topology file for multi-chip module. Use ScanPlus Merge to combine the multi-chip module with the original design. An example of such a module is the Dallas DS21FF42, which is four DS21Q42 boundary scan devices on one multi-chip module. Page 27 of 31