Gate Estimate. Practical (60% util)* (1000's) Max (100% util)* (1000's)

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1 The Product Brief October 07 Ver. 1.3 Group DN9000K10PCIe-4GL XilinxVirtex-5 Based ASIC Prototyping Engine, 4-lane PCI Express (Genesys Logic PHYs) Features PCI Express (4-lane) logic prototyping system with 2-6 Xilinx Virtex-5 FPGA's - XC5V-1, -2 Genesys Logic GL9714 PCI Express Physical Interface (PCIe GEN1 rev 1.1) - Standard 250 or PIPE interface between PHY and FPGA A 100% FPGA interconnect is single-ended or LVDS Nearly 12M ASIC gates (LSI measure) with 6 s FPGA to FPGA interconnect is single-ended or LVDS - 450Mhz LVDS chip to chip (slightly slower when used single-ended) - Reference designs for integrated I/O pad ISERDES/OSERDES 10x pin multiplexing per LVDS pair - Greatly simplified logic partitioning - Source synchronous clocking for LVDS Main Bus (MB) connects all LX FPGA s (1 signals) Single-ended Auspy models for automatic partitioning 6 separate s (250) - 1 SODIMM for FPGA s A,B,F,D - 2 SODIMM s for FPGA s C - 64-bit data width, 250 operation - PC2- or better Description Overview - Addressing/power to support 4GB in each socket - DDR2 Verilog/VHDL reference design provided (no charge) - data transfer rate: 32Gb/s - Alternate pin compatible memory cards available (consult factory for availability): SRAM: QDR, ASYNC, STD, or PSRAM FLASH DRAM: SDR, DDR1, PSRAM or RLDRAM Mictor Extra Interconnect Eight independent low-skew global clock networks - G0, G1, G2, M48, EXT0, EXT1, FBB, FBE - Three, high-resolution, user-programmable synthesizers for G0, G1, G2 User configurable via CompactFLASH or USB - Global clocks networks distributed differentially and balanced - Three independent single-step clocks - Up to three independent external clock inputs (single-ended or differential) can be injected onto low-skew global clock networks Flexible customization via daughter cards - 3 daughter card locations 0-pin FCI MEG-Array connectors FPGA s D,E,F 93 LVDS pairs + clocks (or 186 single-ended) on all signals with LVDS (900 Mb/s) - Signal voltage set by daughter card (1.2v to 3.3V) - Reset - Supplied power rails (fused): +12v (24W max) +5V (10W max) +3.3V (10W max) - Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x) Fast and Painless FPGA configuration - CompactFLASH, JTAG or USB - Configuration Error reporting - Accelerated configuration readback port for embedded up debug - Accessible from all FPGA s Full support for embedded logic analyzers via JTAG interface - ChipScope, ChipScope Pro 130 status LED s: enough to tan a ll giraffe (LGTA). The DN9000k10PCIe-4GL is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype PCIe-based logic and memory designs for a fraction of the cost of existing solutions. The DN9000k10PCIe-4GL is hosted on a 4-lane PCIe bus, but can be used stand-alone and configured via USB and/or Compact FLASH. A single DN9000k10PCIe-4GL configured with 6 Xilinx Virtex-5, XC5V s can emulate up to 12 million gates of logic as measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASIC s). This number does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available to the user application. The DN9000k10PCIe-4GL achieves high gate density and allows for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGA s can be stuffed along with any combination of speed grades. Virtex5 FPGA Speed Grades (slowest to fastest) Slices or LE's FF's Gate Estimate Max (100% util)* (1000's) Practical (% util)* (1000's) Blocks (18kbits) Memory Total (kbits) Total (kbytes) -1,-2 51,8 7,3 3,3 1,990 1, ,368 1,296 LX2-1,-2 34,5 138,2 2,210 1, , LX110-1,-2,-3 17,280 69,1 1, ,8 576 Max I/O's FF's in I/O pad Multipliers (25x18) 1

2 Block Diagram JTAG Config USB 2.0 (480 Mb/s) COMPACT FLASH config Configuration FPGA Spartan 3 up Config Control MB [35:0] QL FPGA D MB [168:0] FPGA F CLK_FB (from FPGA A) Global Clocks clock config GCLK0 GCLK1 GCLK2 QL5064 FPGA A PIPE Interface GL9714 Genesys Logic 1 FPGA C EXT0 Daughtercard D Daughtercard E Daughtercard F 48 EXT1 MB48CLK PCI Express 4 - lane Yellow (x130) FBB FBE 2

3 JTAG COMPACT FLASH config Configuration FPGA Spartan 3 MB [35:0] FPGA D LX110/LX2 LX110/LX2 FPGA F LX110/LX2 Config USB 2.0 (480 Mb/s) up Config Control MB [168:0] CLK_FB (from FPGA A) Global Clocks clock config GCLK0 GCLK1 GCLK2 FPGA A LX110/LX2 PIPE Interface GL9714 Genesys Logic LX110/LX2 FPGA C LX110/LX2 EXT0 Daughtercard D Daughtercard E Daughtercard F 48 EXT1 MB48CLK PCI Express 4 - lane Yellow (x130) FBB FBE LX110 / LX2 3

4 Virtex-5 FPGA s from Xilinx The DN9000k10PCIe-4GL uses high I/O-count, 17-pin, flip-chip BGA packages from the LX family. A Genesys Logic GL9714 PHY device provides the PCI Express interface. Virtex-5 GTP "RocketIO" is not used. For PCIe applications the user must supply a 1-lane or 4-lane PCIe core in FPGA A. A PCIe power cable is necessary (provided) since a 4-lane PCIe connector cannot provide enough power to satisfy the current-hungry s. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. All pins of all banks of each FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 450+ but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 1-pin main bus (MB) is connected to all FPGA s including the Spartan configuration FPGA. Daughter Cards Three separate 0-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially, and can run at the limit of the FPGA: 450 (900 Mb/s). Clocks, resets, and presence detection, along with abundant power are included in each connector. Memory Six separate sockets are stuffed and have connections to FPGA s A, B, D, F, and C (two separate sets). Each socket is tested to 250 with a. Standard, off-the-shelf DDR2 memory DIMM s (PC2- or better) work nicely and we can provide these for a ll charge. We have developed alternative SODIMM s that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, mictors and others. Easy Configuration Via Compact FLASH or USB The configuration bit files for the FPGA's are copied onto a CompactFLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Visibility into the configuration process is enhanced with an port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. FPGA configuration occurs at the fastest possible SelectMap frequency Multiple LED's provide instant status and operational feedback. As always, reference material such as DDR2 SDRAM controllers, and flash controllers are included (in Verilog, VHDL, C) at no additional cost. Status LED s, Debug Although no animal testing was performed, sophisticated statistical models are showing that the 130 status LED s is enough to tan a ll laboratory giraffe. These LED s are user controllable from the FPGA s so can be used as visual feedback in addition to the lab giraffe-tanning application (LGTA). A JTAG connector provides an interface to Chipscope and other third party debug tools. Other FPGA debug solutions will be available later in 07. 4

5 Front Front Detail 5

6 Back Included Accessories: The For technical applications and sales support, call Group 1010 Pearl Street, Suite #6 La Jolla, CA Phone: Fax: Web: The DINI Group reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. 6