Betrouwbare Elektronica ontwerpen en Produceren

Transcription

1 Betrouwbare Elektronica ontwerpen en Produceren Verbeter betrouwbaarheid, time to market en winstgevendheid met boundary scan JTAG Technologies B.V. Rik Doorneweert

2 Boundary scan Testing HW without firmware and without test pads IEEE 49. Standard since 99 and still evolving A.k.a. JTAG (Joint Test Action Group) 2

3 Adding Boundary scan to a device I/0 I/0 I/0 Boundary-Scan Register I/0 I/0 I/0 Core I/0 I/0 I/0 Bypass TCK TRST Optional Instruction Register TAP Controller TCK TRST Test Data In Test Data Out Test Mode Select Test Clock Test Reset TAP (Test Access Port) (JTAG) 3

4 UPDATE drives the Pins / Tracks Core 0 0 Bypass Update TCK TRST Optional Instruction Register TAP Controller 4

5 CAPTURE senses the Pins / Tracks Core Bypass Capture TCK TRST Optional Instruction Register TAP Controller 5

6 Testing interconnections Testvector xxxx IC Core 0 IC2 Core xx0xx Shift Update Capture Shift Mismatch! TCK Caused by an open underneath this pin 6

7 Testing the resistor presence Serial resistors Power Pull up resistors Pull down resistors Core Logic Core Logic Instruction Register Identification Register 49. TCK TRST Ground Instruction Register Identification Register 49. TCK TRST 206 JTAG Technologies 7

8 Testing through connectors Core Logic DIOS Other board Instruction Register Identification Register 49. TCK TRST 8

9 Testing Memory connections Examples: SRAM Core Logic Memory test DRAM SDRAM Instruction Register Identification Register 49. Need access to: Address bus Data bus DDR2 DDR3 DDR4 Control signals TCK TRST 9

10 Testing connections through combinatorial logic Examples: 0 And Or 0 Nand 0 0. TCK TRST 0

11 Testing connections through sequential logic Examples: ADC / DAC I2C components Clock toggle test SPI components Calibration components RS232 Ethernet chips Interactive applications TCK TRST

12 LVDS Interconnect test Core Logic Core Logic Instruction Register Identification Register 49.6 Instruction Register Identification Register 49.6 TCK TRST TCK TRST 2

13 LVDS Interconnect test C 2 C2 2 R

14 Using Special Bscan Instructions BIST (Built In Self Test) Measure voltages (Zynq/XADC) Core Logic Registers Everything what is supported by the IEEE 49. Device (see BSDL file) Boundary Scan Description Language Instruction Register Identification Register 49. TCK TRST 4

15 Using Debug & IP blocks for testing Peripherals Mem Control I2C Enet Perip. Core Logic Debug Instruction Register Identification Register Other SPI ADC/ DAC uc s: ARM Analog Devices Freescale Infineon Microchip Texas Instruments Xscale FPGA s: Altera Xilinx Actel Lattice TCK TRST NXP ST 5

16 Programming Nand / Nor Flash Core Logic NAND / NOR Flash Instruction Register Identification Register 49. TCK TRST 6

17 Programming uc s Core Logic Flash Instruction Register Identification Register 49. Analog Devices Atmel Cypress Freescale Infineon Microchip Nordic NXP Philips Renesas ST Silicon Labs TI. TCK TRST 7

18 Programming Logic JAM STAPL SVF Jedec Actel Altera Lattice Xilinx IEEE 532 8

19 Summary Capabilities Interconnections between Bscan pins Testing through Connectors Resistors presence; Serial Pull-up / Pull down LVDS connections Emulative testing At speed memory interconnection test Using Embedded instruments ISP of Flash, uc, FPGA s, cpld s What can be used on your design?

20 Definitions.Accessibility via: o Boundary Scan o Connector Pins o Test Points 2.Testability o Is it save to drive a value on an accessible net? 3.Coverage o Which potential production failures will be found by the total test strategy o An error model and example for potential production failures covered by various test methods: 20

21 DFT analysis during schematic stage HW Engineer (Bscan) Test Engineer Schematics? Accessibility? Testability Test Generation? Coverage Layout Layout Engineer 2

22 Check Test possibilities during schematic stage How? o Test development house o Test Analysis tool for various EDA tools 22

23 Test Points? Only If schematic analysis shows that you have o a too low testability o a too slow programing process If so, then add to your schematics: TP Digital <n> <level> TP Analogue <n> <voltage>..and recalculate the testability 23

24 24 Visualize Coverage

25 I m not using it for test because: Boundary scan devices are more expensive FPGA s, uc s, can NOT be purchased without it It adds tracks Only 5 to ~0, but minimizes number of Test Points It adds more work during design Less Test Points placing, Quicker Prototype HW validation Investment in tools Some FOC Tools are on the market, Services, Temp. licenses It is all new to me, I don t have time to learn Training on the job during your design process I only do one complex design per year, learning curve Out source analysis and Test pattern generation Our EMS uses other test methods for electrical test Flying Probe and ICT are more expensive & lower coverage

26 Summary: Benefits using Boundary Scan Testing HW without firmware Minimizes number of design cycles Minimizes number of Test Points Tests are already available during prototype stage High coverage of more complex designs Good failure localization One interface for testing and programming One test & ISP strategy for all product life cycles Simplifies tester configuration and fixture

27 JTAG Technologies B.V. Boschdijk 50, Eindhoven Demo s: o Analysis of schematics with JTAGMaps o Boundary scan Application development station o Boundary scan stand alone production station Hal 0 FHI Test & Meet Paviljoen 0 E 036 Questions?