MPEG-4 Simple Profile Decoder v1.3

Transcription

1 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 DS338 (v1.7) April 14, 2008 Introduction The Xilinx LogiCORE TM IP MPEG-4 Part 2 Simple Profile Decoder core is a fully functional VHDL design implemented on a Xilinx FPGA. The MPEG-4 Decoder core accepts compressed video information and recreates a video image suitable for display, based on the Information Technology Generic Coding of Audio Visual Objects-Part 2 Visual section of the ISO/IEC standard. This document defines one basic MPEG-4 Simple Profile Decoder core with additional characteristics that are part of the basic package. The MPEG-4 Decoder core requires a memory controller to perform motion compensation algorithms, necessitated by the MPEG standard. This document addresses varied requirements with two options: one with a memory controller and one without, designated as two discrete subcores under the same general heading of an MPEG-4 Simple Profile Decoder core. Because of the variety of possible video image resolutions, Xilinx provides netlists for two video resolutions (CIF and 4CIF) for each of the supported FPFA families. Features Supported FPGA families: Supported FPGA families: Virtex -5, Virtex-4, Virtex-II Pro, Virtex- II, Spartan -3, and Spartan-3A MPEG-4 Part 2 Simple Profile standard Maximum frame size for standard TV resolutions IDCT-based transform Macroblock processing 4:2:0 YUV processing Motion compensation Residual processing 8-bit input data 12-bit IDCT coefficients AC/DC prediction Variable length decoder Local YUV buffer Communication primitives Bit-accurate testing I and P Frame Processing Applications This section describes some of the key applications for the MPEG-4 Simple Profile Decoder core. Automotive Today s automobile makers are incorporating the latest technologies into vehicle design, such as Global Positioning Systems (GPS) and collision avoidance systems to allow drivers to see video sequences in real-time and to assist them in making split-second decisions. Video compression technology has become an important part of the auto industry infrastructure, and the MPEG-4 technology enhances the overall video product and data transmission requirements. Industrial and Security MPEG-4 compression algorithms are an excellent resource for applications that require video sequences from multiple locations to be sent to a central location for processing. For example, video sequences captured from a variety of locations within an office building or manufacturing plant can be viewed at a central security control room. Broadcasting MPEG-4 technology provides the broadcast community with an effective way to transmit information in a highly compressed format that can deliver various levels of high-quality video information both inside and outside the studio. The MPEG-4 technology fits in well with the invention of HDTV, because HDTV requires that video signals be compressed and to occupy the same analog channel that existed for SDTV. Military Video surveillance from military aircraft necessitates sending valuable video imagery over wireless communication channels. These types of applications rely strongly on effective video compression techniques that can operate at different resolutions based on the accuracy and image quality required Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. DS338 (v1.7) April 14,

2 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - Video Conferencing MPEG-4 decoding and video compression allows for the transmission of high-quality video to multiple sites in real time, thus reducing travel time and overall business costs. Streaming Video Delivering video information through streaming video is an important aspect of Internet communication. Combining MPEG-4 technology with the host of other Internet technologies enhances the overall Internet experience. Video Messaging Cellular telephone technology has gained a significant share of the consumer market over the last decade and continues to expand into other areas, including video. Because the MPEG-4 Decoder core has the capability to compress low-resolution images very effectively, using the MPEG-4 algorithm in these small-screen applications is a natural choice. Feature Summary MPEG-4 Simple Profile Standard. The MPEG-4 Decoder follows the International Standards Organization document number ISO/IEC :199/Amd.1:2000(E) from the ISO/IEC JTC 1/SC 29/WG 11 Coding of Moving Pictures and Audio group. More information about this document can be found on the MPEG website: Maximum Frame Size for Standard TV Resolution. This core can operate at a maximum resolution of 4CIF (704 by 576) or standard definition as well as resolutions as small as QCIF (176 by 144). The size of the frame directly affects the total amount of on-chip memory, or Block SelectRAMs, required. Inverse Discrete Cosine Transform. The Inverse Discrete Cosine Transform (IDCT) is used to transform an eight-by-eight block of video information from the frequency domain to the spatial domain. It is the exact inverse operation performed in the encoding process of the video stream. When the data is in the frequency domain, the coefficients or residual information can be quantized and efficiently encoded for low bandwidth channels. Macroblock Processing. The MPEG-4 Decoder core operates on a macroblock structure, a basic and important data structure of the MPEG-4 algorithm. The macroblock structure contains YUV information for a particular subsection of the image a 16-pixel by 16-pixel square. Because the chroma data representation of that block of video information is reduced in spatial frequency in both the horizontal and vertical directions, fewer informational pixels are needed for the UV components (1/4 of the luma channel information for each color channel). In other words, a macroblock is comprised of 4 luma channel eight-by-eight blocks, one U channel eight-by-eight block, and one V channel eight-by-eight block representing a 16-pixel by 16-pixel portion of the image. YUV Processing. The structure of the macroblock demands that the processing used in MPEG-4 or MPEG systems necessitates 4:2:0 YUV processing. The color channels sample at exactly half the rate in both the horizontal and vertical directions as they relate to the Y channel. For this reason, for every U and V pixel there are four Y pixels. The spatial relationship among the three channels is documented in many MPEG articles. Motion Compensation. The MPEG-4 Decoder core has been designed with a motion compensation module to accept motion vectors from the compressed bitstream. It uses these vectors to access a locally-stored memory that contains macroblocks of the previously decoded frame. These macroblocks are used as a reference to process on the incoming residual processed data. 2 DS338 (v1.7) April 14, 2008

3 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Residual Processing. Compressed video data that is parsed from the incoming compressed bitstream exists in two forms, motion compensation vectors or residual coefficient data. The residual coefficients are sent to the Texture IDCT module where DC and AC prediction processing occurs, based on picture type and macroblock location. The resulting pixels are sent through a two-dimensional inverse discrete coefficient transform to convert the information back to the spatial domain. The resulting macroblock is added to the addressed motion compensation macroblock before it is sent to the display controller. In addition to the pixel data, control information is also passed along to the display controller on a macroblock basis. 8-Bit Input Data. For 8-bit data, the MPEG-4 decoder warrants that the compressed and encoded input bitstream be supplied in an 8-bit wide byte format. 12-Bit IDCT Coefficients. The Inverse Discrete Cosine Transform (IDCT) uses 12-bit coefficients to maintain internal bit accuracy during the execution of the two-stage separable frequency conversion operation. AC/DC Prediction. The MPEG-4 standard uses different prediction modes of operation to determine the DC and AC initial values or predicted values. The MPEG-4 Decoder core determines which mode to employ, then calculates the appropriate value. The result is then added to the parsed coefficient. Variable Length Decoder. The core receives the compressed bitstream from a source and proceeds to decode and present the information in a discernible manner to the appropriate modules. The decoding process involves an interpretation of variable length code words and the appropriate reconstruction of the video samples, as well as motion vectors. Local YUV Buffer. During the motion compensation process, macroblocks from the previous frame are used to construct the current video image. In fact, the same macroblock can be used to construct of a number of current image macroblocks. For this reason, the MPEG-4 Decoder core has a local buffer that contains a number of macroblocks that can be used multiple times in the motion compensation process. The local buffer concept has been employed to minimize bus bandwidth traffic and provides low latency access to the motion compensation windows. Communication Primitives. The MPEG-4 Decoder core uses a variety of communication primitives (hardware-based memories) to send variable blocks of data among different functional modules. These primitives help create a smooth processing flow between the modules in the design with intermittent outputs. Bit-Accurate Testing. The data generated by the MPEG-4 Decoder core has been compared to the data generated by functional C-model program to ensure bit accurate functionality of the hardware core. I and P Frame Processing. The MPEG-4 structure uses frame differences to create residual macroblocks of information. The MPEG-4 Decoder core adds back the expanded bitstream to the appropriate motion compensated macroblock that was previously stored in an external-frame buffer. MPEG-4 Simple Profile Decoder without Memory Controller The MPEG-4 Simple Profile Decoder provides a set of eight precompiled designs (that include netlists) to support specific modes of operation, as well as the different product families defined in Table 1. The variation to the basic core entity involves changing the image resolution. The eight different types of cores are defined below. The two different resolution modes have been created from the same initial VHDL file but with different generics to define the maximum resolution. The additional cores have been synthesized to support the different Xilinx product families. This MPEG-4 Simple Profile Decoder DS338 (v1.7) April 14,

4 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - core requires an external memory controller interface. A second subcore with an internal memory interface is described in "Write Memory Controller Interface." Table 1: Core Configuration File Name (EDF) Resolution Description MPEG4_SP_Decoder_V4 CIF.edf CIF Low resolution single-stream core for a Virtex-4 device. MPEG4_SP_Decoder_V2P_CIF.edf CIF Low resolution single-stream core for a Virtex-II Pro device. MPEG4_SP_Decoder_S3_CIF.edf CIF Low resolution single-stream core for a Spartan-3 device. MPEG4_SP_Decoder_V2_CIF.edf CIF Low resolution single-stream core for a Virtex-II device. MPEG4_SP_Decoder_V4_4CIF.edf 4CIF High resolution single-stream core for a Virtex-4 device. MPEG4_SP_Decoder_V5_CIF.edf CIF Low resolution single-stream core for a Virtex-5 device. MPEG4_SP_Decoder_V2P_4CIF.edf 4CIF High resolution single-stream core for a Virtex-II Pro device. MPEG4_SP_Decoder_S3_4CIF.edf 4CIF High resolution single-stream core for a Spartan-3 device. MPEG4_SP_Decoder_V2_4CIF.edf 4CIF High resolution single-stream core for a Virtex-II device. MPEG4_SP_Decoder_V5_4CIF.edf 4CIF High resolution single-stream core for a Virtex-5 device. Input Interface The Input interface accepts data from the acquiring or tuning circuit. The incoming data is eight-bits wide. There is an interface protocol that has followed to maintain the integrity of the bitstream. Memory Interface Two memory interface units are included in this design: one that reads data from the memory controller to the locally stored memory that is used for the motion compensation module, and a second one that writes the reconstructed macroblock of the display image to the external memory. This MPEG-4 Decoder subcore requires an external memory controller, based on the type of memory being used. Display Interface The display interface is the output of the MPEG-4 Decoder core. It has two types of outputs, video data and control information. The data output of the MPEG-4 Decoder core is in 4:2:0 YUV macroblocks structure, generated in a raster planar fashion. A complete macroblock is transferred before the next macroblock, immediately following it to the right, is sent. The control information defines the (X, Y) location of the macroblock in relation to the overall picture, as well as defining which block of the six blocks within the macroblock is currently being transferred. This MPEG-4 Decoder core requires an external display controller to accept data from the core and to create the system-specific interface (RGB, digital serial interface). If the control port of the display interface is not used, the enable line must be tied HI. 4 DS338 (v1.7) April 14, 2008

5 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Host Interface The host interface provides the ability to control certain aspects of the MPEG-4 Decoder core using a host processor. When no host is provided, the decoder automatically starts decoding the incoming bitstream. The host interface contains a software reset capability as well as the ability to start the decoding process under CPU control. The user can also monitor the incoming bitstream for types of error conditions that might be occurring. The host interface has the capability to interrupt the host when some abnormal error conditions arise within the bitstream with both a non-maskable and maskable interrupts structure. Common Control This section accepts the external clock and reset signals. It ensures that all signals go to the appropriate modules of the MPEG-4 Decoder core. Functional Description The MPEG-4 Decoder core without a memory controller receives the input samples from a tuner or network interface element that is locking onto a particular channel and extracts the bitstream for a specific channel. That video information is then sent to the MPEG-4 Decoder. The MPEG-4 Part 2 Decoder core uses half-pel resolution motion compensation from the previously reconstructed frame and IDCT-based residual processing. A 16x16 macroblock (MB) is the basic memory unit used in an MPEG-4 system, and is defined as a block of memory with 384 samples. For YUV 4:2:0 video data format, it contains four luma 8x8 pixel blocks, one U chroma channel 8x8 block, and one V chroma channel 8x8 block. This MPEG-4 Decoder core supports 12-bit DCT coefficients (both before and after de-quantization) and 8-bit pixel outputs as well as 8-bit pixel inputs. The memory interface section of the MPEG-4 decoder attaches to an external memory controller via multiple ports on the core in either read or write modes. The memory controller module is the hardware that allocates which port has access to the memory at any given point. The interface to/from the memory controller occurs in a burst mode to simplify interface considerations and speed up memory access times. This control information overhead is transmitted to the controller at power up and is a system-defined parameter. The display interface outputs the decompressed macroblocks from the core in YUV 4:2:0 8-bit format. An external display controller changes the data format from a macroblock processing to a raster type of operation as well as conversion and interpolation of the YUV 4:2:0 signals to the output video format required by the target application (for example, RGB 4:4:4 format). The host interface section allows an external processor or control unit to write to control registers or read status registers embedded in the MPEG-4 Decoder core. There are three writable registers in the host interface used for starting the decoding operation, a software reset operation, and a maskable interrupt register to allow certain conditions to be masked from interrupting the processor. The NMI necessitates a response from the processor to continue the decoding operation. It is used for fatal conditions on the bitstream or for debugging system level problems. The maskable interrupts do not cause the decoding operation to stop. They inform the host processor of an abnormality in the bitstream and to investigate further to determine what conditions are causing the interrupt. There are a number of status registers supported in the host interface that can be addressed to determine conditions causing the interrupts. The interface is an asynchronous interface allowing the processor to operate at a different clock frequency. DS338 (v1.7) April 14,

6 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - The MPEG-4 Decoder core processes a single video frame of information at a time. This allows the Decoder to minimize the amount of on-chip memory storage for state variables and dynamic register values during operation. The control section of the system architecture has the clock generation circuitry and global reset and start signals. Figure 1 illustrates the interfaces to the major functional blocks of the MPEG-4 Decoder core and their internal connections. Notice that the major functions described in the MPEG standards document are present in this diagram. X-Ref Target - Figure 1 from Memory Controller to Memory Controller Copy Controller from/to Host Host Interface Shared Memory from Data Source Input Interface Parser FSM Parser/VLD Motion Compensation Pred IDCT Texture_IDCT Texture_Update to Display Logic Figure 1: MPEG-4 Decoder without Memory Controller 4CIF and CIF Interfaces Figure 2 shows the interface signals of both a 4CIF and a CIF MPEG-4 Decoder core without a memory controller. The difference between a 4CIF MPEG-4 Decoder core and a CIF MPEG-4 Decoder core is the amount of local memory needed in the shared memory block. However, the pinouts and their functionality are the same for these two types of subcores. The input interface of the MPEG-4 Decoder core accepts signals from a data provider element. The provider verifies that the core is capable of accepting data samples by monitoring the dec_in_afull signal from the core. Once established that the core can accept information, data is transferred to the input interface section over the data bus and control signals to ensure that no data is lost. The display controller interface is the output section of the MPEG-4 Decoder core that sends the reconstructed video information to an external display controller. Data is sent over an 8-bit data bus along with the control information that defines the current block within the macroblock, and the position of the macroblock within the image. When active, the data bus contains the current block data in a raster format the first row of eight samples followed by the next row of samples. The first four blocks are luma. The first block of the macroblock is displayed as block 0 (the top rightmost block), followed by block 1 (to the immediate right), block 2 (below block 0), and then block 3 (to the right of block 2). The next block transmitted is block 4, which contains the U chroma information, and then block 5 (containing the V chroma information) is sent. 6 DS338 (v1.7) April 14, 2008

7 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 X-Ref Target - Figure 2 clk reset dec_in_d[7:0] dec_in_id dec_in_afull dec_in_aempty ms_stnum[3:0] ms_stnum_ld Input Interface Display Controller Interface dc_dout[7:0] dc_we dc_enbl dc_ctrl_write dc_ctrl_enbl dc_ctrl_dout[14:0] dc_stnum[3:0] wqo_full wqo_afull rq0_job_ad[31:0] rq0_job_push wqo_wcnt[6:0] wqo_werr wqo_wad[31:0] wqo_wbx[4:0] wqo_flush Write to Memory Controller Interface Read from Memory Controller Interface rq0_flush rq0_pop rq0_job_full rq0_job_err rq0_rcnt[6:0] wqo_push rq0_rd[31:0] rq0_empty rq0_ae rq0_rerr host_ce host_re host_we host_address[5:0] host_din[31:0] host_int_ack Host Interface host_int host_nmi host_re_ack host_dout[31:0] Figure 2: MPEG-4 Simple Profile Decoder Interface Signals ds338_02_ The write-to-memory controller interface sends reconstructed video image information to be used for the memory compensation portion of the design. The information is sent in small bursts to maximize memory bandwidth. The information is preceded with a memory address identified by the control bus that is associated with the data bus. The read-from-memory interface retrieves a portion of the reconstructed image that is used in the motion compensation module. Once the starting address of the memory buffer is known, this section determines what part of the memory it has to read to get the appropriate macroblock. It has a similar interface as the write-to-memory controller where the address is sent to the memory controller and the appropriate data is sent in burst to the core. The MPEG-4 Decoder core has a user-supplied external memory controller that allows freedom to choose any memory as well as the needed interfaces. Later in this document is a description of a subcore that has a memory controller built into the decoding process. DS338 (v1.7) April 14,

8 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - The host interface has a number of registers that can be accessed by a host processor. It needs a chip enable signal to signify that an operation is being requested a write enable signal for a write operation and a read enable signal for a read operation. It also uses an address bus to select one of the registers within the host interface. It has 32-bit data buses to and from the host interface. It has a read acknowledge signal to confirm that the addressed read information has been properly placed on the output data bus. There are two interrupts generated by the host interface one is a non-maskable interrupt used for severe conditions and the other is a maskable interrupt controlled by the host via a maskable register. After an interrupt has occurred, the host interface stays in a particular state until the host sends an interrupt acknowledge signal to resynchronize the MPEG-4 Decoder core. The host should keep the host chip enable signal active for the duration of the operation. For read operations, the chip enable should be active until a read acknowledge signal has been sent by the host interface. The common control section of the core accepts a single clock that is sent to all of the processing modules in the MPEG-4 Decoder core. It also needs a synchronous clear signal to reset all modules and to initiate the decoding process. All signals in this design use active HI signals unless otherwise indicated. Common Interface Table 2 defines the signals common to the MPEG-4 Decoder core. Table 2: Common Interface Signals Name Direction Description CLK Input MPEG-4 Decoder Clock: All systems and interface operations are synchronous to this clock. RESET Input MPEG-4 Decoder Sync Clear: Clear signal that resets all internal states to a known state. Input Interface Table 3 defines the MPEG-4 Decoder core input interface signals. The input interface connects to the provider of the compressed video bitstream. The input bus is directed to the input FIFO where signals are monitored to ensure that the FIFO does not overflow, thereby losing data bits and causing potentially catastrophic results. The size of the input FIFO is 2048 words deep. Figure 3 illustrates the signal relationships. Table 3: Input Interface Signals Name Direction Description DEC_IN_D[7:0] Input Decoder Input Data Bus: An 8-bit input bus supplying the compressed video bitstream. DEC_IN_LD Input Decoder Input Load Signal: The load signal to the decoder that loads a byte of information into the decoder at the next clock edge. 8 DS338 (v1.7) April 14, 2008

9 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Table 3: Input Interface Signals (Cont d) Name Direction Description DEC_IN_AFULL Output Decoder Input Almost Full Signal: Indicates to the source of the compressed bit-stream that the decoder is no longer capable of accepting data, that is, DO NOT SEND any more data. DEC_IN_AEMPTY Output Decoder Input Almost Empty Signal: Notifies the source of the compressed bit-stream that the internal FIFO decoder is almost empty and can accept more data. The size of the internal FIFO is 2048 words. X-Ref Target - Figure 3 clock reset dec_in_d[7..0] 80xh 81xh dec_in_id dec_in_afull dec_in_aempty Figure 3: Input Interface Timing Diagram Display Controller Interface Table 4 defines the MPEG-4 Decoder core display controller interface signals. The Decoder core sends the reconstructed image to the display controller, a module external to the core. The data is in macroblocks and is presented in a raster format. The top right-most macroblock is presented first, followed by the one to the immediate right, and so forth for the entire line of macroblocks. Immediately following the first line is the first macroblock of the second line of macroblocks. Along with each macroblock is control information that describes parameters for the current macroblock. Table 4: Display Controller Interface Name Direction Description DC_ENBL Input Decoder Display Controller Enable: An enable signal from an external display controller that informs the Decoder that it is ready for data. DC_DOUT[7:0] Output Decoder Display Controller Output Bus: Supplies the display video information in a 4:2:0 macroblock format. DC_WE Output Decoder Display Controller Write Enable: Write signal to the display controller that indicates data when active. DC_CNTL_ENBL Input Decoder Display Controller Control Word Enable Signal: Signal to the Decoder from the Display Controller to indicate readiness to accept the control word of the current macroblock. DC_CNTL_WRITE Output Decoder Display Controller Control Word Write Signal: Signal to the Display Controller to allow the data to be latched at the next active clock edge. DS338 (v1.7) April 14,

10 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - Table 4: Display Controller Interface (Cont d) Name Direction Description DC_CNTL_DOUT[14:0] Output Decoder Display Controller Control Data Bus: The data bus containing the control word for the current macroblock to the Display Controller. See Table 5. DC_STNUM[3..0] Output Decoder Display Stream Number: Supplies the display video information about what stream number is being generated. The signal is active at the completion of the first burst transfer for the first MB of the current frame. Table 5 defines the control information that is sent to the display controller, which then defines the bits in the control word. The control information defines which block of the six different types of blocks within a macroblock is currently being transmitted. It also gives the macroblock location within the video image using X and Y coordinates. Table 5: Display Controller Control Word Definition DC_CTRL_DIN Output 14:12 11:6 5:0 Block Number MB position (Y value) MB position (X value) Figure 4 illustrates a timing diagram for the data being sent from the MPEG-4 Decoder core to the display controller. It also shows the accessibility of the control word to the user and the interactivity of the data transfer. clock DC_enbl DC_we DC_dout[7:0] XXXXxh data(a) data(b) data(n) XXXXxh XXXXxh DC_entl_enbl DC_cntl_write DC_cntl_din[14:0] XXXXxh Figure 4: Display Controller Timing Diagram Figure 5 illustrates how the display controller output section can be simplified by adding components to the core to put the control data register with the data into a combined bus structure. The external control unit monitors the control write signal an indication that the MPEG-4 Decoder core is ready to send information to the display controller. Control information is then latched into the external register. The video data can be sent to a FIFO with a control unit monitoring FIFO status to ensure that it can store information. The control unit can then combine the two pieces of information onto a multiplexed bus, with additional valid signals defining when control or data is being supplied on the bus. This is another approach to interface to the MPEG-4 Decoder core. Note that the illustration in Figure 5 is not included in the core; it is a proposed approach to interface to the decoder output, if desired DS338 (v1.7) April 14, 2008

11 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 dc_enbl dc_cntl_enbl Control cntl_valid data_valid MPEG-4 Decoder Core dc_we dc_dout[7:0] we d afull FIFO re q sel MUX data_bus dc_cntl_write dc_cntl_din[14:0] ce d Register q Memory Interface Figure 5: Display Controller Output FIFO Structure Option Write Memory Controller Interface This section defines the signals that interface the external memory controller to the section of the MPEG-4 Decoder core to supply an expanded video frame that is used by the motion compensation process. The address data is sent to the memory controller in 32-bit words, along with a 5-bit control bus. Table 6 defines the MPEG-4 Decoder core write memory controller interface signals. Table 7 identifies the significance of the control bus. The control information indicates the presence of an address or data on the address data bus, and the number of valid data bytes. The information is sent in bursts in order for effective bus bandwidth architecture. Table 6: Write Memory Controller Interface Signals Name Direction Description WQ0_FULL Input Memory Controller Write Full: Signal that tells the Decoder that the write FIFO in the memory controller is full and cannot accept any more data. WQ0_AFULL Input Memory Controller Write Almost Full: Signal that tells the Decoder that the write FIFO in the memory controller is almost full. It has space available only to complete the current block. No additional transactions should occur after the completion of the current block until the AFULL line goes inactive. WQ0_WCNT[6:0] Input Memory Controller Write Count: Number of 16-byte bursts currently in Write FIFO. WQ0_WERR Input Memory Controller Write Error: Write FIFO error. WQ0_WAD[31:0] Output Memory Controller Write Data Bus: Write address / data multiplexed. DS338 (v1.7) April 14,

12 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - Table 6: Write Memory Controller Interface Signals (Cont d) Name Direction Description WQ0_WBX[4:0] Output Memory Controller Write Control Bus: Write byte enables/address tag (see Table 7). WQ0_FLUSH Output Memory Controller Write Flush Signal: Flush write FIFO (asynchronous). WQ0_PUSH Output Memory Controller Write Push Signal: Push contents of WQ0_WAD and WQ0_WBX to write FIFO. Table 7: Control Word (WBX) Definitions WBX Address present on WAD 1 X X X 0 Reserved 1 X X 0 X Reserved 1 X 0 X X Reserved 1 0 X X X Reserved bit Data Word End of Data (short burst indicator) Write requests by the user interface (the core) to the memory controller follow a queuing protocol. Each user write port, WQn, sends either a data or an address word to its queue over the set of WAD, WBX, and PUSH signals. Figure 6 shows a sample write transfer. To begin a transfer to external memory, assert the PUSH signal and then set the address on WAD and the appropriate code in the WBX signals (indicated by a highlighted segment). Each subsequent cycle where PUSH is asserted should have data words on the WAD bus, and the appropriate byte enable settings in the WBX. The user can then issue data into the write queue at its own rate, taking wait states as necessary. While pushing data on to the queue, be mindful of the queue status signals: FULL, AFULL, WCNT, and WERR. If data is pushed onto a full queue, the WERR flag asserts. WCNT updates to keep a count of the number of four word bursts currently in the queue. Clock WQn_PUSH WQn_WAD Address Data Data Data Data WQn_WBX WQn_FULL WQn_AFULL WQn_WERR Figure 6: Write Memory Operation Timing Diagram 12 DS338 (v1.7) April 14, 2008

13 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Read Memory Controller Interface This section describes the signals that interface the external memory controller to the section of the MPEG-4 Decoder core supplied with portions of the previous video frame needed for the motion compensation process. The pre-determined macroblock address is derived and sent to the memory controller to gather the appropriate macroblock information in a 32-bit data word, similar to the write process defined in "Write Memory Controller Interface." Table 8 defines the MPEG-4 Decoder core read memory controller interface signals. Table 8: Read Memory Controller Interface Signals Name Direction Description RQ0_JOB_FULL Input Memory Controller Read Full: read job queue full. RQ0_JOB_ERR Input Memory Controller Read Error Signal: read job queue error that goes active if a reset request is made when the job queue is full. RQ0_RCNT[6:0] Input Memory Controller Read Count: number of 16-byte bursts in Read FIFO. RQ0_RD[31:0] Input Memory Controller Read Bus: read data. RQ0_EMPTY Input Memory Controller Read Empty: read empty. RQ0_AE Input Memory Controller Read Almost Empty: read almost empty (programmable threshold). RQ0_RERR Input Memory Controller Read Error: read error. RQ0_JOB_AD[31:0] Output Memory Controller Read Address Bus: read job address. RQ0_JOB_PUSH Output Memory Controller Read Data Signal: push job onto read job queue. RQ0_FLUSH Output Memory Controller Read Flush Signal: flush all read traffic. RQ0_POP Output Memory Controller Read Pop Signal: pop read queue. Read transfers are initiated by issuing an address to the job queue of the read port. Set the address for the read request with RQ0_JOB_AD and assert the RQ0_JOB_PUSH signal. as shown in Figure 7. The user cannot push an address onto the job queue if the RQ0_JOB_FULL flag is asserted. The RQ0_JOB_ERR signal asserts High in this case. After a number of cycles, the read queue EMPTY flag deasserts (logic zero), indicating data is now present for retrieval. When the almost empty (AE) flag is deasserted, there are at least the number of data words (to which the almost threshold was set) present in the queue. The RCNT signal also indicates the number of eight-word bursts available in the queue. When the core asserts its POP signal, the number of data words (set in the read port s burst length register) from the start address is delivered at each subsequent clock cycle, while POP remains asserted. If the Decoder core deasserts POP, the FIFO does not deliver data to the next cycle. In this way, the Decoder core can control the rate at which data is taken from the FIFO. The Decoder core keeps track of the length of the burst and popping the correct number of data words from the queue to reconstitute its memory request. The Decoder core can queue multiple job address requests, but must keep track of the words that are returned. The read queue does not flag data returned as being from different jobs. However, jobs are processed in order. The core must keep a running total of the returned data to determine the address range it belongs to. The core cannot POP from an EMPTY queue; the RERR will be asserted in this event. DS338 (v1.7) April 14,

14 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - Clock RQn_JOB_AD RQn_JOB_PUSH RQn_EMPTY RQn_POP RQn_AE RQn_RD Data Data Data Data Host Interface Figure 7: External Memory Data Read Timing Table 9 defines the MPEG-4 Decoder core host interface signals. In the MPEG-4 Simple Profile Decoder v1.1 version of the core, the host interface is disabled and will be implemented in future releases. The current version decoder is in the start decoding operation automatically, after the reset signal is pulsed. The MPEG-4 Decoder core host interface works with a host processor that can send and receive information to and from the decoder core. The data is transmitted asynchronously since the processor could be running on a different clock cycle. There are chip enable signals to indicate that the host interface is being accessed in either a write or read mode. Registers that exist with their respective addresses and bit definitions are also defined. The interface supports two levels of interrupts to define the state of the Decoder. The maskable interrupt tells the host that something has occurred on the Decoder, but the decoder continues to parse the incoming bitstream. The condition that caused the interrupt is stored in a FIFO on the host interface and is accessible to the host as defined by the associate register mapping table. Every time the FIFO is read, the information ceases to be stored on the FIFO. Table 9: Host Interface Signals Name Direction Description HOST_CE Input Host Interface Chip Enable: Enable signal from an external host that informs the Decoder host interface section of the core to prepared for a read or write operation. HOST_WE Input Host Interface Write Enable: Write enable signal to the host interface that defines a write operation is taking place to the register addressed by the address bus. HOST_RE Input Host Interface Read Enable: Read enable signal to the host interface that defines a read operation is taking place to the register addressed by the address bus. Once a read has taken place, it is confirmed by a read acknowledgement signal. HOST_ADDRESS[5:0] Input Host Interface Address Bus: A six-bit address bus that contains the address of the register being selected for the read or write operation. It is used with the input or output data buses to write or read to a register DS338 (v1.7) April 14, 2008

15 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Table 9: Host Interface Signals (Cont d) Name Direction Description HOST_DIN[31:0] Input Host Interface Data Input Bus: The 32-bit data bus used to deliver data to one of the host interfaces registers. HOST_INT_ACK Input Host Interface interrupt acknowledge: Signal to the Host Interface that confirms that the interrupt has been processed. HOST_RE_ACK Output Host Interface Read Acknowledge: Signal from the host interface to the hot that states that the read operation has been completed and the data is on the data output bus. HOST_NMI Output Host Interface Non-Maskable Interrupt: Non-maskable interrupt signal to the host. HOST_INT Output Host Interface Interrupt Signal: Maskable interrupt signal to the host. HOST_ DOUT[31:0] Output Host Interface Data Output bus: The 32-bit data bus used to send data to the host from one of the host interfaces registers. Figure 8 illustrates a write to the internal decoder core registers. The registers are selected with the host address signal and delivered to the register via the data bus. Note that the host processor might be on another clock source, so the length of the chip enable and write enable signals should overlap the decoder clock to ensure the data has encountered a decoder clock edge. clock host_ce host_we host_address valid data valid data host_din Figure 8: Host Interface Register Write Timing Diagram DS338 (v1.7) April 14,

16 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - Figure 9 shows a read operation between the host and the host interface. The host interface activates a read acknowledgement signal to indicate to the host that the read data has been placed on the output bus. clock host_ce host_re host_address host_dout host_re_ack Figure 9: Host Interface Register Read Timing Diagram Figure 10 illustrates the effect of an interrupt (either masked or non-maskable) sent to the host. In this example, the MPEG-4 Decoder core remains in that condition until the interrupt is acknowledged. After acknowledgement, the MPEG-4 Decoder core returns to normal operation. The NMI signal warrants immediate attention because the decoder might stop operation. The maskable interrupt also requires attention to determine the cause of the interrupt, which does not stop the decoding process, but indicates an abnormality in the bitstream. This type of interrupt is an indication of a condition not currently supported by the core. clock host_int host_int_ack host_nmi Figure 10: Host Interface Interrupt Table 10 defines the host interface registers, their addresses, their read and write ability (R/W), and the number of bits within the register. Table 10: Host Interface Register File Mapping Parameter Register name Address R/W Bits Description Start Register 0 R/W 1 Bit that enables the decoder to start parsing Reset Register 1 R/W 2 Software reset and parser reset bit Mask Register A 2 R/W 8 Contains eight mask able error codes Mask Register B 3 R/W 8 TBD 16 DS338 (v1.7) April 14, 2008

17 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Table 10: Host Interface Register File Mapping (Cont d) Parameter Register name Mask Register C 4 R/W 8 TBD Mask RegisterD 5 R/W 8 TBD Done register 6 R 16 Contains the 16 bit error bus Error Count Register 7 R 16 Contains the number of error codes in the FIFO as well as the FIFO full flag FIFO Data 8 R 16 The port that reads the contents of the FIFO State Machine status Time Code Register Lower Time Code Register Lower Address R/W Bits Description 9 R 2 Register that contains the status of the Host Interface state machine 10 R 16 The current time code value, lower 16 bits 11 R 2 The current time code value, upper 2 bits Table 11 contains additional details of the host interface register set. The start register must be set to HI to start the decoding process. The decoder automatically sets this bit to HI on reset, and can be user-disabled. DS338 (v1.7) April 14,

18 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - Table 11: Host Interface Register Bit Definitions Start Register 15:1 0 Reserved Start Parser Bit Reset Registers 15:2 1 0 Reserved Parser Reset Bit SW Reset Bit Mask Registers 15: Error Count Error H Error G Error F Error E Error D Error C Error B Error A Done Register 15:0 Error code during done signal Error Count Register :6 5:0 FIFO Full Flag FIFO Empty Flag Not Used Error Count Value FIFO Data Register 15:0 Error code during done signal State Machine Status Register 15:2 1: State Machine Code Time Code Lower Register 15:0 Time Code Bits 15 through 0 Time Code Higher Register 15:2 1: TC Bits 17 through DS338 (v1.7) April 14, 2008

19 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Table 12 defines the error codes found in the Done Register and the FIFO Data Register. Table 12: Error Code Definitions ERROR_CODE[7:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0xFF Definition No error found VO/VOL start codes not found VOP start code not found (resynchronization issued) Illegal or unsupported parameter in VOL header Error coding MCBPC in MB header Inter MB found in I-VOP Error reading CBPY code Error position BB-1 in DCT variable length decoding Reserved for future use MPEG-4 Simple Profile Decoder Core with Memory Controller The MPEG-4 Simple Profile Decoder core with memory controller provides a set of eight netlists that have a ZBT memory controller built in to support CIF and 4CIF image resolutions, as well as different product families. Table 13 details these configurations. Variations to the basic core involve changing the image resolution. Two different modes for image resolution have been created from the same initial VHDL file, but with different generics to define maximum resolution. Additional cores have been synthesized to support different Xilinx product families. The MPEG-4 Decoder core supplies the ZBT memory output data bus a memory input data bus as well as an output enable signal. The TRI-state operation is to be performed by the user in the top-most level of the complete system design of the FPGA. Table 13: Core Configuration with Memory Controller File Name (EDF) Resolution Description MPEG4_SP_Decoder_V4_CIF_wMEM.edf CIF Low resolution single stream core for a Virtex-4 device. MPEG4_SP_Decoder_V2P_CIF_wMEM.edf CIF Low resolution single stream core for a Virtex-II Pro device. MPEG4_SP_Decoder_S3_CIF_wMEM.edf CIF Low resolution single stream core for a Spartan- 3 device. MPEG4_SP_Decoder_V2_CIF_wMEM.edf CIF Low resolution single stream core for a Virtex-II device. MPEG4_SP_Decoder_V5_CIF_wMEM.edf CIF Low resolution single stream core for a Virtex-5 device. MPEG4_SP_Decoder_V4_4CIF_wMEM.edf 4CIF High resolution single stream core for a Virtex-4 device. MPEG4_SP_Decoder_V2P_4CIF_wMEM.edf 4CIF High resolution single stream core for a Virtex-II Pro device. MPEG4_SP_Decoder_S3_4CIF_wMEM.edf 4CIF High resolution single stream core for a Spartan- 3 device. DS338 (v1.7) April 14,

20 MPEG-4 Simple Profile Decoder v1.3 - THIS IS A DISCONTINUED IP CORE - Table 13: Core Configuration with Memory Controller (Cont d) MPEG4_SP_Decoder_V2_4CIF_wMEM.edf 4CIF High resolution single stream core for a Virtex-II device. MPEG4_SP_Decoder_V5_4CIF_wMEM.edf 4CIF High resolution single stream core for a Virtex-5 device. Input Interface The input interface accepts data from the acquiring or tuning circuit. The incoming data is 8-bits wide. An interface protocol must be followed to maintain the veracity of the bitstream. ZBT Memory Interface The MPEG-4 Decoder core has been designed with a memory controller. This controller is used to send and retrieve the macroblock information used in motion compensation processes. The core supplies two data buses, one for input and one for output. It also includes an output enable signal that is connected to a bi-directional bus structure by the user at the highest level of the system design. The TRI_State buffer resides in the IOB module of the design. Display Interface The display interface is the output of the MPEG-4 Decoder core. It has two types of outputs: video data and control information. The data output of the MPEG-4 Decoder core is in 4:2:0 YUV macroblocks and is generated in a raster planar fashion. A complete macroblock is transferred before the next macroblock (immediately following it to the right) is sent out. The control information defines the X, Y location of the macroblock in relation to the overall picture, and defines which block of the six blocks within the macroblock is currently being transferred. This MPEG-4 Decoder core requires an external display controller to accept data from the core and create the system specific interface (that is, RGB, digital serial interface). If the control port of the display interface is not used, the enable line must be tied HI. Host Interface The host interface provides the ability to control specific aspects of the MPEG-4 Decoder core using a host processor. If no host is provided, the core automatically starts decoding the incoming bitstream. The host interface contains a software reset capability and the ability to start the decoding process under CPU control. It also provides the capability to monitor the incoming bitstream for the types of error conditions that might be occurring. The host interface has the capability to interrupt the host when some abnormal conditions arise within the bitstream with both a non-maskable and maskable interrupts structure. Common Control File Name (EDF) Resolution Description This section accepts the external clock and reset signals. It ensures that all signals go to the appropriate modules of the MPEG-4 Decoder core DS338 (v1.7) April 14, 2008

21 - THIS IS A DISCONTINUED IP CORE - MPEG-4 Simple Profile Decoder v1.3 Functional Description The MPEG-4 Decoder core with a memory controller receives the input samples from a tuner or network interface element that is locking onto a particular channel and extracts the bitstream for a specific channel. That video information is then sent to the MPEG-4 Decoder core along with a stream number or channel selection. The MPEG-4 Part 2 Decoder core uses half-pel resolution motion compensation from the previously reconstructed frame and IDCT-based residual processing. A 16x16 macroblock (MB) is the basic memory unit used in an MPEG-4 system, and is defined as a block of memory with 384 samples, YUV 4:2:0 video data format. It contains four luma 8x8 pixel blocks, one U chroma channel 8x8 block, and one V chroma channel 8x8 block. The MPEG-4 Decoder core supports 12-bit DCT coefficients (both before and after de-quantization) and 8-bit pixel outputs as well as 8-bit pixel inputs. The ZBT memory interface section of the MPEG-4 decoder has a built-in memory controller. It interfaces to an external ZBT memory with the host of control signals and the input and output buses. The core is supplying the output bus and the input bus as well as an output enable signal. The user combines the two buses into a single bidirectional bus that the ZBT memory requires. The display interface outputs the decompressed macroblocks from the core in YUV 4:2:0 8-bit format. An external display controller is responsible for changing the data format from a macroblock processing to a raster type of operation, as well as conversion and interpolation of the YUV 4:2:0 signals to the output video format required by the target application (for example, RGB 4:4:4 format).the MPEG-4 Decoder core processes a single video frame of information at a time. This minimizes the amount of onchip memory storage required for state variables and dynamic register values during operation. The control section of the system architecture contains the clock generation circuitry and global reset signals. Figure 11 illustrates the interfaces to the major functional blocks of the MPEG-4 Decoder core and their internal connections. The major functions described in the MPEG standards document are also present. A memory controller is included inside the Decoder core block diagram. DS338 (v1.7) April 14,