CCB is ON Semiconductor s original format. All addresses are managed by ON Semiconductor for this format.

Transcription

1 Ordering number : ENA39 LC7886PW CMO C /4 and /3-Duty LCD Display Driver with ey nput Function Overview The LC7886PW is /4 duty and /3 duty LCD display driver that can directly drive up to 224 segments and can control up to general-purpose output ports. This product also incorporates a key scan circuit that accepts input from up to 3 keys to reduce printed circuit board wiring. Features ey input function for up to 3 keys (A key scan is performed only when a key is pressed.) /4 duty /3 bias and /3 duty /3 bias drive schemes can be controlled from serial data. Capable of driving up to 224 segments using /4 duty and up to 7 segments using /3 duty. witching between key scan output and segment output can be controlled from serial data. The key scan operation enabled/disabled state can be controlled from serial data. witching between segment output port and general-purpose output port can be controlled from serial data. witching between general-purpose output port, clock output port, and segment output port can be controlled from serial data. (Up to general-purpose output ports and up to one clock output port) erial data /O supports CCB format communication with the system controller. (upport 3.3V and V operation) leep mode and all segments off functions that are controlled from serial data. The frame frequency of the common and segment output waveforms can be controlled from serial data. witching between RC oscillator operating mode and external clock operationg mode can be controlled from serial data. Direct display of display data without the use of a decoder provides high generality. Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. RE pin provided for forcibly initializing the C internal circuits. CCB is ON emiconductor s original format. All addresses are managed by ON emiconductor for this format. CCB is a registered trademark of emiconductor Components ndustries, LLC. emiconductor Components ndustries, LLC, 23 July, 23 39HM No.A39-/36

2 pecifications Absolute Maximum Ratings at Ta = 2 C, V = V LC7886PW Parameter ymbol Conditions Ratings Unit Maximum supply voltage V DD max V DD -.3 to +7. V nput voltage Output voltage Output current V N,,, RE -.3 to +7. V N 2 OC, TET, V DD, V DD 2, to -.3 to V DD +.3 V OUT -.3 to +7. V OUT 2 OC, to 7, COM to COM4, to 6, P to P -.3 to V DD +.3 OUT to 7 3 μa OUT 2 COM to COM4 3 OUT 3 to 6 OUT 4 P to P Allowable power dissipation Pd max Ta=8 C 2 mw Operating temperature Topr -4 to +8 C torage temperature Tstg - to +2 C V V ma tresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = -4 to +8 C, V = V Parameter ymbol Conditions Ratings min typ max upply voltage V DD V DD V nput voltage nput high level voltage nput low level voltage Recommended external resistor for RC oscillation Recommended external capacitor for RC oscillation V DD V DD 2/3V DD V DD V V DD 2 V DD 2 /3V DD V DD V H,,, RE.4V DD 6. V H 2 to.6v DD V DD V V H 3 OC: External clock operating mode.4v DD V DD V L,,, RE.2V DD V L 2 to.2v DD V V L 3 OC: External clock operating mode.2v DD R OC C OC OC: RC oscillation operating mode OC: RC oscillation operating mode Unit 39 kω pf Guaranteed range of RC oscillation f OC OC: RC oscillation operating mode khz External clock operating frequency f C OC: External clock operating mode [Figure4] External clock duty cycle D C OC: External clock operating mode [Figure4] khz 3 7 % Data setup time t ds, [Figure2], [Figure3] 6 ns Data hold time t dh, [Figure2], [Figure3] 6 ns wait time t cp, [Figure2], [Figure3] 6 ns setup time t cs, [Figure2], [Figure3] 6 ns hold time t ch, [Figure2], [Figure3] 6 ns High level clock pulse width t φh [Figure2], [Figure3] 6 ns Low level clock pulse width t φl [Figure2], [Figure3] 6 ns Rise time t r,, [Figure2], [Figure3] 6 ns Fall time t f,, [Figure2], [Figure3] 6 ns output deley time t dc R PU =4.7kΩ C L =pf * [Figure2], [Figure3] rise time t dr R PU =4.7kΩ C L =pf * [Figure2], [Figure3] Note: * ince the pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance.. μs. μs No.A39-2/36

3 Electrical Characteristics for the Allowable Operating Ranges Ratings Parameter ymbol Pin Conditions min typ max Hysteresis V H,,, RE.3V DD V H 2 to.v DD Unit V Power-down detection voltage V DET V nput high level current nput low level current H,,, RE V =6.V. H 2 OC V =V DD : External clock. operating mode L,,, RE V =V -. L 2 OC V =V: External clock -. operating mode nput floating voltage V F to.v DD V Pull-down resistance RPD to V DD =.V 2 kω Output off leakage current Output high level voltage Output low level voltage Output middle level voltage *2 OFFH V O =6.V V OH to 6 O =-μa V DD -. V DD -. V DD -.2 V OH 2 P to P O =-ma V DD -.9 V OH 3 to 7 O =-2μA V DD -.9 V OH 4 COM to COM4 O =-μa V DD -.9 V OL to 6 O =2μA.2.. V OL 2 P to P O =ma.9 V OL 3 to 7 O =2μA.9 V OL 4 COM to COM4 O =μa.9 V OL O =ma..3 V MD to 7 /3 bias O =±2μA 2/3V DD -.9 V MD 2 to 7 /3 bias O =±2μA /3V DD -.9 V MD 3 COM to COM4 /3 bias O =±μa 2/3V DD -.9 V MD 4 COM to COM4 /3 bias O =±μa /3V DD -.9 Oscillator frequency f OC OC R OC =39kΩ, C OC =pf RC oscillation operating mode Current drain 2/3V DD +.9 /3V DD +.9 2/3V DD +.9 /3V DD +.9 μa μa 6. μa khz DD V DD leep mode DD 2 V DD V DD =6.V, Output open, RC oscillation operating mode, f OC =38kHz DD 3 V DD V DD =6.V, Output open, External clock operating mode, f C =38kHz, V H 3=.V DD, V L 3=.V DD 4 9 Note: *2. Excluding the bias voltage generation divider resistor built into the and. (ee [Figure ]) V V V μa To the common and segment drivers Excluding these resistors [Figure ] No.A39-3/36

4 . When is stopped at the low level LC7886PW VH VL V H % V L tφh tφl V H V L tr tf tcp tcs tch tds tdh tdc tdr D D [Figure 2] 2. When is stopped at the high level VH VL tφl tφh V H % V L tf tr V H V L tcp tcs tch tds tdh D D [Figure 3] tdc tdr 3. OC pin clock timing in external clock operating mode OC V H 3 % V L 3 tch [Figure 4] t fc= DC= tch + t tch tch + t [khz] [%] No.A39-4/36

5 Package Dimensions unit : mm (typ) max... ANYO : QFP8(2X2) Pin Assignment 4 3 2/6 / COM4/4 COM3 COM2 COM /P V TET OC RE P/ P2/ LC7886PW P3/3 P4/ Top view No.A39-/36

6 Block Diagram COM4/4 COM3 COM2 COM COMMON DRVER V OC OC GENERATOR CCB NTERFA /2 / 3 4/P4 3/P3 2/P2 /P P/7 EGMENT DRVER & LATCH GENERAL PURPOE PORT CONTROL REGTER HFT REGTER EY BUFFER RE EY CAN VDET TET No.A39-6/36

7 Pin Functions Handling ymbol Pin No. Function Active /O when unused /P to 4/P4 to 3 79,8,,2 3 to COM to COM3 2 to 4 COM4/4 / 6 2/6 7 3 to 6 8 to 6 to 62 to 66 P/7 67 OC 73 egment outputs for displaying the display data transferred by serial data input. The /P to 4/P4 pins can be used as general-purpose output ports under serial data control. - O OPEN Common driver outputs. The frame frequency is f O [Hz]. - O OPEN The COM4/4 pin can be used as a segment output in /3 duty. ey scan outputs. Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMO transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The / - O OPEN and 2/6 pins can be used as segment outputs when so specified by the control data. ey scan inputs. These pins have built-in pull-down resistors. H GND General-purpose output port. This pin can be used as clock output port or segment output port under - O OPEN serial data control. Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. This pin can also be used as the external clock input pin if the external clock operating mode is selected with - /O V DD the control data. 76 erial data interface connections to the controller. Note that, being an open-drain output, requires a pull-up resistor. H 77 : Chip enable GND 78 7 : ynchronization clock : Transfer data : Output data - - O OPEN RE 74 Reset signal input RE=Low Display off - /P to 4/P4, /, 2/6=Low (These pins are forcibly set to the segment output port function and fixed at the low level.) - to 3=Low - COM to COM3=Low - COM4/4=Low (This pin is forcibly set to the common output function and fixed at the low level.) - P/7=Low (This pin is forcibly set to the general-purpose output port function and fixed at the low level.) L V DD - 3 to 6=Low - ey scanning disabled - All the key data is reset to low. - OC= Z (High impedance) - RC oscillation stopped - nhibits external clock input RE=High Display on - General-purpose output port state setting is enabled - ey scanning is enabled. - RC oscillation enabled (RC oscilltator operating mode) - Enables external clock input (external clock operating mode) However, serial data can be transferred when the RE pin is low TET 72 This pin must be connected to ground. - - V DD 69 Used to apply the LCD drive 2/3 bias voltage externally. - OPEN V DD 2 7 Used to apply the LCD drive /3 bias voltage externally. - OPEN V DD 68 Power supply connections. Provide a voltage of between 4. to 6.V V 7 Power supply connections. Connect to ground No.A39-7/36

8 erial Data nput. /4 duty () When is stopped at the low level D D2 D47 D48 D49 D D D2 D3 D4 D D6 OC PC PC C P P P2 C B B B2 B3 A A A2 A3 Display data (6 bits) Control data (3 bits) DD (3 bits) D7 D8 B B B2 B3 A A A2 A3 D3 D4 D D6 D7 D8 D9 D D D2 Display data (6 bits) FC FC FC2 Control data (3 bits) DD (3 bits) B B B2 B3 A A A2 A3 D3 D4 D9 D6 D6 D62 D63 D64 D6 D66 D67 D68 Display data (6 bits) Fixed data (3 bits) DD (3 bits) B B B2 B3 A A A2 A3 D69 D7 D2 D26 D27 D28 D29 D22 D22 D222 D223 D224 Display data (6 bits) Fixed data (3 bits) DD (3 bits) Note: B to B3, A to A3 DD Direction data No.A39-8/36

9 (2) When is stopped at the high level D D2 D47 D48 D49 D D D2 D3 D4 D D6 OC PC PC C P P P2 C B B B2 B3 A A A2 A3 Display data (6 bits) Control data (3 bits) DD (3 bits) D7 D8 D3 D4 D D6 D7 D8 D9 D D D2 FC FC FC2 B B B2 B3 A A A2 A3 Display data (6 bits) Control data (3 bits) DD (3 bits) D3 D4 D9 D6 D6 D62 D63 D64 D6 D66 D67 D68 B B B2 B3 A A A2 A3 Display data (6 bits) Fixed data (3 bits) DD (3 bits) D69 D7 D2 D26 D27 D28 D29 D22 D22 D222 D223 D224 B B B2 B3 A A A2 A3 Display data (6 bits) Fixed data (3 bits) DD (3 bits) Note: B to B3, A to A3 DD Direction data 42H D to D224 Display data OC RC oscillator operating mode/external clock operationg mode switching control data PC, PC General-purpose output port/clock output port/segment output port switching control data C ey scan operation enabled/disabled state setting control data, leep control data, ey scan output/segment output switching control data P to P2 egment output port/general-purpose output port switching control data C egment on/off control data FC to FC2 Common and segment output waveform frame frequency control data No.A39-9/36

10 2. /3 duty () When is stopped at the low level LC7886PW D D2 D47 D48 D49 D D D2 D3 D4 D D6 D7 OC PC PC C P P P2 C B B B2 B3 A A A2 A3 Display data (7 bits) Control data (2 bits) DD (3 bits) B B B2 B3 A A A2 A3 D8 D9 D4 D D6 D7 D8 D9 D D D2 D3 D4 Display data (7 bits) FC FC FC2 Control data (2 bits) DD (3 bits) B B B2 B3 A A A2 A3 D D6 D6 D62 D63 D64 D6 D66 D67 D68 D69 D7 D7 Display data (7 bits) Fixed data (2 bits) DD (3 bits) Note: B to B3, A to A3 DD Direction data No.A39-/36

11 (2) When is stopped at the high level LC7886PW D D2 D47 D48 D49 D D D2 D3 D4 D D6 D7 OC PC PC C P P P2 C B B B2 B3 A A A2 A3 Display data (7 bits) Control data (2 bits) DD (3 bits) B B B2 B3 A A A2 A3 D8 D9 D4 D D6 D7 D8 D9 D D D2 D3 D4 Display data (7 bits) FC FC FC2 Control data (2 bits) DD (3 bits) B B B2 B3 A A A2 A3 D D6 D6 D62 D63 D64 D6 D66 D67 D68 D69 D7 D7 Display data (7 bits) Fixed data (2 bits) DD (3 bits) Note: B to B3, A to A3 DD Direction data 42H D to D7 Display data OC RC oscillator operating mode/external clock operationg mode switching control data PC, PC General-purpose output port/clock output port/segment output port switching control data C ey scan operation enabled/disabled state setting control data, leep control data, ey scan output/segment output switching control data P to P2 egment output port/general-purpose output port switching control data C egment on/off control data FC to FC2 Common and segment output waveform frame frequency control data No.A39-/36

12 Control Data Functions. OC RC oscillator operating mode/external clock operating mode switching control data This control data bit selects the OC pin function (RC oscillator operating mode or external clock operating mode) OC OC pin function RC oscillator operating mode External clock operating mode Note: f RC oscillator operating mode is selected, connect an external resistor ROC and an external capacitor COC to the OC pin. 2. PC, PC General-purpose output port/clock output port/segment output port switching control data These control data bits swithes the functions of the P/7 output pin between the general-purpose output port, the clock output port, and the segment output port. Control data PC PC The state of P/7 output pin General-purpose output port (P) ( L level output) General-purpose output port (P) ( H level output) Clock output port (P) (Clock frequency is f OC /2 or f C /2) egment output port (7) Note: f the sleep mode is set, the P/7 output pin can not be used as the clock output port. 3. C ey scan operation enabled/disabled state setting control data This control data bit enables or disables key scan operation. C ey scan operating state ey scan operation enabled (A key scan operation is performed if any key on the lines corresponding to to 6 pin which is set high is pressed.) ey scan operation disabled (No key scan operation is performed, even if any of the keys in the key matrix are pressed. f this state is set up, the key data is forcibly reset to and the key data read request is also cleared. ( is set high.)) 4., leep control data These control data bits switch between normal mode and sleep mode, and set the states of the to 6 key scan output during key scan standby. Control data Mode OC pin state (RC oscillator or acceptance of the external clock signal) egment output / Common output Output pin states during key scan standby Normal Operating Operating H H H H H H leep topped L L L L L L H leep topped L L L L L H H leep topped L H H H H H H Note: This assumes that the / and 2/6 output pins are selected for key scan output. No.A39-2/36

13 ., ey scan output/segment output switching control data These control data bits switch the functions of the / and 2/6 output pins between the key scan output and the segment output. Control data Output pin state / 2/6 Maximum number of input keys X 6 2 X : don't care Note: n (n= or 2): ey scan output n (n= or 6): egment output 6. P to P2 egment output port/general-purpose output port switching control data These control data bits switch the functions of the /P to 4/P4 output pins between the segment output port and the general-purpose output port. Control data Output pin state P P P2 /P 2/P2 3/P3 4/P P P P2 3 4 P P2 P3 4 Note: n (n= to 4): egment output port Pn (n= to 4): General-purpose output port P P2 P3 P4 The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. Output pin Correspondence display data /4 duty /3 duty /P D D 2/P2 D D4 3/P3 D9 D7 4/P4 D3 D For example, if the circuit is operated in /4 duty and the 4/P4 output pin is selected to be a general-purpose output port, the 4/P4 output pin will output a high level when the display data D3 is, and will output a low level when D3 is. 7. C egment on/off control data This control data bit controls the on/off state of the segments. C Display state On Off However, note that when the segments are turned off by setting C to, the segments are turned off by outputting segment off waveforms from the segment output pins. 8. FC to FC2 Common and segment output waveform frame frequency control data These control data bits set the common and segment output waveform frequency. Control data FC FC FC2 Frame frequency f O [Hz] f OC /768, f C /768 f OC /76, f C /76 f OC /384, f C /384 f OC /288, f C /288 f OC /92, f C /92 No.A39-3/36

14 Display Data and Output Pin Correspondence. /4 duty Output pin COM COM2 COM3 COM4 Output pin COM COM2 COM3 COM4 /P D D2 D3 D4 29 D3 D4 D D6 2/P2 D D6 D7 D8 3 D7 D8 D9 D2 3/P3 D9 D D D2 3 D2 D22 D23 D24 4/P4 D3 D4 D D6 32 D2 D26 D27 D28 D7 D8 D9 D2 33 D29 D3 D3 D32 6 D2 D22 D23 D24 34 D33 D34 D3 D36 7 D2 D26 D27 D28 3 D37 D38 D39 D4 8 D29 D3 D3 D32 36 D4 D42 D43 D44 9 D33 D34 D3 D36 37 D4 D46 D47 D48 D37 D38 D39 D4 38 D49 D D D2 D4 D42 D43 D44 39 D3 D4 D D6 2 D4 D46 D47 D48 4 D7 D8 D9 D6 3 D49 D D D2 4 D6 D62 D63 D64 4 D3 D4 D D6 42 D6 D66 D67 D68 D7 D8 D9 D6 43 D69 D7 D7 D72 6 D6 D62 D63 D64 44 D73 D74 D7 D76 7 D6 D66 D67 D68 4 D77 D78 D79 D8 8 D69 D7 D7 D72 46 D8 D82 D83 D84 9 D73 D74 D7 D76 47 D8 D86 D87 D88 2 D77 D78 D79 D8 48 D89 D9 D9 D92 2 D8 D82 D83 D84 49 D93 D94 D9 D96 22 D8 D86 D87 D88 D97 D98 D99 D2 23 D89 D9 D9 D92 D2 D22 D23 D24 24 D93 D94 D9 D96 2 D2 D26 D27 D28 2 D97 D98 D99 D 3 D29 D2 D2 D22 26 D D2 D3 D4 / D23 D24 D2 D26 27 D D6 D7 D8 2/6 D27 D28 D29 D22 28 D9 D D D2 P/7 D22 D222 D223 D224 Note: This is for the case where the /P to 4/P4, /, 2/6, P/7 output pins are selected for use as segment outputs. For example, the table below lists the segment output states for the output pin. Display data D4 D42 D43 D44 Output pin state () The LCD segments for COM, COM2, COM3 and COM4 are off. The LCD segment for COM4 is on. The LCD segment for COM3 is on. The LCD segments for COM3 and COM4 are on. The LCD segment for COM2 is on. The LCD segments for COM2 and COM4 are on. The LCD segments for COM2 and COM3 are on. The LCD segments for COM2, COM3 and COM4 are on. The LCD segment for COM is on. The LCD segments for COM and COM4 are on. The LCD segments for COM and COM3 are on. The LCD segments for COM, COM3 and COM4 are on. The LCD segments for COM and COM2 are on. The LCD segments for COM, COM2 and COM4 are on. The LCD segments for COM, COM2 and COM3 are on. The LCD segments for COM, COM2, COM3 and COM4 are on. No.A39-4/36

15 2. /3 duty LC7886PW Output pin COM COM2 COM3 Output pin COM COM2 COM3 /P D D2 D3 3 D9 D92 D93 2/P2 D4 D D6 32 D94 D9 D96 3/P3 D7 D8 D9 33 D97 D98 D99 4/P4 D D D2 34 D D D2 D3 D4 D 3 D3 D4 D 6 D6 D7 D8 36 D6 D7 D8 7 D9 D2 D2 37 D9 D D 8 D22 D23 D24 38 D2 D3 D4 9 D2 D26 D27 39 D D6 D7 D28 D29 D3 4 D8 D9 D2 D3 D32 D33 4 D2 D22 D23 2 D34 D3 D36 42 D24 D2 D26 3 D37 D38 D39 43 D27 D28 D29 4 D4 D4 D42 44 D3 D3 D32 D43 D44 D4 4 D33 D34 D3 6 D46 D47 D48 46 D36 D37 D38 7 D49 D D 47 D39 D4 D4 8 D2 D3 D4 48 D42 D43 D44 9 D D6 D7 49 D4 D46 D47 2 D8 D9 D6 D48 D49 D 2 D6 D62 D63 D D2 D3 22 D64 D6 D66 2 D4 D D6 23 D67 D68 D69 3 D7 D8 D9 24 D7 D7 D72 COM4/4 D6 D6 D62 2 D73 D74 D7 / D63 D64 D6 26 D76 D77 D78 2/6 D66 D67 D68 27 D79 D8 D8 P/7 D69 D7 D7 28 D82 D83 D84 29 D8 D86 D87 3 D88 D89 D9 Note: This is for the case where the /P to 4/P4, COM4/4, /, 2/6, P/7 output pins are selected for use as segment outputs. For example, the table below lists the segment output states for the output pin. Display data D3 D32 D33 Output pin state () The LCD segments for COM, COM2, and COM3 are off. The LCD segment for COM3 is on. The LCD segment for COM2 is on. The LCD segments for COM2 and COM3 are on. The LCD segment for COM is on. The LCD segments for COM and COM3 are on. The LCD segments for COM and COM2 are on. The LCD segments for COM, COM2 and COM3 are on. No.A39-/36

16 erial Data Output. When is stopped at the low level B B B2 B3 A A A2 A3 X Note: B to B3, A to A3 D D2 Output data D27 D28 D29 D3 A X: don t care 2. When is stopped at the high level B B B2 B3 A A A2 A3 X D Note: B to B3, A to A3 D2 43H D to D3 ey data A leep acknowledge data Note: f a key data read operation is executed when is high ( does not generate a key data read request output), the read key data (D to D3) and sleep acknowledge data (A) will be invalid. D3 Output data D28 D29 D3 A X X: don t care Output Data. D to D3 ey data When a key matrix of up to 3 keys is formed from the to 6 output pins and to input pins and one of those keys is pressed, the key output data corresponding to that key will be set to. The table shows the relationship between those pins and the key data bits / D D2 D3 D4 D 2/6 D6 D7 D8 D9 D 3 D D2 D3 D4 D 4 D6 D7 D8 D9 D2 D2 D22 D23 D24 D2 6 D26 D27 D28 D29 D3 When the / and 2/6 output pins are selected to be segment outputs by control data bits and and a key matrix of up to 2 keys is formed using the 3 to 6 output pins and the to input pins, the D to D key data bits will be set to. 2. A leep acknowledge data This output data bit is set to the state when the key was pressed. Also, while will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. A will be in sleep mode and in normal mode. No.A39-6/36

17 leep Mode Functions leep mode is set up by setting or in the control data to. When sleep mode is set up, both the segment and common outputs will go to the low level. n RC oscillator operating mode (OC=), the oscillator on the OC pin will stop (although it will operate during key scan operations), and in exeternal clock operating mode (OC=), acceptance of the external clock signal on the OC pin will stop (although the clock signal will be accepted during key scan operations). Thus this mode reduces power consumption. However, the /P to 4/P4, P/7 output pins can be used as general-purpose output ports under control of the P to P2, PC and PC bits in the control data even in sleep mode (The P/7 output pin can not be used as clock output port). leep mode is cancelled by setting both and in control data to. ey can Operation Functions. ey scan timing The key scan period is 288T[s]. To reliably determine the on/off state of the keys, the LC7886PW scans the keys twice and determines that a key has been pressed when the key data agrees. t outputs a key data read request (a low level on ) 6T[s] after starting a key scan. f the key data does not agree and a key was pressed at that point, it scans the keys again. Thus the LC7886PW cannot detect a key press shorter than 6T[s]. *3 *3 2 *3 2 2 *3 3 *3 3 3 *3 4 *3 4 4 *3 *3 * T= = foc fc ey on 76T[s] Note: *3. These are set to the high or low level by the and bits in the control data. ey scan output signals are not output from pins that are set to the low level. No.A39-7/36

18 2. Normal mode, when key scan operations are enabled () The to 6 pins are set high. (ee the description of the control data.) (2) When a key is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. (3) f a key is pressed for longer than 6T[s] (Where T=/fOC or T=/fC), the LC7886PW outputs a key data read request (a low level on ) to the controller. The controller acknowledges this request and reads the key data. However, if is high during a serial data transfer, will be set high. (4) After the controller reads the key data, the key data read request is cleared ( is set high) and the LC7886PW performs another key scan. Also note that, being an open-drain output, requires a pull-up resistor (between and kω). ey input ey input 2 ey scan 6T[s] 6T[s] 6T[s] erial data transfer (C=) erial data transfer (C=) ey address(43h) erial data transfer (C=) ey address(43h) ey address(43h) ey data read request 3. leep mode, when key scan operations are enabled () The to 6 pins are set to high or low level by the and bits in the control data. (ee the description of the control data.) (2) f a key on one of the lines corresponding to a to 6 pin which is set high is pressed, the oscillator on the OC pins starts in RC oscillator operating mode (the C starts accepting the external clock signal in external clock operating mode) and a key scan is performed. eys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. (3) f a key is pressed for longer than 6T[s] (Where T=/fOC or T=/fC), the LC7886PW outputs a key data read request (a low level on ) to the controller. The controller acknowledges this request and reads the key data. However, if is high during a serial data transfer, will be set high. (4) After the controller reads the key data, the key data read request is cleared ( is set high) and the LC7886PW performs another key scan. However, this does not clear sleep mode. Also note that, being an open-drain output, requires a pull-up resistor (between and kω). () leep mode key scan example Example: =, = (leep with only 6 high) ey data read ey data read ey data read ey data read request ey data read request T= = foc fc L L 2 L 3 L 4 L H *4 When any one of these keys is pressed, the oscillator on the OC pins starts in RC oscillator operating mode (the C starts accepting the external clock signal in external clock operating mode) and a key scan operation is performed. Note: *4. These diodes are required to reliably recognize multiple key presses on the 6 line when sleep mode state with only 6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the 6 key scan output signal when keys on the to lines are pressed at the same time. No.A39-8/36

19 ey input (6 line) ey scan 6T[s] 6T[s] ey erial data transfer erial data transfer erial data transfer (C=) (C=) address(43h) (C=) ey address(43h) T= = foc fc ey data read request ey data read ey data read ey data read request 4. Normal/sleep mode, when key scan operations are disabled () The to 6 pins are set to high or low level by the and bits in the control data. (2) No key scan operation is performed, whichever key is pressed. (3) f the key scan disabled state (C= in the control data) is set during a key scan, the key scan is stopped. (4) f the key scan disabled state (C= in the control data) is set when a key data read request (a low level on ) is output to the controller, all the key data is set to and the key data read request is cleared ( is set high). Note that, being an open-drain output, requires a pull-up resister (between to kω). () The key scan disabled state is cleared by setting C in the control data to. ey input ey input 2 ey scan 6T[s] 6T[s] erial data transfer erial data transfer erial data transfer erial data transfer erial data transfer (C=) (C=) (C=) (C=) (C=) ey address(43h) ey data read request ey data read request ey data read T= = foc fc Multiple ey Presses Although the LC7886PW is capable of key scanning without inserting diodes for dual key presses, triple key presses on the to input pin lines, or multiple key presses on the to 6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more bits and ignore such data. No.A39-9/36

20 /4 Duty, /3 Bias Drive Technique fo[hz] COM COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM, COM2, COM3, and COM4 are turned off. LCD driver output when only LCD segments corresponding to COM are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM, COM2, and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM, COM2, COM3, and COM4 are on. V V V V V V V V V V V V V V V Control data Common and segment output waveform FC FC FC2 frame frequency f O [Hz] f OC /768, f C /768 f OC /76, f C /76 f OC /384, f C /384 f OC /288, f C /288 f OC /92, f C /92 No.A39-2/36

21 /3 Duty, /3 Bias Drive Technique fo[hz] COM COM2 COM3 LCD driver output when all LCD segments corresponding to COM, COM2, and COM3 are turned off. LCD driver output when only LCD segments corresponding to COM are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when all LCD segments corresponding to COM, COM2, and COM3 are on. V V V V V V V V V V V Control data Common and segment output waveform FC FC FC2 frame frequency f O [Hz] f OC /768, f C /768 f OC /76, f C /76 f OC /384, f C /384 f OC /288, f C /288 f OC /92, f C /92 No.A39-2/36

22 Clock ignal Output Waveform PC Control data PC The state of P/7 output pin Clock output port (P) (Clock frequency is f OC /2 or f C /2) P Tc/2 Tc= fc Tc Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e., when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.3V, typical. To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power supply voltage rise time when the power is first applied and the power supply voltage fall time when the voltage drops are both at least ms. (ee Figure and Figure 6.) ystem Reset The LC7886PW supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, all the key data is reset to low, and the general-purpose output ports are fixed at the low level (The /P to 4/P4 pins are forcibly set to the segment output port function and fixed at the low level. The P/7 pin is forcibly set to the general-purpose output port function and fixed at the low level). When the reset is cleared, display is turned on, key scanning is enabled and the general-purpose output ports state setting is enabled.. Reset methods () Reset method by the voltage detection type reset circuit (VDET) f at least ms is assured as the supply voltage rise time when power is applied, a system reset will be applied by the VDET output signal when the supply voltage is brought up. f at least ms is assured as the supply voltage fall time when power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (/4 duty: the display data D to D224 and the control data, /3 duty: the display data D to D7 and the control data) has been transferred, i.e., on the fall of the signal on the transfer of the last direction data, after all the direction data has been transferred. (ee Figure and Figure 6.) /4 duty t t2 VDET VDET VL D to D6 nternal data OC, PC, PC, C,,,,, P to P2, C Undefined Display and control data transfer Defined Undefined nternal data (D7 to D2, FC to FC2) Undefined Defined Undefined nternal data (D3 to D68) Undefined Defined Undefined nternal data (D69 to D224) Undefined Defined Undefined ystem reset period Note: t [ms](power supply voltage rise time) t2 [ms](power supply voltage fall time) [Figure ] No.A39-22/36

23 /3 duty t t2 VDET VDET VL D to D7 nternal data OC, PC, PC, C,,,,, P to P2, C Undefined Display and control data transfer Defined Undefined nternal data (D8 to D4, FC to FC2) Undefined Defined Undefined nternal data (D to D7) Undefined Defined Undefined ystem reset period Note: t [ms](power supply voltage rise time) t2 [ms](power supply voltage fall time) [Figure 6] (2) Reset method by the RE pin When power is applied, a system reset is applied by setting the RE pin low level. The reset is cleared by setting the RE pin high level after all the serial data (/4 duty: the display data D to D224 and the control data, /3 duty: the display data D to D7 and the control data) has been transferred. n the allowable operating range (=4. to 6.V), A reset is applied by setting the RE pin low level. and the reset is cleared by setting the RE pin high level 2. nternal block states during the reset period OC GENERATOR A reset is applied and either the OC pin oscillator is stopped or external clock reception is stopped COMMON DRVER, EGMENT DRVER & LATCH A reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. EY CAN A reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. EY BUFFER A reset is applied and all the key data is set to low. GENERAL PURPOE PORT A reset is applied, the circuit is set to the initial state. CCB NTERFA, HFT REGTER, CONTROL REGTER ince serial data transfer is possible, these circuits are not reset. No.A39-23/36

24 COM4/4 COM3 COM2 COM 3 4/P4 3/P3 2/P2 /P P/7 COMMON DRVER EGMENT DRVER & LATCH GENERAL PURPOE PORT V OC OC GENERATOR CONTROL REGTER HFT REGTER CCB NTERFA EY BUFFER RE EY CAN VDET TET Blocks that are reset /2 / No.A39-24/36

25 3. Pin states during the reset period Pin tate during reset /P to 4/P4 L * to 3 COM to COM3 COM4/4 L *6 /, 2/6 L * 3 to 6 L *7 P/7 L *8 OC Z *9 L L LC7886PW H * Note: *. These output pins are forcibly set to the segment output function and held low. *6. This output pin is forcibly set to the common output function and held low. *7. These output pins are forcibly held fixed at the low level. *8. This output pin is forcibly set to the general-purpose output port function and held low. *9. This /O pin is forcibly set to the high-impedance state. *.ince this output pin is an open-drain output, a pull-up resistor of between and kω is required. This pin remains high during the reset period even if a key data read operation is performed. Notes on the OC Pin Peripheral Circuit. RC oscillator operationg mode (Control data bit OC=) When RC oscillator operationg mode is selected, an external resistor ROC and an external capacitor COC must be connected between the OC pin and GND. OC ROC COC 2. External clock operating mode (Control data bit OC= ) When selecting the external clock operating mode, connect a current protection resistor Rg (4.7 to 47kΩ) between the OC pin and the external clock output pin (external oscillator). Determine the value of the resistance according to the maximum allowable current value of the external clock output pin. Also make sure that the waveform of the external clock is not excessively distorted. External clock output pin External oscillator Rg OC Note: Allowable current value at external clock output pin > Rg No.A39-2/36

26 ample Application Circuit /4 duty, /3 bias (for use with normal panels) (P) (P2) (P3) (P4) P (Genenal-purpose output port) Used with the backlight controller or other circuit. +V * V TET OC *3 COM COM2 COM3 4/COM4 * From the controller * To the controller To the controller power supply C.47μF *4 C C RE * / 2 / P/ P2/2 P3/3 P4/4 3 P/7 () (6) (7) LCD panel (up to 224 segments) ey matrix (up to 3 keys) Note: *. Add a capacitor to the power supply line so that the power supply voltage rise time when power is applied and the power supply voltage fall time when power drops are both at least ms, as the LC7886PW is reset by the VDET. *2. f the RE pin is not used for system reset, it must be connected to the power supply. *3. When RC oscillator operating mode is used, the external resistor ROC and the external capacitor COC must be connected between the OC pin and GND, and when external clock operating mode is selected the current protection resistor Rg (4.7 to 47kΩ) must be connected between the OC pin and the external clock output pin (external oscillator). (ee the section on the OC pin peripheral circuit.) *4. The pin, being an open-drain output, requires a pull-up resistor. elect a resistance (between to kω) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *. The pins to be connected to the controller (,,,, RE) can handle 3.3V or V. No.A39-26/36

27 ample Application Circuit 2 /4 duty, /3bias (for use with large panels) kω R kω C.47μF (P) (P2) (P3) (P4) P (Genenal-purpose output port) Used with the backlight controller or other circuit. +V * From the controller * To the controller To the controller power supply * C *4 C R R R V TET RE *2 4 OC * / 2 / COM COM2 COM3 4/COM4 P/ P2/2 P3/3 P4/4 3 P/7 () (6) (7) LCD panel (up to 224 segments) ey matrix (up to 3 keys) Note: *. Add a capacitor to the power supply line so that the power supply voltage rise time when power is applied and the power supply voltage fall time when power drops are both at least ms, as the LC7886PW is reset by the VDET. *2. f the RE pin is not used for system reset, it must be connected to the power supply. *3. When RC oscillator operating mode is used, the external resistor ROC and the external capacitor COC must be connected between the OC pin and GND, and when external clock operating mode is selected the current protection resistor Rg (4.7 to 47kΩ) must be connected between the OC pin and the external clock output pin (external oscillator). (ee the section on the OC pin peripheral circuit.) *4. The pin, being an open-drain output, requires a pull-up resistor. elect a resistance (between to kω) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *. The pins to be connected to the controller (,,,, RE) can handle 3.3V or V. No.A39-27/36

28 ample Application Circuit 3 /3 duty, /3 bias (for use with normal panels) (P) (P2) (P3) (P4) P (Genenal-purpose output port) Used with the backlight controller or other circuit. +V * From the controller * To the controller To the controller power supply C.47μF *4 C * C V TET RE *2 4 OC * / 2 / COM COM2 COM3 P/ P2/2 P3/3 P4/4 3 COM4/4 P/7 (4) () (6) (7) LCD panel (up to 7 segments) ey matrix (up to 3 keys) Note: *. Add a capacitor to the power supply line so that the power supply voltage rise time when power is applied and the power supply voltage fall time when power drops are both at least ms, as the LC7886PW is reset by the VDET. *2. f the RE pin is not used for system reset, it must be connected to the power supply. *3. When RC oscillator operating mode is used, the external resistor ROC and the external capacitor COC must be connected between the OC pin and GND, and when external clock operating mode is selected the current protection resistor Rg (4.7 to 47kΩ) must be connected between the OC pin and the external clock output pin (external oscillator). (ee the section on the OC pin peripheral circuit.) *4. The pin, being an open-drain output, requires a pull-up resistor. elect a resistance (between to kω) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *. The pins to be connected to the controller (,,,, RE) can handle 3.3V or V. No.A39-28/36

29 ample Application Circuit 4 /3 duty, /3bias (for use with large panels) kω R kω C.47μF (P) (P2) (P3) (P4) P (Genenal-purpose output port) Used with the backlight controller or other circuit. +V * From the controller * To the controller To the controller power supply * C *4 C R R R V TET RE *2 4 OC * / 2 / COM COM2 COM3 P/ P2/2 P3/3 P4/4 3 COM4/4 P/7 (4) () (6) (7) LCD panel (up to 7 segments) ey matrix (up to 3 keys) Note: *. Add a capacitor to the power supply line so that the power supply voltage rise time when power is applied and the power supply voltage fall time when power drops are both at least ms, as the LC7886PW is reset by the VDET. *2. f the RE pin is not used for system reset, it must be connected to the power supply. *3. When RC oscillator operating mode is used, the external resistor ROC and the external capacitor COC must be connected between the OC pin and GND, and when external clock operating mode is selected the current protection resistor Rg (4.7 to 47kΩ) must be connected between the OC pin and the external clock output pin (external oscillator). (ee the section on the OC pin peripheral circuit.) *4. The pin, being an open-drain output, requires a pull-up resistor. elect a resistance (between to kω) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *. The pins to be connected to the controller (,,,, RE) can handle 3.3V or V. Notes on Transferring Display Data from The Controller When using the LC7886PW in /4 duty, applications transfer the display data (D to D224) in four operations, and in /3 duty, they transfer the display data (D to D7) in three operations. n either case, applications should transfer all of the display data within 3ms to maintain the quality of displayed image. No.A39-29/36

30 Notes on the Controller ey Data Read Techniques. Timer based key data acquisition () Flowchart = L = L YE NO ey data read processing (2) Timing chart ey input ey on ey on ey scan t3 t4 t3 t3 t6 ey address t ey data read t t6 t t6 ey data read request Controller determination (ey on) t7 Controller determination (ey on) t7 Controller determination (ey off) t7 Controller determination (ey on) t7 Controller determination (ey off) t3 ey scan execution time when the key data agreed for two key scans. (6T[s]) t4 ey scan execution time when the key data did not agree for two key scans and the key scan was executed again. (23T[s]) t ey address (43H) transfer time t6 ey data read time T= = foc (3) Explanation n this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the state when is low every t7 period without fail. f is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t7 in this technique must satisfy the following condition. t7>t4+t+t6 f a key data read operation is executed when is high ( does not generate a key data read request output), the read key data (D to D3) and sleep acknowledge data (A) will be invalid. fc No.A39-3/36

31 2. nterrupt based key data acquistion () Flowchart LC7886PW = L = L YE NO ey data read processing Wait for at least t8 = L NO = H YE ey OFF (2) Timing chart ey input ey on ey on ey scan t3 t3 t4 t3 t6 ey address t ey data read t t6 t t6 t t6 ey data read request Controller determination (ey on) t8 Controller determination (ey off) Controller determination (ey on) t8 Controller determination (ey on) t8 Controller determination (ey on) t8 Controller determination (ey off) t3 ey scan execution time when the key data agreed for two key scans. (6T[s]) t4 ey scan execution time when the key data did not agree for two key scans and the key scan was executed again. (23T[s]) t ey address (43H) transfer time t6 ey data read time T= = foc (3) Explanation n this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the state when is low. f is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by checking the state when is low and reading the key data. The period t8 in this technique must satisfy the following condition. t8>t4 f a key data read operation is executed when is high ( does not generate a key data read request output), the read key data (D to D3) and sleep acknowledge data (A) will be invalid. fc No.A39-3/36

32 About Data Communication Method with The Controller. About data communication method of 4 line type CCB format The 4 line type CCB format is the data communication method of before. The LC7886PW must connect to the controller as followings. *6 *7 Controller (NT) Rup LC7886PW Note: *6. Connect the pull-up resistor Rup. elect a resistance (between to kω) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *7. The (NT) pin is an input port for the key data read request signal (a low level on ) detection. 2. About data communication method of 3 line type CCB format The 3 line type CCB format is the data communication method that made a common use of the data input in the data output. The LC7886PW must connect to the controller as followings. *6 *7 Controller (NT) O Rup LC7886PW Note: *6. Connect the pull-up resistor Rup. elect a resistance (between to kω) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *7. The (NT) pin is an input port for the key data read request signal (a low level on ) detection. n this case, Applications must transfer the data communication start command before the serial data input (CCB address 42H, display data and control data transfer) or serial data output ( 43H transfer, key data read) to avoid the collision of the data input signal and the data output signal. Then applications must transfer the data communication stop command when the controller wants to detect the key data read request signal (a low level on ) during a movement stop of the serial data input and the serial data output. <> Data communication start command () When is stopped at the low level (2) When is stopped at the high level / / H Command data H Command data <2> Data communication stop command () When is stopped at the low level (2) When is stopped at the high level / / H Command data H Command data No.A39-32/36

33 Data Communication Flowchart of 4 Line Type or 3 Line Type CCB Format. Flowchart of the initial setting when power is turned on. Power on (Applications must observe that the power supply rise time is at least ms.) Power supply stability (Applications must wait till the level of the power supply is stable) erial data input (Display and control data transfer) ystem reset clear (Display on, ey scanning is enabled, General-purpose output port state setting are enabled) Note: The flowchart of initial setting when power is turned on is same regardless of the 4 line type or 3 line type CCB format. Take explanation about "system reset" into account. 2. Flowchart of the serial data input Data communication start command transfer *8 erial data input (Display and control data transfer) NO The controller wants to detect the key data read request signal (a low level on ). YE Data communication stop command transfer *8 Note: *8. n the case of the 4 line type CCB format, the transfers of data communication start command and data communication stop command are unnecessary, and, in the case of the 3 line type CCB format, these transfers are necessary. 3. Flowchart of the serial data output NO The controller acknowledges the key data read request (When the is low, the is low) YE Data communication start command transfer erial data output (ey data and sleep acknowledge data read) *9 *2 Note: *9. n the case of the 4 line type CCB format, the transfer of data communication start command is unnecessary, and, in the case of the 3 line type CCB format, the transfer is necessary. *2. Because the serial data output has the role of the data communication stop command, it is not necessary to transfer the data communication stop command some other time. No.A39-33/36

34 Timing Chart of 4 Line Type and 3 Line Type CCB Format. Timing chart of 4 line type CCB format <Example > ey input ey off ey on ey scan ey scan execution *2 ey scan execution *2 (42H) (42H) (42H) (43H) erial data input (Display and control data transfer) ey data read request erial data output (ey data read) ey data read request <Example 2> ey input ey off ey on ey off ey on ey scan ey scan execution *2 ey scan execution *2 (42H) (42H) (42H) (43H) (43H) erial data input (Display and control data tranfer) ey data read request erial data output (ey data read) ey data read request erial data output (ey data read) <Example 3> ey input ey off ey on ey off ey scan ey scan execution *2 ey scan execution *2 (42H) (42H) (42H) (43H) (43H) ey data read request erial data input (Display and control data transfer) erial data output (ey data read) Note: *2. When the key data agrees for two key scans, the key scan execution time is 6T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 23T[s]. ey data read request erial data output (ey data read) T= = foc fc No.A39-34/36

35 2. Timing chart of 3 line type CCB format LC7886PW <Example > ey input ey off ey on ey scan ey scan execution *2 ey scan execution *2 / (42H) (42H) (42H) (43H) Data communication start command erial data input (Display and control data transfer) Data communication stop command ey data read request Data communication start command erial data output (ey data read) ey data read request <Example 2> ey input ey off ey on ey off ey on ey scan ey scan execution *2 ey scan execution *2 / (42H) (42H) (42H) (43H) (43H) Data communication start command erial data input (Display and control data transfer) Data communication stop command ey data read request Data communication start command erial data output (ey data read) Data communication start command ey data read request erial data output (ey data read) <Example 3> ey input ey off ey on ey off ey scan ey scan execution *2 ey scan execution *2 / (42H) (42H) (42H) (43H) (43H) ey data read request Data communication start command erial data input (Display and control data transfer) erial data output (ey data read) ey data read request Data communication start command erial data output (ey data read) Note: *2. When the key data agrees for two key scans, the key scan execution time is 6T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 23T[s]. T= = foc fc No.A39-3/36