Virtual Memory and Interrupts

Transcription

1 Constructive Computer Architecture Virtual Memory and Interrupts Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology November 13, L21-1

2 Address Translation: putting it all together Virtual Address TLB Lookup hardware hardware or software software miss hit Page Table Walk Protection Check the page is memory memory denied permitted Page Fault (OS loads page) Update TLB Protection Fault Physical Address (to cache) Where? Resume the instruction November 13, 2015 SEGFAULT L21-2

3 Address Translation in Pipeline Machines PC Inst TLB Inst. Cache D Decode E M Data + TLB Data Cache W TLB miss? Page Fault? Protection violation? TLB miss? Page Fault? Protection violation? Software handlers need a restartable exception on page fault or protection violation Handling a TLB miss needs a hardware or software mechanism to refill TLB Methods to overcome the additional latency of a TLB: slow down the clock pipeline the TLB and cache access virtual address caches parallel TLB/cache access November 13, L21-3

4 Physical vs Virtual Address Caches? CPU VA TLB Physical Cache PA Primary Memory Alternative: place the cache before the TLB VA CPU Virtual Cache TLB PA Primary Memory (StrongARM) One cycle in case of a hit (+) cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) aliasing problems due to the sharing of pages (-) November 13, L21-4

5 Aliasing in Virtual-Address Caches Page Table Tag Data VA 1 Data Pages VA 1 1st Copy of Data at PA PA VA 2 2nd Copy of Data at PA VA 2 Two virtual pages share one physical page Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General Solution: Disallow aliases to coexist in cache Software (i.e., OS) solution for direct-mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in directmapped cache (early SPARCs) November 13, L21-5

6 VA Concurrent Access to TLB & Cache VPN L b Virtual Index PA TLB PPN Page Offset k Direct-map Cache 2 L blocks 2 b -byte block Tag hit? = Physical Tag Data Index L is available without consulting the TLB cache and TLB accesses can begin simultaneously Tag comparison is made after both accesses are completed Cases: L + b = k L + b < k L + b > k what happens here? Partially VA cache! November 13, L21-6

7 Virtual-Index Physical-Tag Caches: Associative Organization VA VPN L = k-b b W ways Virtual Index TLB k Direct-map 2 L blocks Direct-map 2 L blocks PA PPN Page Offset Phy. Tag Tag = hit? = After the PPN is known, W physical tags are compared Data Allows cache size to be greater than 2 L+b bytes November 13, L21-7

8 Exception handling in a pipeline machine November 13, L21-8

9 Exception Handling Commit Point PC Inst. Mem D Decode E + M Data Mem W PC address Exception Ex D Illegal Opcode Ex E Overflow Ex M Data address Exceptions Cause Select Handler PC Kill F Stage PC D Kill D Stage PC E Kill E Stage PC M External Interrupts EPC Kill Writeback 1. An instruction may cause multiple exceptions; which one should we process? from the earliest stage 2. When multiple instructions are causing exceptions; which one should we process first? from the oldest instruction November 13, L21-9

10 Interrupt processing Internal interrupts can happen at any stage but cause a redirection only at Commit External interrupts are considered only at Commit If an instruction causes an interrupt then the external interrupt, if present, is given a priority and the instruction is executed again Some instructions, like Store, cannot be undone once launched. So an instruction is considered to have completed before an external interrupt is taken November 13, L21-10

11 Exception Handling When instruction x in stage i raises an exception, its cause is recorded and passed down the pipeline For a given instruction, exceptions from the later stages of the pipeline do not override cause of exception from the earlier stages If an exception is present at commit: Cause and EPC registers are set, and pc is redirected to the handler PC Epoch mechanism takes care of redirecting the pc November 4, L19-11

12 Epoch PC Killing vs Poisoning Next Addr Pred f12f2 Inst Memory f2d wrong path insts are dropped Decode d2e scoreboard wrong path insts are poisoned Register File Execute e2m Data Memory This affects whether an instruction is removed from sb in case of an interrupt November 4, L19-12 m2c external interrupts considered at Commit

13 Interrupt processing at Execute Incoming Interrupt no yes -if (mem type) issue Ld/St -if (mispred) redirect -pass einst to M stage -pass einst to M stage unmodified einst will contain information about any newly detected interrupts at Execute November 13, L21-13

14 Interrupt processing at Memory stage -pass einst with modified data to Commit Incoming Interrupt no yes Memory Interrupt? no yes -pass new Cause to Commit -pass einst to Commit unmodified November 13, L21-14

15 Interrupt processing at Commit -commit -sb.rm External Interrupt? no yes Incoming interrupt Incoming interrupt no yes no yes EPC<= pc; causer <= incause; if (incause after Reg Fetch) sb.rm; mode <= privilege; Redirect commit; sb.rm; EPC<= ppc; causer <= Ext; mode <= privilege; Redirect EPC<= pc; causer <= Ext; if (incause after Reg Fetch) sb.rm; mode <= privilege; Redirect November 13, L21-15

16 Final comment There is generally a lot of machinery associated with a plethora of exceptions in ISAs Precise exceptions are difficult to implement correctly in pipelined machines Performance is usually not the issue and therefore sometimes exceptions are implemented using microcode The code slides follow November 4, L19-16

17 One-Cycle SMIPS rule doexecute; let inst = imem.req(pc); let dinst = decode(inst, csrf.getstatus); let rval1 = rf.rd1(frommaybe(?, dinst.src1)); let rval2 = rf.rd2(frommaybe(?, dinst.src2)); let einst = exec(dinst, rval1, rval2, pc,?); if(einst.itype == Ld) einst.data <- dmem.req(memreq{op: Ld, addr: einst.addr, data:?}); else if(einst.itype == St) let d <- dmem.req(memreq{op: St, addr: einst.addr, data: einst.data}); if (isvalid(einst.dst)) rf.wr(frommaybe(?, einst.dst), einst.data); setting special registers next address calculation endrule endmodule November 4, L19-17

18 Type: Decoded Instruction typedef struct { IType itype; AluFunc alufunc; BrFunc brfunc; Maybe#(RIndx) dst; Maybe#(RIndx) src1; Maybe#(RIndx) src2; Maybe#(Data) imm; Maybe#(CsrIndx) csr; } DecodedInst deriving(bits, Eq); typedef enum {Unsupported, NoPermit, Alu, Ld, St, J, Jr, Br,..., Syscall, ERet} IType deriving(bits, Eq); November 4, L19-18

19 Decode function DecodedInst decode(data inst, Status status); DecodedInst dinst =?;... opsystem: begin case (funct3)... fnpriv: begin // privilege inst dinst.itype = (case(inst[31:20]) fn12scall: Syscall; // sys call // ERET can only be executed under privilege mode fn12eret: isprivmode(status)? Eret : NoPermit; default: Unsupported; endcase); dinst.dst = Invalid; dinst.src1 = Invalid; dinst.src2 = Invalid; dinst.imm dinst.alufunc =?; dinst.brfunc = NT; end... endcase end... return dinst; endfunction = Invalid; November 4, L19-19

20 Set special registers if (einst.itype==syscall) begin csrf.setstatus(statuspushku(csrf.getstatus)); csrf.setcause(32 h08); // cause for System call csrf.setepc(pc); end else if (einst.itype==eret) begin cop.setstatus(statuspopku(cop.getstatus)); end November 4, L19-20

21 Redirecting PC if (einst.itype==syscall) pc <= csrf.gettvec; else if (einst.itype==eret) pc <= cop.getepc; else pc <= einst.brtaken? einst.addr : pc + 4; November 4, L19-21